JPS6042954B2 - electronic musical instruments - Google Patents

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to an improvement of an electronic musical instrument using a sound assignment method. [Prior Art] An electronic musical instrument using the sound assignment method includes a wave generator having a plurality of musical tone generation channels, and an assigner that assigns the sound of a pressed keyboard key to each channel of the wave generator. be done. [Problems to be Solved by the Invention] By the way, in conventional electronic musical instruments of this type, the assigner and the wave generator are directly connected, so the configuration of the wave generator cannot be easily changed. ,
Since both need to operate synchronously, there are design constraints. Furthermore, although the assigner and the wave generator are usually constructed of 151 separate chips, the above-mentioned conventional electronic musical instrument has the disadvantage that the number of wires between the two chips increases. [
Means for Solving the Problems] The present invention has been made to solve the above-mentioned drawbacks, and in accordance with the assignment of sounds to each channel, the assigner is configured to collect frequency data and information regarding the assigned sounds. The wave generator is configured to sequentially output the envelope data to the bus for each channel, and the wave generator is configured to store the frequency data and the envelope data sent to the bus for each channel, respectively; a first calculating means for calculating the frequency data stored in the storage means for each channel to form phase data for each channel and outputting the same in a time-division manner; a second calculation means that calculates envelope waveform data for each channel and outputs it in a time-division manner; It is characterized by comprising a tone waveform forming means for forming a tone waveform in a time-division manner. [Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. First, the basic principle of tone waveform formation used in this embodiment will be explained. First, in this embodiment, a musical sound waveform is formed digitally based on the frequency modulation calculation formula y=ASIN(ω. In equation (1), A determines the amplitude of the musical sound waveform. ωo is an element that determines the carrier wave frequency in frequency modulation, and ω1, ω2 and 11,
11 is an element that determines the frequency and amplitude of a modulated wave in frequency modulation. FIG. 1 is a diagram showing an example of a basic circuit configuration when forming a tone waveform based on the above equation (1), and in this figure, ACCl to ACC3 are all accumulators. These accumulators ACCl to ACC3 each accumulate phase increment values Δω1, Δω2, and Δωo supplied to each input terminal in accordance with a clock pulse of a constant period, and sequentially output the accumulated results. Both sine tables SINl and SIN2 are memories that store each instantaneous value of the sine waveform,
When the outputs of the accumulators ACCl and ACC2 are respectively supplied as address signals, the instantaneous values stored in the addresses corresponding to the same address signals are read out and sent to the multipliers Ml and M.
2, respectively. In the above configuration, for example, each instantaneous value of the sine wave for exactly one period is sequentially read from the sine table SINl during the period from when the accumulator ACCl starts accumulation from -RO to overflow. . In this case, the accumulation speed of the accumulator ACCl is constant because the frequency of the clock pulse is constant, and therefore, if the phase increment value Δω1 is constant, the sine table S
The period of the sine wave output from INl is constant. In other words, by changing the value of the phase increment value Δω1, the period (frequency) of the sine wave output from the sine table SINl can be changed. for example,
If the phase increment value Δω1 is made large, the period of the sine wave becomes small, and if the increment value Δω1 is made small, the period of the sine wave becomes large. Expressing the cumulative sum of
0INT is the initial value of each phase O Returning to FIG. It multiplies, and its output is sent to adder circuit A.
Supplied to U. Similarly, the multiplier M2 multiplies the output of the sine table SIN2 by the output of the numerical value generation circuit 12 that generates the 12th value in equation (1), and outputs the multiplication result to the addition circuit AU. Adder circuit AU includes multipliers Ml, M
2. Add each output of the accumulator ACC3, and supply the addition result to the sine table SIN3 as an address signal. Sign table SIN3 is the above-mentioned sign table SIN.
It has the same configuration as 1 and 2, and its output is supplied to the multiplier circuit M3. Multiplier M3 multiplies the output of sine table SIN3 by the output of numerical value generation circuit A that generates the value of A in equation (1), and outputs the multiplication result. As is clear from the above description, the output of each block shown in FIG. 1 corresponds to each of the following elements in equation (1). That is, the waveform shown in equation (1) is obtained as the output of the multiplier M3. Note that the output of the multiplier M3 is, of course, digital data. Therefore, in order to obtain a musical tone waveform, it is necessary to convert this data into an analog waveform using a D/A (digital/analog) converter. The basic configuration of the tone waveform forming circuit has been described above. Next, the process of forming tone waveforms in this embodiment will be described in more detail. In this embodiment, A, ω0, 11, 12 of the above equation (1)
, ω1, and ω2 are changed appropriately between the generation of the musical tone and the stop of the musical tone, thereby making the musical tone formed closer to the musical tone of a natural musical instrument. That is, in this embodiment, if the amplitude envelope of the musical sound waveform is shown in FIG.
2 is divided into eight segments 0 to 7, and each segment has the above, A, and ω. , 11, . . . are set as separate values (which may be the same value in some cases), and the tone waveform of equation (1) is formed based on the set values. In addition, in this case, within each segment, the above A, ll, l
Each value of 2 changes, and as a result, the musical tone waveform formed also changes sequentially within each segment 0 to 7. Changes in the values of A, 11, and 12 within each segment 0 to 7 are performed based on the following equations. Note that in these equations, ΔA, Δ11, and Δ12 are the increment values of A, ll, and l2 in equation (1), respectively, and A! N.T.
,ll! Nτ912! NT is the initial value of A9ll9l2.O Also, the time width of each segment 0 to 7 is
It is determined by segment data to be described later, that is, late count data RCDO-RCD7 and envelope count data ECDO-CD7. As is clear from the above, in this embodiment, in order to generate one tone waveform (tone waveform generated by one key operation), the following data (total 70W0RD: 1W0RD=16 bits). (4) Incremental value shown in Tables 1 and 2 (48W0RD
) (B) Initial value (6W0RD) A! NT9ll! NT9l2engineeringNTωO! NT9ω1! NT9ω21NT(C) Segment data (16W0RD) Late count data RC
DO-RCD7 Envelope Count Data ECDO Upper CD7 Therefore, in this embodiment, the above-mentioned (4) to (C
) are set in advance in the memory, and musical tones are formed by reading each data in the memory. For example, in the case of an electronic organ with one type of tone and 44 keys, each of the above-mentioned data is set in the memory for 44 countries. The above is the basic principle of musical tone formation used in this embodiment. Next, the electronic organ according to this embodiment will be explained in detail. FIG. 3 is a block diagram showing the configuration of the electronic organ. In this figure, reference numeral 101 is a tone lever for setting the tone, and 102 is a group of keys provided on the keyboard. In this embodiment, the tone lever 101 is composed of 1C@ levers, and w tone switches are provided corresponding to each lever. The output of each tone switch is then supplied to the key assigner 103, respectively. In this embodiment, the key group 102 is composed of 44 keys and 44 key switches corresponding to each key, and the output of each key switch is supplied to a key assigner 103. The key assigner 103 detects the currently set tone based on each output of the tone switch described above, and detects a newly pressed key or a released key based on the output of the key switch described above. do. When a newly pressed key is detected, the musical tone generation of the key is assigned to one of the channels (described later) of the wave generator 104 according to the present invention, and when a released key is detected. commands the channel to which the same key is assigned to stop sound generation. This key assigner 103 includes =RArVl (random access memory) 105 and ROM (read-on memory) 106.
are connected to each other. The RAMIO5 stores various data tables, data files, etc. used in channel assignment, and also stores the ROM,
6 includes programs used for detecting tone switches, detecting key presses and key releases, channel assignment, etc., and various data necessary for creating musical sound waves in the wave generator 104, that is, the above-mentioned (4) ) to (C) are stored. Ru. The wave generator 104 forms a musical sound waveform based on the basic principle described above, and is connected to the data boat 107 and the musical sound waveform forming section 1.
It consists of 08. In addition, the details of the data boat 107. is shown in FIG. 4, and details of the tone waveform forming section 108 are shown in FIGS. 5 to 7. This wave generator 104 has 16 channels (0th channel CHO to 15th channel CH) in this embodiment.
It has a tone waveform calculation string 15), and is designed to be able to simultaneously form 16 tone waveforms. However, the arithmetic section for calculating the tone waveform based on the equation (1) and the sine table described above each have one circuit, and these arithmetic sections and the sine table are used in two ways in a time-sharing manner. Next, the wave generator 104 shown in FIGS. 4 to 7 will be explained in detail. ) Outline of operation When any key in the key group 102 shown in FIG.
Allocate to an empty channel among 5. Next, the key assigner 103 corresponds to the pressed key,
The tone forming data (70W0RD) corresponding to the setting state of the tone lever 101 is read out from the ROM 106 and transferred to the incremental value data memory 1, initial value data memory 13, and segment data memory 15 shown in FIG. When this transfer is completed, a start command is output that instructs the channel to which sound generation is assigned to start sound generation. This start command is read into the start command register 30 shown in FIG. Start command register 3
When the start command is read at 0, 2 starts from the rising edge of the next clock pulse INITCLK (see Figure 8).
During 56 μSec (one period of INITCLK), the fourth
The data in the memories 11, 13, and 15 shown in the figure includes the envelope calculation memory 54, phase calculation memory 55, envelope increment value memory 66, phase increment value memory 67,
Transferred to segment count memory 76. and,
Tone waveform calculation is performed after this transfer is completed.
In this musical sound waveform calculation, the following three systems of calculations are performed in parallel. (1) Segment operation This operation is performed by the segment count memory 76 shown in FIG. 6, the circuit below it, the segment memory 22 shown in FIG.
The time of each of segments 0 to 7 shown in FIG. 2 is sequentially measured based on the segment data in FIG. 2, and the segment number currently being executed is sequentially output from the segment memory 22 shown in FIG. According to the segment number output from the memory 22, each of the incremental value data shown in the first and second tables described above is selected. (Ii) Envelope and phase calculation This calculation is the calculation of the above-mentioned equations (5) to (7) and equations (2) to (4), and the envelope calculation memory 5 phase calculation shown in FIG. This is done by an arithmetic memory 55, a circuit shown below these memories 54, 55, an envelope increment value memory 66 and a phase increment value memory 67. Then, the calculation results of equations (5) to (7) are sequentially supplied to the musical tone calculation circuit of FIG. 7 as ENVDATA15 to 0 shown in the lower part of FIG. The results of each calculation are shown in the lower part of Figure 6 as FREQDATA15~0.
The signal is sequentially supplied to the musical tone calculation circuit shown in FIG. (Ii
O musical sound waveform calculation This calculation is the calculation of the above-mentioned formula (1), and the seventh
This is performed by the musical tone calculation circuit shown in the figure. This musical tone arithmetic circuit operates according to the micro instructions in the micro program memory 47.
0 and FREQDATA15 to 0 are used to perform musical waveform calculations. Next, the musical tone ends as follows. When a pressed key in the key group 102 is released, the key assigner 103 outputs a Decay command or a Dump 5 command that instructs the end of the sound generation of the channel to which the released key is assigned. . The Decay command is read into the Decay command register 38 in FIG. 5, and the dump command is read into the Dump command register 4.
2. DAYK command is key assigner 10
When the tone waveform calculation is outputted from segment 3, no matter which of segments 0 to 4 the musical tone waveform calculation is in, it is forcibly transferred to segment 5, and thereafter the tone waveform calculations of segments 5 to 7 are performed. Further, if the musical waveform calculation at that time is in one of segments 5 to 7, the waveform calculation for each segment is executed sequentially. On the other hand, when a dump command is output from the key assigner 103, the musical tone rapidly decays at a constant speed, regardless of which segment the waveform calculation is performed at that time. Next, each of the above-mentioned operations and the configuration related to each operation will be explained. (2) Writing to memories 11, 13, 15 In FIG. 4, the master clock generator 1 generates four types of clock pulses MCLKl, MCL used in each part of the circuit.
This is a circuit that generates K2, MCLK3, and INITCLK. In FIG. 8, these clock pulses MCLKl~INI
TCLK waveforms and interrelationships are shown. Master counter 2 is a 10-bit binary counter that performs a counting operation according to master clock MCLKl, and its count output is output as address signals 1A5-0 and ISA9-6. Here, address signals IA5-0 are the 5th bit to 0th bit (lower 6 bits) of the count output,
Address signals 1SA9-1SA6 are the 9th bit to 6th bit (upper 4 bits) of the count output. The vibe line register 3 is a 10-bit register that is triggered by the clock pulse MCLKl, in other words, it reads input data at the timing of the clock pulse MCLKl. That is, this vibe line register 3 converts the output of the master counter 2 into one period (25
0r1 sec: This time is hereinafter referred to as base clock time) and is output with a delay. The output of this vibe line register 3 is the address signal P
ISA5~0 (lower 6 bits), PIA9~6 (higher 4 bits)
bits). Address decoder buffer 10 is a 10-bit register in which an address signal output from key assigner 103 (FIG. 3) and supplied via address bus 17 is temporarily stored. The incremental value data memory 11 is a memory in which the incremental value data (see Tables 1 and 2) output from the key assigner 103 and supplied via the data bus 18 is written, as shown in FIG. Channel CHO ~ Channel CH
It has a storage area corresponding to each of 15. For example, if the sound is assigned to channel CHO, the increment value data of 48W0RD shown in Tables 1 and 2 is output from the key assigner 103 and written in the area corresponding to channel CHO in FIG. . The initial value data memory 13 stores the initial values A4T, lllNT9l2! output from the key assigner 103. NT9ω01NT9
ω11NT9ω2! This is a memory in which NT is written, and as shown in FIG. 10, it has areas corresponding to each of channels CHO to CH15. The segment data memory 15 stores segment data output from the key assigner 103, that is, late count data RCDO-R.
CD7 and envelope count data ECDO top C
D7 is a memory to which data is written, and as shown in FIG. 11, it has areas corresponding to each of channels CHO to CH15. Each of the data selectors 4, 6, and 8 is a circuit that selectively outputs one of the data at the input terminal A or B, and performs the above selection in response to the memory selection signal MS output from the key assigner 103. The memory selection signal MS is a 3-bit signal, the 0th bit of which is supplied to the data selector 4 and the memory 11 (not shown), the 1st bit is supplied to the data selector 6 and the memory 13,
The second bit is also supplied to the data selector 8 and memory 15. Then, when the 0th bit of the signal MS becomes ゜゜1゛, the data selector 4 selects and outputs the data (address signal) of the input terminal B, and the memory 11
becomes ready for data writing. When the first and second bits of the signal MS each become "1", the data selectors 6 and 8 and the memories 13 and 15 operate in the same way.The address buffers 5, 7 and 9 are buffer amplifiers, In addition, each of the buffer registers 12, 14, and 16 receives input data within a base clock time (250r1sec).
This is a register that outputs with a delay. Now, assume that any key in the key group 102 shown in FIG. 3 is pressed, and in response to this key operation, the key assigner 103 assigns the sound of the pressed key to, for example, channel CHO. In this case, the key assigner 103 sequentially outputs each incremental value data of Tables 1 and 2 regarding the pressed key together with an address signal indicating each address of the area of channel CHO in FIG. Selection signal MS“
Outputs 00F゛ (0th bit is ゛゜1゛). The address signals output from the key assigner 103 are sequentially written into the address decoder buffer 10 via the address bus 17, and the written address signals are sequentially supplied to the memory 11 via the data selector 4 and address buffer 5. Ru. As a result, the incremental value data supplied to the memory 11 via the data bus 18 is sequentially written in the area corresponding to the chin HO shown in FIG. 9 in the state shown in the figure. Next, the key assigner 103 similarly sequentially outputs the initial value data and segment data together with the address signal and memory selection signal MS. As a result, each data is sequentially written in each area corresponding to the channel CHO of the memory 13 shown in FIG. 10 and the memory 15 shown in FIG. 11 in the state shown in the figure. ()Memory 11
, 13, 15 to memories 54, 55, 66, 6
Transferred to 7, 76 (Fig. 6) Fig. 12 A. Figure 12 shows the waveforms of clock pulses MCLKl and INITCLK, respectively. Figures ISA9-6, E, and F are diagrams showing address signals PIA5-0 and PISA9-6 respectively output from the vibe line register 3 of FIG. 4. As shown in this figure, address signals 1A5-0 and I
Both SA9-6 become ROJ at the rising edge of clock pulse INITCLK. In addition, the address signal PIA
5-0 and PISA9-6 are each address signal 1A
5-0 and ISA9-6 with 1 base clock time (
The signal is delayed (250 nsec). FIG. 12 is a diagram showing channel address signals ClIA3-0. These channel address signals CHA3-0 are signals output from the microprogram memory 47 shown in FIG. 7, and as shown in FIG.
When 0 is RO~3, RO is R4~7. When J.RL. ．．
R2J when r8~11J... Rl5 when R6O~63J
This is a 4-bit signal representing J. Each value of this channel address
For example, the channel address signal CHA
When 3-0 is ROJ, channel CHO processing is performed, and when R15J, channel CH15 processing is performed. When transferring data in the memories 11, 13, and 15 to the memories 54 to 76, each of the above address signals is used. Next, reading of each data in the memories 11, 13, and 15 will be explained. Each data in these memories 11, 13, and 15 is always read out in parallel except in the case of data writing described above. That is, except in the case of data writing described above, the memory selection signal MS becomes "0, 0, 0", and therefore the data selectors 4, 6, and 8 each output the data of the input terminal A. As a result, Address signals 1A5-0 and ISA9-6 output from the master counter 2 are supplied to each address terminal AD of the memories 11, 13, 15 via data selectors 4, 6, 8 and address buffers 5, 7, 9, As a result, each data in the memories 11, 13, and 15 is read out sequentially.However, the address signals supplied to the memory 11 are IA5-0 and ISA9-6, but the address signals supplied to the memory 13 are IA5-0 and ISA6 (6th bit signal of master count 2 output)
The address signals supplied to the memory 15 are IA5-1 (1st to 5th outputs of the master counter 2).
bit signals) and ISA8 to ISA6 (sixth to eighth bit signals). Next, the process of reading data in each memory 11, 13, 15 will be described in detail. (1) Memory 11 First, address signals 1A5-0 are set to 10. When RO is supplied as J, ISA9~6,
The data Δ110 (a) shown in FIG.
2), then RljIsA9 as IA5~0
When RO is supplied as ~6, the data Δ1 in FIG.
20[1] is read and 163J. is read as IA5-0.
．． When ROJ is supplied as ISA9-6, data Δ
Mr. [63] is read out. That is, when ISA9-6 is 70J, the envelope increment value data (Δ110, Δ120, ΔAO) of segment 0 of each channel CHO-CH15 is read.
Next, when ISA9-6 becomes r1yo, IA5-0 becomes R
While changing from O to B, each channel CHO
Envelope increment value data of segment 1 of ~CHl5 Δ111[[], Δ121[1a]...ΔA1[63]
a] is read out (see FIG. 12, H), and in the same manner, each envelope increment value data is sequentially read out. Next, I
When SA9~6 becomes 18jo (6"1000゛), IA
5-0 is RO-63. During the change over j, phase increment value data (Δω10, Δω9, Δω00) of segment 0 of each channel CHO to CHl5 are read out, and in the same manner, each phase increment value data is sequentially read out. As is clear from the above process, address signal 1SA8
Each of the values of ~6 corresponds to segments 0-7, and
6'0'' and '6r3 of the address signal 1SA9 are the 9th
This corresponds to areas EO and El shown in the figure. Each data read out through the above process is delayed by one base clock time and output by the batch register 12 (FIG. 4) (see FIG. 12). l) When the address signal 1SA6 of the memory 13 is "0", the data 111NT shown in FIG.

[0]~AINT[63
] (envelope initial value data) is read and if address signal 1SA6 is "r', address signals 1A5 to
While 0 changes from RO to 63J, the data ω10NTC01] to ω01NT[6311](
phase initial value data) is read out (see FIG. 12H). Then, each read data is delayed by one base clock time by the buffer register 14 and output (
(See Figure 12). 110 Memory 15 When the address signals 1SA8 to 1SA6 are RO, the data RCDOCO] to ECDO[31 shown in FIG.
) is read out, and if the address signals 1SA8-6 are r1, the data RCDl[[]-ECD in FIG.
1 [31a] is read out, and thereafter, each segment data is sequentially read out in the same way (see FIG. 12). That is, reading from the memory 15 is performed every two base clock times, and each value of address signals 1SA8-6 corresponds to segments 0-7, respectively. Each data read from the memory 15 is stored in a buffer register 16.
The signal is delayed by one base clock time and output (see FIG. 12). Next, a process in which data in the memories 11, 13, and 15 are transferred to the memories 54, 55, 66, 67, and 76 will be explained. Suppose now that the key assigner 103 assigns the sound of the pressed key to channel CHO. In this case, as described above, the key assigner 103 outputs various data corresponding to the pitch and timbre of the musical sound to be produced, and the memory 11, 13,
It writes to the area corresponding to channel CHO 15, and then outputs a start command "400...01" (16 bits). The 0th bit ゜゜1゛ in this start command instructs the start of channel CHO. After this start command is output,
Each envelope increment value data corresponding to channel CHO in area EO of memo I river 1 shown in FIG. 9 is transferred to envelope increment value memory 66 in FIG. 6, and also corresponds to channel CHO in area E1. Each phase increment value data is transferred to the phase increment value memory 67 shown in FIG. 6, and each envelope initial value data 5 (11) corresponding to the channel CHO in the memory 13 shown in FIG.
0N,,12,N,,A,N,) are transferred to the envelope calculation memory 54, and each phase initial value data (ω11NT, ω21
NT9ω0INT) are transferred to the phase calculation memory 55, and the channel CH of the memory 15 shown in FIG.
Each segment data corresponding to O is transferred to segment count memory 76. The above operation will be explained in detail below. When the aforementioned start command "00...01" is output from the key assigner 103, this start command is read into the start command register 30 (16 bits) shown in FIG. 5 via the data bus 18.
Next, when the clock pulse INITCLK rises, the output data of the start command register 30 is read into the init register 31 at this rising time, and the read data! data is provided to an init multiplexer 34. The input multiplexer 34 outputs the signal of the 0th bit of the manual data when the channel address signals CHA3 to CHA0 (FIG. 12) are RO.
When ~0 is R1J-R15J, signals of the 1st bit to 15th bit of the input data are output (parallel-to-serial conversion is performed). That is, when the data (start command) read into the init register 31 is 6400...0r2, the output signal of the init multiplexer 34 is 1NIT-1.
becomes the waveform shown in Fig. 12 (o). The pulse width of this signal 1NIT-1 is 1 μSec, and as shown in the opening of Figure 13, the clock pulse INITCLK (Figure 7313-A)
This occurs at least once during one period (256 μSec). When this signal 1NIT-1 occurs 16 times, the memory 54
~76 data writing is performed. This signal 1NIT-
1 is supplied to the set input terminal S of flip-flop 37 (FIG. 5). The flip-flop 37 is triggered by the clock pulse MCLKl and the signal 1NI
T-1 is delayed by 1 base clock time and the signal 1NI
Output as T (Figure 12 wa). And the above signal 1
Based on NIT-1 and INIT, data is written into the memories 54 to 76 in the following process. (1) Memories 66, 67 (Fig. 6) These memories 66, 67 are located in the area EO of Fig. 9, respectively.
, El, and has the same capacity as address signal PIA
5 to 0 (see FIGS. 4 and 12) are supplied as lower addresses, and address signals PSA8 to PSA 6 are supplied as upper addresses. Here, address signals PSA8 to PSA6 will be explained. The selector register 21 shown in FIG.
When 1 is ゜゛0゛, memory 2 is being supplied to human power terminal A.
2 is read at the timing of the clock pulse MCLKl, and when the signal 1NIT-1 is "゜1゛", the address signals ISA9 to ISA6 supplied to the input terminal B are read.
(FIG. 12D) is read at the timing of the RO clock pulse MCLKl. Then, the read signals are output as address signals PSA9 to PSA6. That is, the signal 1NI
When T-1 becomes "1", the address signals 1SA9-6 are delayed by one base clock time in the selector register 21 (therefore, they become the same signals as address signals PISA9-6), and are output as address signals PSA9-6. The address signals PSA8-6 supplied as upper addresses to the memories 66 and 67 are the lower three bits of the address signals PSA9-6 mentioned above.Next, the memory 6
The outputs of AND gates 68 and 69 are supplied to read/write terminals R/W 6 and 67, respectively. Further, a signal INIT is supplied to each first input terminal of AND gates 68 and 69, an address signal PSA9 is supplied to a second input terminal of AND gate 68 via an inverter 70, and a second input terminal of AND gate 69 is supplied with a signal INIT. An address signal PSA9 is directly supplied to the end. Here, the address signal PSA9 is the address signal 1SA
9 is a signal delayed by one base clock time by the selector register 21 (Fig. 5) (however, signal 1
Therefore, when the address signal PSA9 is '60', the data in the area EO in FIG. 9 is output from the buffer register 12 in FIG. 4,
When address signal PSA9 is 66r', data in area F1 in FIG. 9 is output from buffer array 1 register 12 in FIG. Now, the clock pulse INITCLK rises to the 6'F9 signal, and then the signal 1N indicated by the symbol P1 in FIG.
When IT is output, the signal PSA9 becomes “0” at that point.
゛The same signal 1NIT is connected to AND gate 68
The signal is supplied to the read/write terminal R/W of the memory 66 via. At this time, as shown in Figure 12, envelope increment value data (Δ110, Δ120
, ΔAO: Fig. 9) are sequentially outputted to the memory 66 (Fig.
(Fig.) is supplied to the data input terminal. Therefore, when the signal 1NIT indicated by the symbol P1 is output, the above-mentioned envelope increment value data is written into the memory J66.
Next, when the signal 1NIT indicated by P2 in FIG. 12 is output, the envelope increment value data (Δ111, Δ121, ΔA
1) are sequentially written into the memory 66, and hereinafter, the signal 1NIT
Each time the signal becomes a ゜゜1゛ signal, each envelope increment value data of segments 2, 3, . . . , 7 of channel CHO is sequentially written into the memory 66. Next, area E1 in Figure 9
When the data in the buffer register 12 (FIG. 4) is sequentially output, the address signal PSA9 is output as described above.
゛ becomes ゜゜1゛, therefore, the AND gate 69 becomes open and the signal INIT is supplied to the read/write terminal R/W of the memory 67. As a result, the signal IN
Every time IT is output, each phase increment value data (Δω109Δω20
9Δω00ゞΔω179Δω219Δω07: Figure 9)
are sequentially written into the memory 67. 1) Memories 54, 55 The initial value data output from the buffer register 14 in FIG. 4 is supplied to each input terminal A of the selector registers 51, 52 shown in FIG. The selector registers 51 and 52 each have an AND gate 51
When the outputs of the AND gates 51a and 52a are "1", the data of the input terminal A is read at the timing of the clock pulse MCLK3 (see Fig. 8), and when the outputs of the AND gates 51a and 52a are "0", the data of the input terminal B is read. The data of clock pulse MCLK
Load at timing 3. A signal 1 is input to each first input terminal of AND gates 51a and 52a.
NIT is supplied, address signal PISA6 is supplied to the second input terminal of AND gate 51a via inverter 50, and address signal PISA6 is directly supplied to the second input terminal of AND gate 52a. Here, when the address signal PISA6 is "0", the envelope initial value data (11!NT9) shown in FIG.
l2lNT9A! NT9) is output from the buffer register 14 in FIG. 4, and when the address signal PISA6 is "1", the phase initial value data (ω1!NT9ω2) in FIG.
! NT9ωO! NT) is output from the buffer register 14. As shown in FIG. 14, the memories 54 and 55 have areas corresponding to each of channels CHO to CH15, and each area is composed of 4 storage slots (20 bits per slot). In this case, four slots in each area are addressed by address signals PIAl,O, and each area is addressed by address signals PIAl,O.
Addressed by 5-2. These memories 54 and 55 read the outputs of the selector registers 51 and 52 at the timing of the rising edge of the clock pulse MCLKl. Therefore, the signal 1NIT indicated by the symbol P1 in FIG.
When is output, since the address signal PISA6 is ゜゜0゛ at the timing of this signal 1NIT,
Signal 1NIT is supplied to selector register 51 via AND gate 51a. As a result, the envelope initial value data (111NT, 111NT,
121NT, A0N, ) (see Figure 12) are sequentially read into the selector register 51, and then each read initial value data is sequentially read into the area corresponding to channel CHO of the memory 54. Next, the symbol P2 is shown in the 12th diagram.
When the signal INIT shown in is output, since the address signal PISA6 is ゜゛1゛ at this time, the signal INIT is output.
IT is connected to the selector register 5 via the AND gate 51a.
2. As a result, the channel CHO phase initial value data (ω1, NT, ω2, NT, ωoIT) output from the buffer register 14 at the signal 1NIT timing mentioned above
) are sequentially read into the selector register 52, and then each read initial value data is transferred to the channel CH of the memory 55.
They are sequentially read into the area corresponding to O. Thereafter, the exact same operation as described above is repeated every time the signal INIT is output. (Ii) Memory 76 The segment data output from the buffer register 16 in FIG. 4 is input to the input terminal A of the selector register 75 in FIG.
supplied to The selector register 75 has the same configuration as the selector registers 51 and 52 described above, and reads the data of the input terminal A at the timing of the clock pulse MCLK3 when the signal 4 is set to 1, and when the signal 1NIT is set to 0. Segment count memory 765 reads data from input terminal B at time.
is a memory having the same configuration as the memory 15 shown in FIG. 11, in which address signals PIA5-1 are supplied as lower addresses, address signals PSM8-6 are supplied as upper addresses, and clock pulse MCLKl rises on the evening of 4.
Read input data at the right time. When the signal 1MT indicated by the symbol P1 in FIG. 12 is output, the segment data (late count data rc
DO and envelope count data (ECDO) are sequentially read into selector register 75, and then the read data is sequentially read into segment counter memory 76. Hereafter, each time the signal INIT is output, the channel CHO
Each segment data of segments 1 to 7 is sequentially read into the memory 76. (4) Segment calculation Data transfer to the memories 54 to 76 described above is performed during one cycle of the clock pulse INITCLK (25
6 μSec). Then, the clock pulse INITCLK is 4"1"
When the voltage rises to 0, the data ゛00...01゛ in the init register 31 shown in FIG. 5 is read into the run register 32. Each of the 16 bits output from the run register 32 is inverted by an inverter 36 and supplied to each bit reset terminal of the init register 31 and start command register 30, respectively. As a result, the bits of the registers 30 and 31 corresponding to the "1" bit of the run register 32 are reset. Also, the "0" signal of the output (16 bits) of the inverter 36 is transmitted to the start command register 32. Input of the corresponding bit is prohibited. Also, the output of the run register 32 is sent to the run multiplexer 35.
supplied to The run multiplexer 35 uses the channel address signal CI
(When A3~0 is 0J, output the 0th bit signal of the run register 32, when CHA3~0 is r1, output the 1st bit signal of the run register 32,
At 5J, the signal of the 15th bit of the run register 32 is output (parallel-to-serial conversion is performed). The output of this run multiplexer 35 is the signal RUN-1
The signal is supplied to the reset terminal R of the flip-flop 37 as a signal. Flip-flop 37 delays signal RUN-1 by one base clock time and outputs it as signal RUN. Note that FIG. 13C shows the waveform of the signal RUN-1. When these signals RUN-1 and RUN are output, the corresponding channel (in the example of FIG. 13, channel CHO
) segment calculations, envelope and phase calculations, and tone waveform calculations are performed, thereby forming musical tones. The output of the run register 32 is also supplied to the key assigner 103 (FIG. 3) via the bus driver 33 and data bus 18. The “゜1” bit of this run register 32 is reset when musical tone formation is completed, and therefore the run register 32
The output indicates the channel where musical tone formation is currently being performed. The key assigner 103 uses this run register 32.
Based on the output of , it is detected whether musical tone formation is being performed in the current channel. Next, segment calculation will be explained. The segment memory 22 in FIG.
There are 0th to 15th memory slots (4 bits per slot) corresponding to HO to CHl5, respectively. 1L1 channel address signals CHA3 to 0 (see FIG. 15C) are supplied to the address terminal AD, and address signals 1A5 to A signal 1A1 of the first bit of 0 is supplied to the read/write terminal R/W. The data in the second 0th to 15th storage slots of this segment memory 22 are stored in channels CHO and CHO.
- Indicates the number of the segment currently being executed in CH15. For example, if the data in the 0th to 3rd storage slots are R3 and 121r5, respectively, then the current channels CHO to CH3 have segments 3 and 2, respectively.
, 5 shows that musical tone formation is occurring. The data read from this segment memory 22 is delayed by one base clock time by the selector register 21, and
It is output as address signals PSAj9 to PSAj6. Then, the lower 3 bits PSA of these address signals PSA9 to PSA
8 to 6 are supplied to address terminal AD2 of segment count memory 76 (FIG. 6). Note that this sector memory 22 is initially reset. Channel C now
When the sound generation is assigned to HO and then writing to the area corresponding to channel CHO of segment counter memory 76 is completed, the data in the 0th storage slot 1 corresponding to channel CHO of segment memory 22 is transferred to RO. It becomes u. Therefore, the signal RUN
-1 (Fig. 15 D) rises to "1", then the signal RU
At the time when N (FIG. 15) becomes ゜゜1゛, address signals PSA8 to PSA6 are ROJ, and this data R
O is the address terminal A of the segment count memory 76.
It is supplied to D2. In addition, address signals PlA5 to PlA1 (see FIG. 15) are sent to the address terminal ADl of the same memory 76.
is supplied. As a result, when the address signal PIA5~ is RO, the rate count data RCDO corresponding to channel CHO and segment 0 is read from the segment count memory 76, and the address signal PIA5~ is read out from the segment count memory 76.
When IA5-1 is RlJ, segment counter memory 7
Envelope count data ECDO corresponding to segment 0 and channel CHO is read from channel 6 (first
5) and is supplied to the distribution circuit 77. Distribution circuit 7
7 is a circuit that outputs input data from an output terminal A or B in accordance with a signal PIAl. At the time when the data RCDO is read from the segment counter memory 76, the signal PIAl (FIG. 15) is at '0', so that the data RCDO is output from the output terminal B of the distribution circuit 77. Here, in order to make the following explanation easier to understand, the data contents of the rate count data CD and envelope count data ECD and these data R
An overview of CD and ECD processing will be explained. First, the envelope count data ECD is, for example, 16-bit numerical data as shown in Table 3. Envelope count data ECD as shown in Table 3
In each segment, r1 is repeatedly subtracted from the initial value at a predetermined cycle, and when the subtraction result becomes RO, the segment ends and the next segment is started. For example, the data ECD regarding segment 0 is changed from the initial value Rl68 to Rl67 at a predetermined period. J, rl66. J
- r1yo and RlJ are sequentially decreased, and then the data ECD
is R.O. When reaching J, segment 0 ends. Also,
The late count data RCD is, for example, 16-bit data as shown in Table 4, but the lower 7 bits are RlJ from the envelope count data ECD mentioned above.
Numerical data that indicates the period of repeated subtraction, and
The 7th bit is a HOLD signal, and the upper 8 bits are data indicating the result of subtracting RlJ sequentially from the numerical value represented by the lower 7 bits. In this case, the HOLD signal is a control signal for sustaining musical tones in the same state, and in the case of sustained musical tones (organ sounds, etc.), the HOLD signal of rate count data RCD4 (rate count data corresponding to segment 4) becomes "1". Note that the HOLD signal becomes "1" only in this case. This late count data RCD
The numeric data of the lower 7 bits is initially transferred to the upper 8 bits of , and then becomes data indicating a value obtained by sequentially subtracting r'1 from this numeric value at a fixed timing. For example, in segment 0, since the lower 7 bits of data RCD are data R2lJ, the upper 8 bits of data will sequentially change R2lJ, r2O, Rl9, RlJ. When the data in the upper 8 bits of data RCD becomes ROJ, the numerical data in the lower 7 bits is again transferred to the upper 8 bits as is, and at this timing, the envelope count data EcD(7)RlJ is subtracted. I'm starting to repeat this. in this way,
By determining the time of each segment based on envelope count data ECD and rate count data RCD, the length of each segment can be finely and arbitrarily set using a small number of bits overall. In addition, in the following explanation,
Since each of the above data ECD and RCD is 7-complement data, subtraction of RlJ is performed by addition of RlJ. Now, the upper 8 bits of the rate count data RCDO output from the output terminal B of the distribution circuit 77 are applied to the input terminal A of the data selector 80, and the lower 7 bits are applied to the input terminal B of the data selector 80. In addition, the 7th bit of input terminal B of the selector 80 is “
゜0゛ is applied. The data selector 80 outputs the data of the human input terminal B when the output of the NOR circuit 83 which takes the NOR of each bit of the data supplied to the input terminal A is "1", and outputs the data of the human input terminal A when the output is "0". Output data. In this case, since the upper 8 bits of the rate count data RCDO are all “0”, the lower 7 bits of the rate count data RCDO
8-bit data obtained by adding "゜0゛" to the bits is output from the data selector 80 and supplied to the input terminal A of the adder 81. The adder 81 selects the output of the data selector 80 and the output of the OR gate 84 (゜゛1゛ or "゜0゛). The inverter 72 is connected to the first input terminal of the OR gate 84.
The input terminal of the inverter 72 is supplied with the seventh bit of the data RCD output from the output terminal B of the distribution circuit 77, that is, the HOLD signal. Further, a second input terminal of the OR gate 84 is supplied with a decay request signal DEQ, which will be described later. Therefore, H.O.
When the LD signal is ゛゜0゛, the output of the inverter 72 becomes ゜゜1゛, and this ゜"1゛ is supplied to the input terminal B of the adder 81 via the OR gate 84. As a result, the output of the inverter 72 becomes ゛゜1゛. Adder 81 adds R to the output data.
lJ is added, and the addition result is supplied to the upper 8 bits of input terminal B of data selector 73. Further, the lower 8 bits of the input terminal B of the data selector 73 contain the rate count data RCDO output from the distribution circuit 77.
The lower 8 bits are supplied. The data selector 73 outputs the data of the input terminal B when the address signal PIAl (FIG. 15) is ゜゛0゛, and when it is ``1'', it outputs the data of the input terminal A. Therefore, in this case, the input terminal Data B is output from the data selector 73 and supplied to the selector register 75.Then, this data is read into the register 75 at the timing of the clock pulse MCLK3, and then read into the segment count memory 76 at the timing of the clock pulse MCLK1. In this way, at the timing T.O shown in Figure 15, data RCDO is first read out, and RlJ is added to the read data RCDO (RlJ is added to the read data RCDO).
lJ is subtracted), then the data after this addition is used as the upper 8 bits, and the data RCDO before addition is used as the lower 8 bits is again the data RCDO in the memo 1J76.
is written to the location. Next, time T shown in the 15th diagram.
At timing 1, envelope count data ECDO is read from segment count memory 76 and supplied to distribution circuit 77. At this time, the signal PIAl
is in the "F" signal, therefore, the data ECDO is output from the output terminal A of the distribution circuit 77 and supplied to the input terminal A of the adder 78.The output of the OR gate 82 is supplied to the input terminal B of the adder 78. Supplied by Orgate 82
A stamp request signal DAQ (always at 0) is supplied to the first input terminal of , and the output of a delay circuit (delay time=2 base clock times) 85 is supplied to the second input terminal. Further, a signal from the carry-out terminal CO of the adder 81 is supplied to the input terminal of the delay circuit 85. The time T mentioned above
. At O, if the carry out output of adder 81 is O”
and therefore time T. In l, the delay circuit 85
The output signal becomes "0", and this signal "0" is supplied to the input terminal B of the adder 78 via the OR gate 82. As a result, the envelope count data ECDO supplied to the input terminal A of the adder 78 is output from the adder 78 as is, and is supplied to the input terminal A of the data selector 73. At this time, the signal PIAl is "゜1", so the envelope count data ECDO output from the adder 78 is output from the selector 73, read into the selector register 75, and then read into the segment count memory 76. .In this way, at time T.l, the envelope count data ECDO is read from the segment count memory 76, and when the output of the delay circuit 85 is "゜0゛", the read data ECD
O is again written to the same location in memory 76. Below, address signals PIA5 to 1 (to Figure 15) are ROJ
RlJ is added to the rate count data RCDO every time the address signal PIA5-1 becomes RlJ, and the envelope count data ECDO is added to the memory 7
6 and then written to the same memory 76. Then, from the carry out terminal CO of adder 81゜“
When the 1゛ signal is output (when the upper 8 bits of data RCDO become RO), the delay circuit 85 outputs the ゜゜1'' signal with a delay of 2 base clock times, and the signal is sent to the input terminal of the adder 78 via the OR gate 82. B. This causes the envelope count data ECDO to contain rl
1 is added (11 is subtracted). Thereafter, the same process is repeated, and when the ゜゜1゛ signal is output from the carry out terminal CO of the adder 78 (data EC
When DO becomes ROJ), this “゜1゛” signal becomes signal FC.
The carry-in terminal C of the adder 25 shown in FIG.
Supplied to I. The above is the process of time measurement for channel CHO and segment 0. On the other hand, data corresponding to the channel CHO in the 0th storage slot of the segment memory 22 in FIG. The register 24 delays the supplied data by one base clock time and outputs it to the input terminal B of the adder 25.
Data ED is supplied to the input terminal A of the adder 25 from the decay dump control circuit 29. This data E
D is always r'0J, so register 2
The output data of No. 4 is the carry-in terminal CI of the adder 25.
When the signal ECCC゜l゛signal) is not supplied to
The signal is output as is from the adder 25 and supplied to the AND gate 26. AND gate 26 receives signal RUN (15th
When E) in the figure is ゛1゛, it is open and the output of the adder 25 is supplied to the input end of the segment memory 22.
The contents of the 0th memory slot corresponding to the channel CHO of the segment memory 22 are set to RO in the initial state, and even after the signal R[-1N rises to "゜1゛", ROJ continues.
Then, at the timing of channel CHO, signal ECC (
Rl only when the ゜゜1゛ signal) is supplied to the adder 25.
J (indicating segment 1). When the content of the 0th storage slot corresponding to channel CHO of the segment memory 22 becomes RlJ, the address signals PSA8 to PSA6 become r1, and this address signal 1 is supplied to the address terminal AD2 of the segment count memory 76 in FIG. be done. As a result, from now on, the rate count data RCDl (corresponding to segment 1) is set every time the address signals PIA5-1 become RO corresponding to the channel CHO, and the envelope count data Each ECDl is read from the segment count memory 76, and time measurement for segment 1 is performed in the same manner as described above. Then, when the signal ECC is outputted again from the carry-out terminal CO of the adder 78, the contents of the 0th storage slot corresponding to channel CHO of the segment memory 22 (Fig. 5) become 12J, and from then on, the time measurement of segment 2 is performed. When the time measurement for segment 2 is completed, time measurement for segments 3 to 7 is then performed sequentially. The above is the process of segment calculation. Note that the above process is a segment calculation process for channel CHO, but when sound generation assignment is performed for channels CH1 to CH15, the same process is performed. In this case, the time measurement of channel CHl is performed at time T1 shown in Fig. 15, . . .
The time measurement of l5 is performed at time Tl5 shown in the figure. In addition, in the above process, when the HOLD signal is "°1", the output of the inverter 72 is "0", and therefore the output of the OR gate 84 is "60", and this 4"0" signal is the output of the adder 81. is supplied to input terminal B of. As a result, the addition of 1+ in the adder 81 is not performed, the segment calculation substantially stops, and the segment continues to be in the state of 4 -. Note that the subsequent segment processing in this case will be explained in the subsequent key-off processing. ]) Envelope calculation At the time when the musical tone calculation period Tg shown in FIG. 13 begins, the envelope initial values 110NT, I20NT, A0NT are stored respectively, and envelope increment values Δ110, Δ120, ΔAO, Δ111,
Δ121, ΔAl, ... Δ117, Δ127, ΔA7
are stored respectively (see area EO in FIG. 9). In this state, when the address signals PIA5-0 become ROJ corresponding to the channel CHO (see time TaO shown in FIG. 16A), the initial value 111NT corresponding to the channel CHO is output from the envelope calculation memory 54 (the Also, the envelope increment value memory 66 outputs an increment value Δ110 corresponding to the channel CHO (see FIG. 16A). and,
The output of the envelope calculation memory 54 is supplied to the input terminal A of the adder 57, and the envelope increment value memory 6
The output of 6 is supplied to input terminal A of data selector 59. The data selector 59 outputs data RO when the output of the inverter 72 is 0 (HOLD signal is 1), and when the output of the inverter 72 is 1, the dump request signal DAQ is output. Input terminal A when “゜0゛”
When the signal DAQ is "1", the data at the input terminal B is output. At % of the time in FIG. 16A, the output of the inverter 72 is "1", and the dump request signal DAQ is "0". and
Therefore, the output Δ1 of the envelope increment value memory 66
10 is supplied to the input terminal B of the adder 57 via the data selector 59. As a result, data (
111NT+Δ11o) is output and sent to the input terminal A of the adder 58. External control data is supplied to input terminal B of this adder 58. This external control data is data that is supplied when, for example, the performer wants to directly control the volume, timbre, etc. of the generated musical tones during a performance, or when the performer wants to apply periodic modulation to the volume or timbre. shall be. Therefore, normally the data supplied to the input terminal A of the adder 58 is
The signal is outputted as is from MCLK3 and read into the selector register 51 at the timing of clock pulse MCLK3. The read data is then outputted from the same register 51 as ENVDATA15-0 (FIG. 16A, d), supplied to the tone calculation circuit shown in FIG. 7, and written into the envelope calculation memory 54 again. In this way, the signal P
Period 11 with IA5~0 in ROJ! In TTaO, data 1 corresponding to channel CHO is retrieved from memory 54.
11NT is read out, and then data Δ110 is added to this data 111NT, and the addition result is 11, +Δ1.
10 is ENV regarding data 11 of channel CH20
It is output as DATA15 to 0 and is also stored in the memory 54.
The data 111NT within is written to the location where it was stored. Next, when the signal PIA5-0 is turned on, data 1218+Δ120 is output as ENVDATA15-,0, and this data is written into the memory 54 in the same manner as the above-mentioned input. Then signal PIA5~
When 0 becomes R3J, channel CHO data AINT+ΔAO is output as ENVDATA15 to 0,
This data is also written into memory 54. The above is the processing for channel CFIO, and from now on, signal PIA
When signal PIA5-0 is 14-7, processing for channel CH1 is performed, and when signal PIA5-0 is 160-63, processing for channel CH15 is performed. Next, when the signals PIA5 to 0 become ROJ again, data 111NT+Δ110 is read out from the memory 54, Δ110 is added to this read data, and the addition result is 111NT+2.
Δ110 is output as ENVDATA15-0 and is written again into the memory 54, and the same process is repeated (see FIG. 16B). The above is the process of envelope computation, and in this way, the computations of equations (5) to (7), that is, the following computations are performed. Note that when the output of the inverter 72 is "0" (when the HOLD signal is "6F"), the output of the data selector 59 is RO.
Therefore, the data read from the memory 54 is ENVDATA as it is (without the increment value added).
It is output as l5-0 and is also rewritten into memory 54. In this case, of course, the envelope data A, 11, and 12 do not change. Note that, in reality, the output of the inverter 72 is supplied to the data selector 59 via a timing adjustment circuit, but a description of this point will be omitted. 3) Phase calculation The process of this phase calculation is almost the same as the envelope calculation process described above, so a detailed explanation will be omitted.
The outputs of the phase calculation memory 55 and the phase increment value memory 67 and FREQD are shown in FIGS. 16A and 16B, respectively.
Shows ATAl5-0. This data FREQDATA15-0 is supplied to the musical tone calculation circuit shown in FIG. This phase calculation is the above-mentioned (2)
This is the calculation of formula (4), that is, the calculation. Note that the external control data supplied to the input terminal B of the adder 61 is data supplied when frequency modulation (for example, bifrato) is applied to the musical tone, and when no frequency modulation is applied, it is ROJ.7) Musical sound waveform Operation This musical sound waveform calculation is a calculation for forming a musical sound waveform, and is performed by the musical sound calculation circuit shown in FIG.
Performed using VDATA15-0 and FREQDATA15-0. In FIG. 7, reference numeral 47 is a microprogram memory (ROM), and this memory 47 stores in advance microinstructions of 64 steps (16 bits per step) shown in FIG. In FIG. 17, the O mark indicates the "r" signal, and the blank space indicates the "0" signal. For example, the instruction TO in the first line of the diagram is the instruction "00...0111r". Also, the name of each bit signal is written at the top of the diagram. The function of each bit signal is as follows. -Channel address signals CHA3-0 (first
5th to 12th bits) As mentioned above, channel CHO
This is a signal indicating the processing timing for each of CH15 to CH15 (see FIGS. 12 and 15). ●Gate signal GATEMULK (7th bit) When this gate signal GATEMULK becomes "R5", the gate circuit 92 in FIG. 7 becomes open. -Select signal FREQSEL (6th bit) This select signal FREQSEL becomes 6'0" When this happens, the input terminal A of the selector register R3 in FIG. 7 is selected, and when it becomes "1", the input terminal B is selected. - Load signal LDB (5th bit) Then, the data is read into the output buffer 93 in FIG. 7. Load signal LDR5 (4th bit) When this load signal LDR5 becomes "1", the register
5 (FIG. 7). - Load signal LDR4 (3rd bit) When this load signal LDR4 becomes ゜゜1゛. Data is read into register R4. - Load signal LDR3 (second bit) When this load signal LDR3 reaches ゜゛F゛, the data selected by the above-mentioned select signal FREQSEL is read into the register R3.・Load signal LDR2 (1st bit) This load signal L
When DR2 becomes ゜゜1゛, data is read into register R2.・Load signal [J) R1 (0th bit) When this load signal LDRl becomes “4r”, ・data is read into register R1. Also, the number written inside the O mark in FIG.
Channels CHO to CHl processed by that signal
It shows the number 5. Each instruction in the above-mentioned microprogram memory 47 is read out by address signals 1A5-0. That is,
When the address signal 1A5-0 is ROJ, the instruction TO in FIG. 17 is read out, and when the address signal 1A5-0 is RlJ, the instruction T1 is read out,
When R63J, instruction T63 is read. Of the bit signals included in the read instruction, the channel address signals CH3 to CH0 are output to each part of the circuit shown in FIGS. After being delayed by the base clock time, it is output to FIG. Next, the operation of the circuit shown in FIG. 7 will be explained with reference to FIGS. 17 and 18. First, FIG. 18 shows clock pulse MCLKl, address signals 1A5-0, PIA5-0, ENDATA15-0.
, FREQDATA15-0 and FIG. 7 is a timing diagram showing the interrelationship of outputs of each part. In this figure, the numbers ROJ and RLO in the lower right corner of the rectangular frame indicate channel numbers, respectively. Further, each microinstruction TO to T63 in the microprogram memory 47 in FIG.
As mentioned above, the address signal 1A5-0 (Figure 18)
Therefore, it is constantly read out repeatedly. Then, each of the read microinstructions TO to T63 is delayed by one base clock time by the instruction register 48 and
Output to each part of the diagram. On the other hand, address signals PIA5~
0 (FIG. 18C) is a signal obtained by delaying address signals 1A5-0 by one base clock time. Therefore, as shown in FIG. 18C and F, the address signal PIA5
When ~0 is RO, the microinstruction TO is output from the instruction register 48, and the address signal PIA
Instruction register 48 when 5 to 0 is R63J
A microinstruction T63 is output from the microinstruction T63. In addition, the aforementioned data ENVDATA15-0 and FREQDATA
The timing at which l5-0 is supplied to the circuit of FIG. 7 is as shown in FIGS. 16A and 16B, 2 and 5, and these data are transferred to FIGS. 18, 2 and 5, respectively. In addition, ω1, ω2, ω in FIG. 18E. instead of ω
1t, ω2t, ω0t1 as mentioned above (
This is to make the correspondence with formula 1) easier to understand. The operation of the circuit shown in FIG. 7 will be described below with reference to FIG. First, the time TO (first
8), the microinstruction TO is output from the instruction register 48 in FIG.
Also, at this time, channel C is connected to the input terminal of register R1.
HO ENVDATA15 to 0rI1J are supplied, and channel CHO is supplied to input terminal A of selector register R3.
FREQDATAAl5~0r0)1tJ is supplied. When the microinstruction TO is output from the instruction register 48, the load signals LDR1 to LDR4
(see FIG. 17) are supplied to registers R1 to R4, respectively. Here, load signals LDR1 and LDR3 are signals for forming a musical tone signal of channel CHO, while load signals LDR2 and LDR4 are signals for forming a musical tone signal of channel CH15. Hereinafter, only the case of forming a musical tone signal for channel CHO will be explained. When load signals LDR1 and LDR3 are supplied to registers R1 and R3, respectively, registers R1 and R
The above data 11 and ω1t are read into 3 (
(See Figure 18, Figure 18). In addition, at this time, the select signal FR
EQSEL is 0, and input terminal A of register R3 is selected. When the data ω1 is read into the register R3, this data ω1t is supplied to the sign table 96, and as a result, the data ω1t is read from the sign table 96.
is output (see Fig. 18E). Next, at time t1, ENVDATA15~0 is sent to the input terminal of register R1.
rI2J is also connected to input terminal A-. of register R3. F.R.E.
QDATA15~0'ω2tJ are each supplied, and
Microinstruction T1 from instruction register 48
(See FIG. 17) is output. This microinstruction T1 causes the load signal 1J) R1 to
LDR4 is supplied to each register R1-R4, and each data shown in FIG. 18 is read into each register R1-R4. Further, when the data ω2t is read into the register R3 and supplied to the sine table 96, the sine table 96 outputs the data Sinω2t. Also, register R
Data Sinω1t is read into register R2, data 11 is read into register R2, and these data are respectively input to multiplier 9.
When 0 is supplied, data 11Sinω is output from the multiplier 90.
1t is output (FIG. 18W). Also, at this time, the gate signal GATEMUIK is "0", so the output of the gate circuit 92 is 0 (18th diagram).
When the multiplier 90 outputs the data 11 sin ω 1t and the gate circuit 92 outputs data 0, the output of the adder 91 becomes 11 sin ω 1 t (FIG. 18 y).
. Next, at time T2, microinstruction T2 is output from instruction register 48. This causes load signals LDR2, LDR4, LDR5 to be applied to registers R2, R4. R5, each register R2, R
4, each data shown in FIG. 18 is read into R5. Note that the data in registers R1 and R3 are the same as the data at time t1. Also at this time, sign table 96,
The outputs of the multiplier 90 and the adder 91 are as shown in the figure. Next, at time T3, microinstruction T3 is output from instruction register 48. As a result, the load signals LDR1, LDR3, the select signal FREQSEL1, and the gate signal GATEMULK are supplied to the registers R1, R3 and the gate circuit 92, respectively.
When the load signal LDRl is supplied to the register R1, data A is read into the register R1. Also, at this time T3
In registers R2, R4 . The data in R5 is time T
The data is the same as in 2. Therefore, multiplier 9
The output of 0 becomes data I2sinω2t, and the output of register R5 becomes data 11sinω1t. Here, when the gate circuit 92 is opened by the gate signal GAlEMULK, the output of the adder 91 becomes the data 11.
Sinω1t+I2Sinω2t, and this data is supplied to the input terminal B of the adder 95. As a result, the output of the adder 95 is data ω. t+11Sinω1+I2S
inω2, and this data is supplied to input terminal B of register R3. Here, load signal 1 to register R3
J) When both R3 and the select signal FREQSEL are supplied, the data at the input terminal B of the register R3 is read into the register R3 and supplied to the sign table 96. As a result, at time T3, from the sign table 96, Sin(ω0t+11Sinω1t+I2Sinω
2t) is output (see FIG. 18). Next, at time T4, microinstruction T4 is output from instruction register 48. This results in
The load signals LDRl~1J)R4 are respectively applied to the registers R1~
R4, and each data shown in the figure is sent to registers R1 to R.
4. Here, each data read into registers R2 and R4 is data for forming a musical tone signal of channel CHO, while data read into registers Rl and R3 is data for forming a musical tone signal of channel CH1. It is data. That is, from this time T4, musical tone signal formation for channel CH1 is started. Register R2
, R4 receives data A and data Si of channel CHO.
When n(ω0t+11Sinω1t+I2Sinω2t) is read, the multiplier 90 outputs Asin(ω0t+1
1Sinω1t+I2Sinω2t), that is, the data of the equation (1) for channel CHO, is output, and this data is output from the adder 91. Next, at time T5, microinstruction T5 is output from instruction register 48. As a result, load signal LDR5 is supplied to register R5, and the above data is read into register R5. Next, at time T6, the instruction register 48
A microinstruction T6 is output from the microinstruction T6. As a result, the load signal LDB is supplied to the output buffer 93, and the data Asin(ω0t+11Sinω1t+I2Sinω
2t) is read into the output buffer 93. Then, the data read into this output buffer 93 is
The signal is converted into an analog signal by the -A converter 94, and produced as a musical tone from a speaker (not shown). The above is the process of forming the channel L/CHO musical tone signal, and as described above, the channel CHO musical tone signal is formed between the address signals PIA5-0 and RO-6. Further, each musical tone signal of channels CH1 to CH15 is also formed in exactly the same process. In this case, the channel CHl
The musical tone signal of channel CH2 is formed when the signal PIA5-0 is R4-10J, and the musical tone signal of channel CH2 is formed when the signal PIA5-0 is R4-10J.
is formed when R8~14J, channel CHl5
The musical tone signal is generated when the signal circles A5-0 are R60-2J. Therefore, the operation of the circuit shown in FIG. 7 described above is constantly repeated. Therefore, for example, a musical tone is assigned to the channel HO, and then various data regarding the channel CHO is transferred in the data transfer period Tt in FIG. 13, and then the musical tone calculation period Tg in FIG. 13 is entered. ENVDATA15~0 and FREQDA of channel CHO
When TAl5-0 are sequentially supplied to the circuit of FIG. 7 at the timing of signals PIA5-0r0-3J, a tone signal of channel CHO is formed in the above process. on the other hand,
When channel CHO pronunciation is not assigned,
ENVDATA15~0 of the channel CHO mentioned above,
Both FREQDATA15 to 0 become ROJ, and musical tone formation is not performed. ) Key-off processing When a pressed key in the key group 102 (FIG. 3) is released, the key assigner 103 selects the channel (CH) to which the released key is assigned a sound, as described above.
A Decay command or a dump command is output to instruct the end of the sound generation of 0 to CH15). The processes performed in response to these commands will be described below. (1) Processing for the Decay command For example, when instructing the end of sound generation on channel CHO, the key assigner 103 uses the 16-bit Decay command 66
00...01'' (the 0th bit is "1" and the other bits are 0'') is output together with the address signal. This Decay command is read into the Decay command register 38 shown in FIG. .Then clock pulse I
When NITCLK rises, the Decay command in register 38 is read into Decay register 39 and supplied to Decay multiplexer 40. The Decay multiplexer 40 has the same configuration as the eat multiplexer 34 and the run multiplexer 35 described above, and when the channel address signals CHA3 to CHA0 are RO, the data (
CH3
When ~0 is R15J, the signal of the 15th bit of the data at the human input end is output. The output of the decay multiplexer 40 is delayed by one base clock time by the register 41 and then outputted to the decay dump control circuit 29 as a signal DEOAY. Decay dump control circuit 29 detects that a Decay command is output on channel CHO based on the signal DECAY, and outputs Decay request signal DEQ when address signals PIA5 to PIA0 are R.
The output is performed at timings 0 to 3, and the following processing is performed. That is, when the data in the 0th storage slot corresponding to channel CHO of the segment memory 22 is output from the register 24, this data is checked,
The next data ED is output to the input terminal A of the adder 25 in accordance with the value of the same data. Through this processing, even if the tone formation of channel CHO at that time is in any of segments 0 to 4, the tone formation is forcibly shifted to segment 5, and thereafter the tone formation of segments 5 to 7 is performed. In addition, the musical tone formation of channel CHO is in segments 5 to 7.
In either case, musical tone formation continues as is. The above is the processing for the Decay command. (Ii
) Processing for the dump command For example, if you want to quickly end the sound of channel CHO, the key assigner 103 uses the 16-bit dump command 4.
'00...0r' (0th bit is "゜1゛)" is output together with the address signal. This dump command is read into the dump command register 42 shown in FIG. 5. Then, the clock pulse IN
When ITCLK rises, the dump command in register 42 is read into dump register 43 and supplied to dump multiplexer 44. Like the Decay multiplexer 40, the dump multiplexer 44 converts the data (16 bits) supplied to the input terminal based on the channel address signals CHA3 to CHA0 into serial data, and outputs the serial data to the register 41. The register 41 delays the output of the dump multiplexer 44 by one base clock time and outputs it to the decay dump control circuit 29 as a signal DAMP. Decay dump control circuit 29 controls channel CH based on this signal DAMP.
It is detected that the dump command for O is output, and thereafter, the dump request signal DAQC "1") is sent to the 6th address signal PIA5-0 at the timing of RO-3J.
It is output to the data selector 59 shown at the lower left of the figure. As a result, the envelopes 11, 12, and A of the channel CHO outputted from the envelope calculation memory 54 are each attenuated to 1-1164J by the attenuation circuit 63,
The data is supplied to the adder 57 via the data selector 59.
As a result, the generated musical tones are rapidly attenuated. The above is the processing for the dump command. Note that in the case of percussive musical tones, segments 9 to 7 may have already been completed at the time of key-off. In such a case, of course, no decay or dump command is output from the key assigner 103. )) Sound generation end processing The sound generation ends when the data in the segment memory 22 in FIG.
It is detected when VDATA15-0 (see FIG. 6) becomes negative. That is, the third bit of the output of the register 24 in FIG. 5 is supplied to the first input terminal of the OR gate 27. Also,
The negative data detection circuit 64 shown in the lower part of FIG.
When Al5~0 becomes negative, signal RER (゛゜1゛ signal)
This circuit outputs the signal RER, and this signal RER is supplied to the second input terminal of the OR gate 27. As a result, when the sound generation is finished, the OR gate 27 outputs the ゜“1゛ signal.
The signal is supplied to the sound generation end processing circuit 28. The sound generation end processing circuit 28 determines which channels CHO to C based on the output of the OR gate 27 and the channel address signals CHA3 to CHA0.
It detects whether the sound generation of El5 has ended, and outputs a 16-bit signal SFC indicating the ended channel CHO to CHl5. For example, when the channel CHO ends, ゜"11...10゛ (0th bit is ゜゜0゛) is output as the signal GFC. This signal SFC is sent to the run register 32.
, decay register 39, and dump register 43, thereby resetting the 0th bit of each of these registers 32, 39, and 43. When the 0th bit of the run register 32 is reset, since the output of the run register 32 is supplied to the key assigner 103,
The key assigner 103 detects the end of the sound generation of the channel CHO, and assigns a new sound generation to the channel CHO for subsequent key-on. In addition, in the description of the above embodiment,
Although this invention has been applied to an electronic organ, it is of course applicable to other similar electronic musical instruments. Furthermore, in the above embodiment, the envelope waveform is divided into 8 segments so that independent waveform calculation can be performed in each segment, but the number of divided segments is 8.
Not limited to individuals. Furthermore, the method of allocating the attack state, sustain state, and decay state of the musical sound waveform to the segments is not limited to that described in the above embodiment. [Effects of the Invention] As is clear from the above detailed description, according to the present invention, the assigner and the wave generator each operate independently, and therefore there are no design restrictions such as having them operate synchronously. There are benefits that do not arise. Further, according to the present invention, since the assigner sequentially outputs frequency data etc. to the wave generator for each channel via the bus line, there is an effect that the number of wiring between the assigner and the wave generator can be reduced. .

[Brief explanation of drawings]

1 and 2 are a block diagram and an envelope waveform diagram of a musical tone signal, respectively, for explaining the basic principle of musical sound waveform formation used in an embodiment of the present invention, and FIG. 3 is a diagram illustrating an embodiment of the present invention. A block diagram showing the configuration of the applied electronic organ, FIGS. 4 to 7 are circuit diagrams showing examples of the configuration of each part in the wave generator in the same embodiment, and FIG. 8 shows various clocks used in the same embodiment. The pulse waveform diagrams, FIGS. 9 to 11, respectively show the incremental value data memory 11 and the initial value data memory 13 in the same embodiment.
, a diagram showing each storage content of the segment data memory 15,
FIG. 12 is a timing chart for explaining the process of transferring data in the memories 11, 13, and 15 to the memories 54, 55, 66, 67, and 76, respectively, and FIG. 13 is a timing chart for the signal 1N.
A timing chart for explaining IT-1 and signal RUN-1, FIG. 14 is a diagram showing the storage contents of the memories 54 and 55, and FIG. 15 is a timing chart for explaining the time measurement process of each segment 0 to 7. Chart, Figure 16A, No. 1
Figure 6B is a timing chart for explaining the process of envelope and phase calculation, and Figure 16B is a timing chart for explaining the process of envelope and phase calculation.
This is a continuation of Figure A. FIG. 17 is a diagram showing microinstructions output from the microprogram memory 47, and FIG. 18 is a timing chart for explaining the operation of the musical tone calculation circuit shown in FIG. 7. 11... Incremental value data memory, 13...
... Initial value data memory, 15 ... Segment data memo ■822 ... Segment memory, 54
... Envelope calculation memory, 55 ... Phase calculation memory, 57, 60 ... Adder, 66 ...
Envelope increment value memory, 67...Phase increment value memory, 76...Segment counter memory 18103
. . . Key assigner, 104 . . . Wave generator, 108 . . . Musical waveform forming unit.

Claims (1)

[Claims] 1. An assigner that assigns a sound selected by operating a keyboard key to one of a plurality of channels, and a musical waveform of the sound assigned to each channel in accordance with the assignment of the assigner. In the electronic musical instrument, the assigner sequentially outputs frequency data and envelope data regarding the assigned sound to the bus for each channel in accordance with the assignment of the sound to each channel. The wave generator includes (a) storage means for storing the frequency data and envelope data sent to the bus for each channel, and (b) the frequency data stored in the storage means. (c) calculating the envelope data stored in the storage means for each channel; and (c) calculating the envelope data stored in the storage means for each channel. (d) time-sharing for each channel based on the phase data and envelope waveform data output from the first and second calculating means; An electronic musical instrument is provided with a musical sound waveform forming means for forming a musical sound waveform.