JPS61123886A - Formation of musical sound - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

"Field of Industrial Application" This invention relates to a musical tone forming method used in electronic musical instruments and the like. 1-Prior art” As a musical tone forming method used in electronic musical instruments, etc.,
Various methods have been proposed in the past, one of which is known as a method of forming musical tones using frequency modulation technology. JP-A-50-126406 discloses the above method, and according to the method described in this publication, musical tones containing many harmonic components can be formed with a simple configuration. . [Problems to be Solved by the Invention] This invention is a further improvement on the conventional frequency modulation musical tone forming method described above, and it is possible to easily obtain a more natural-looking musical tone with a large number of more complex harmonic components. The purpose of this invention is to provide a musical tone formation method that allows for [Means for solving the problem] The present invention frequency-modulates a first frequency signal in the audible frequency range according to a second frequency signal also in the audible frequency range, and modulates the frequency of the first frequency signal in the audible frequency range according to the signal obtained by this frequency modulation. It is characterized in that the third frequency signal in the frequency range is frequency modulated, and musical tones are formed based on the signal obtained by this frequency modulation. "Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, in the musical tone forming method according to the present invention, a musical sound waveform is formed based on, for example, the following basic formula for frequency modulation calculation. y-ΣA15IN(ωit+ 1=1 1 j Σ[jSIN(ωjt+ΣIk SIN wk t)
)j-1 to -1 (1) In the embodiment described below, a musical tone waveform is formed by the following equation included in the above basic equation (1). V-ASIN (ωo 1+ 12SIN(ω2t+[+sINω+1)...
(1a) In this equation (1a), A is an element that determines the amplitude of the musical sound waveform, ω0 is an element that determines the frequency of the carrier wave in frequency modulation, and ω electric, ω2, and II
, 12 are elements that determine the frequency and amplitude of a modulated wave in frequency modulation. FIG. 1 is a diagram showing an example of a basic circuit configuration when a musical tone waveform is formed by digital technology based on the above equation (1a), and in this figure, ACG1 to ACC3 are all accumulators. These accumulators ACC1~A'
CC3 is the increment value Δω of the phase supplied to each input terminal.
1. Δω2. Δω0 is accumulated according to a clock pulse of a constant period, and the accumulated results are sequentially output as phase data. The sine table S[N1 is a memory that stores each instantaneous value of the sine waveform, and when the output of the accumulator ACCI is supplied as an address signal, the instantaneous value stored in the address corresponding to the same address signal is The value is read. In this case, the accumulator ACCI starts accumulating from [Oj,
Then, each instantaneous value of the sine wave for exactly one period is sequentially read out from the 1.1.1 sine table 5INI until overflow occurs. Here, the accumulation speed of the accumulator ACC1 is constant because the period of the clock pulse is constant. Therefore, when the phase increment value Δω1 is constant, the period of the sine wave output from the sine table 5IN1 becomes constant. In other words, the phase increment value Δω1
By changing the value of sine table 5IN1
The period (frequency) of the sine wave output from can be changed. For example, if the phase increment value Δω1 is made large, the period of the sine wave becomes small, and if the increment value Δω1 is made small, the period of the sine wave becomes large. Moreover, if the accumulation performed in each of the accumulators AC01 to ACC3 is expressed by a formula, ω1 can be expressed as −ΣΔω! +ωI IN?・・・・・・・・・
(2)ω2t=ΣΔω2+ω21NT・・・・・・・・・
・(3)ωat−ΣΔω0+ωOIII?・・・・・・
...(4). Note that in these equations, ωtI
llr, ω2, ω. Each application is an initial value of the phase. Next, 5IN2.8 [N3 in FIG. 1 are each a sign table configured similarly to the above-mentioned sign table 5IN1, and M1 to M3 each have a value of 11.8 for input data.
I2. The multipliers ADDl and ADD2 that multiply A are adders. The outputs of these constituent elements each have the values shown in the figure, and the musical tone signal expressed by equation (1a) is obtained as the output of the multiplier M3. The basic configuration of the tone waveform forming circuit has been described above. Next, the process of forming tone waveforms in this embodiment will be described in more detail. In this embodiment, A, ω0゜II, 1 in the above formula (1a)
2. ω1. Each of ω2 is appropriately changed from the generation of musical tones until they are stopped, thereby making the musical tones formed closer to the musical tones of a natural musical instrument. That is,
In this embodiment, assuming that the amplitude envelope of the musical sound waveform is as shown in FIG. 2, for example, the period from the musical sound generation time t1 to the musical sound stop time t2 in this envelope is divided into eight segments O to ■. Separate values (
(in some cases, the same value) is set, and the tone waveform of equation (1) is formed based on the set value. In this case, the eight values A, . Then, A in each segment data, 11,
] The change in the 8 values of 2 is performed based on the following formula. A-ΣΔA + A +wt・・・・・・・・・・・・
・・・・・・・・・・・・(5) 1+=ΣΔ[1+l1
lNT・・・・・・・・・・・・(6) I2=ΣΔ12
+I21NT・・・・・・・・・・・・(7) In these equations, ΔA, Δl+, Δ[2 are respectively the (1a-th
), the increment values (sometimes negative values) of A, Il, and I2, Auvr, II INT, and I2M are the initial values of A, I+, and I2, respectively. In addition, the time width of each of segments 0 to ■ is determined by segment data described later, that is, late count data RC.
Do=RCD7 and envelope account data EC
It is determined by Do to ECD7. As is clear from the above, in this embodiment, one tone waveform (a tone waveform generated by one key operation) is generated, and the following (1) each data (total of 70 words; IWORD - 16 bits). (A) Incremental value shown in Tables 1 and 2 (48 WORD) (B) Initial value (6 WORD) AINTI I + lNTl I2 vωolN
T, ωIINT, ω21NT (C) Segment data (16WORD>Late count data RCDo~CD7 Envelope count data FCDo~CD7 Table 1 Table 2 Therefore, in this example, it corresponds to the timbre and pitch of the musical tone to be generated. The above-mentioned data (A) to (C) are set in advance in the memory, and musical tones are formed by reading each data in the memory.For example,
In the case of an electronic organ with 10 types of tones and 44 keys, 440 sets of the above-mentioned data are set in the memory. The above is the basic principle of musical tone formation used in this embodiment. Next, this example will be explained in detail. FIG. 3 is a block diagram showing the configuration of the electronic organ according to this embodiment. In this figure, reference numeral 101 is a tone lever for setting the tone, and 102 is a group of keys provided on the keyboard. In this embodiment, the tone lever 101 is composed of ten levers, and ten tone switches are provided corresponding to each lever. and,
The output of each tone switch is supplied to a key assigner 103, respectively. In this embodiment, the key group 102 is composed of 44 keys and 44 key switches corresponding to each key, and the output of each key switch is sent to the key assigner 10.
3. The key assigner 103 detects the currently set tone based on each output of the tone switch described above, and 1. Based on the output of the key switch described above, a newly pressed key and a newly released key are detected. When a newly pressed key is detected, the musical tone generation of the key is assigned to one of the channels (described later) of the Unibu generator 104, and when a released key is detected, the same Instructs the above channel to which key sound generation is assigned to stop sound generation. This key assigner 103 has RAM (random access memory) 10
5 and ROM (read-on memory) 106 are connected to each other. The RAM 105 stores various data tables, data files, etc. used for channel assignment, and the ROM 106 stores tone switch detection, key press/release detection, channel assignment, etc. Programs used in this process and various data necessary for musical tone formation in the Unibu generator 104 at J5, ie, each of the above-mentioned data (A) to (C), are stored. The Unibu generator 104 forms a musical tone waveform based on the basic principle described above, and is composed of a data port 107 and a musical tone waveform forming section 108. In addition,
Details of the data port 107 are shown in FIG. 4, and details of the tone waveform forming section 108 are shown in FIGS. 5 to 7. In this embodiment, this Unibu generator 104 has 16 channels (
It has a tone waveform calculation system for channels Oth channel CHO to 15th channel CH15), and is capable of simultaneously forming 16 tone waveforms. However, if the musical sound waveform is
) The arithmetic unit that performs calculations based on the formula and the sine table described above are each one circuit, and these arithmetic units and the sine table are used in a time-sharing manner. Next, the Unibu generator 10 shown in FIGS. 4 to 7
4 will be explained in detail. [1] General operation When any key in the key group 102 shown in FIG. Allocate to an empty channel among CH15. Next, the key assigner 103 reads out musical tone forming data (70 WORD) corresponding to the pressed key and the setting state of the tone lever 101 from the ROM 106, and reads out the increment value data memory 11 and the initial value shown in FIG. The data is transferred to the data memory 13 and the segment data memory 15. When this transfer is completed, a start command is output that instructs the channel to which sound is assigned to start sounding. This start command is the start command shown in FIG. It is read into the register 30. When the start command is read into the start command register 30, 256 μm (INITCLK) is read from the rising edge of the next clock pulse INITCLK (see Figure 8).
During one revolution 111) of K, the memories 11, 13 .
The data in '15 are transferred to the envelope calculation memory 54, phase calculation memory 55, envelope increment value memory 66, phase increment value memory 67, and segment count memory 76 shown in FIG. After this transfer is completed, musical sound waveform calculations are performed. In this musical sound waveform calculation, the following three systems of calculations are performed in parallel. (D Segment operation This operation is performed by the segment count memory 76 in FIG. 6, the circuit below it, the segment memory 22 in FIG. 5, etc.)
Based on the segment data in FIG. 2, each time of segments O to ■ shown in FIG. According to the segment number output from this memory 22, the above-mentioned table 1 and M2
Each incremental value data shown in the table is selected. (i) Envelope and phase calculation This calculation is based on the above-mentioned equations (5) to (7) and (2) to (4).
This is the calculation of the equation, and the envelope calculation memory 54, phase calculation memory 55, and these memories 54 and 55 shown in FIG.
This is done by the circuit shown at the bottom of the figure, an envelope increment value memory 66, and a phase increment value memory 67. The calculation results of equations (5) to (7) are sequentially supplied to the musical tone calculation circuit of FIG. ) are sequentially supplied to the musical tone calculation circuit shown in FIG. 7 as FREQDATA15 to 0 shown in the lower part of FIG. 0 Musical sound waveform calculation This calculation is the calculation of the above-mentioned formula (1a), and the seventh
This is performed by the musical tone calculation circuit shown in the figure. This musical tone calculation circuit executes the above-mentioned ENVDATA 5 according to the microinstructions in the microprogram memory 47.
~0 and FREQDATA15~0 are used to perform musical waveform calculations. Next, the musical tone ends as follows. Ki group 10
When the pressed key No. 2 is released, the key assigner 103 outputs a decay command or a dump command instructing to end the sound generation of the channel to which the sound generation of the released key is assigned. Decay command is the 5th
The decay command register 38 shown is loaded, and the dump command is loaded into the dump command register 42. When a decay command is output from the key assigner 103, no matter which segment ◎ to ■ the musical sound waveform calculation is in at that time, it is forcibly transferred to the segment ■ related to decay, and from then on, the musical waveform calculation in segments ■ to ■ will be performed. It will be done. Furthermore, if the musical waveform calculation at that time is in one of the segments (1) to (2), the waveform calculation for each segment is executed sequentially. On the other hand, when a dump command is output from the key assigner 103, the musical tone rapidly decays at a constant speed, regardless of which segment the waveform calculation is performed at that time. Next, each of the above-mentioned operations and the configuration related to each operation will be explained. [2] Writing to memory 11.13.15 In FIG. 4, master clock generator 1 generates four types of clock pulses MCLKI, MCLK2, . MCLK
3. This is a circuit that generates IN[TCLK. In Figure 8, these glue t10 pulses MCLK
The waveforms and mutual relationships of I~IN*TCLK are shown. Master counter 2 is a 10-bit pinary counter that performs counting according to master clock MCLK1, and its count output is address signal IA5-O, l5A.
Output as 9-6. Here, address signal IA5
~0 is the 5th bit to Oth bit (lower 6th bit) of the count output.
address signals [SA9 to SA6 are the 9th to 16th bits (upper 4 pits) of the count output. Pipeline register 3 is triggered by clock pulse MCLKI, in other words clock pulse MOLK
This is a 10-bit register that reads input data at a timing of 1. That is, this pipeline register 3 converts the output of the master counter 2 into a clock pulse MC and -Kl
The output signal is delayed by one period (250 nsec; hereinafter referred to as pace clock time) and output. The output of this pipeline register 3 is the address signal PIA5~
0 (lower 6 bits), PtS89 to 6 (upper 4 bits)
is output as The address decoder buffer 10 is a key assigner 103
This is a 10-bit register in which an address signal outputted from the address bus 17 (FIG. 3) is temporarily stored. The layer value data memory 11 is a memory to which the incremental value data (see Tables 1 and 2 above) outputted from the key azalea 1103 and supplied via the data bus 18 is transferred, and is shown in FIG. As shown, it has storage areas corresponding to each of channels CHO to CH15. For example, when sound generation is assigned to channel CHO, the 48 WORD increment value data shown in Tables 1 and 2 is output from the key assigner 103 and written in the area corresponding to channel CHO in FIG. . The initial value data memory 13 stores the initial value AlNT, I + lNTl I output from the key assigner 103.
This is a memory into which 21NT, ωolNT, ωIINT, and ω21NT are written, and has areas corresponding to channels CHO to CHI5, respectively, as shown in FIG. The segment data memory 15 is connected to the key assigner 10.
This is a memory in which segment data outputted from channels CHO-CH, that is, late count data RCDa=RCD7 and envelope count data ECDo-ECDy are written, as shown in FIG.
It has areas corresponding to each of the 15 areas. Each of the data selectors 4.6.8 is a circuit that selectively outputs either the data of the input terminal or the data of B, and the key assigner 10
The above selection is made in accordance with the memory selection signal MS outputted from 3. The memory selection signal MS is a 3-bit signal,
The Oth bit is supplied to data selector 4 and memory 11 (not shown), the first bit is supplied to data selector 6 and memory 13, and the second bit is supplied to data selector 8 and memory 15. Then, when the Oth bit of the signal MS becomes "1", the data selector 4 selects and outputs the data (address signal) of the input terminal B, and the memory 11 becomes in a data writable state. The first and second bits of the signal MS are each "1"
If , data selector 6.8, memory 13.
15 operates similarly. Address buffer? 5, 7.9 are buffer amplifiers, and buffer registers 12.
14 and 16 are registers that delay input data by base clock time (250 nsea) and output the delayed data. Now, assume that any key in the key group 102 shown in FIG. 3 is pressed, and in response to this key operation, the key assigner 103 assigns the sound of the pressed key to, for example, channel CHO. In this case, the key assigner 103 transfers each increment value data of Tables 1 and 2 corresponding to the pressed key and the selected tone to an address indicating each address of the area of channel CHO in FIG. Output sequentially along with the signal,
At the same time, memory selection signal MS “OOl” (Oth
The address signal output from the key assigner 103 is written into the address decoder buffer 10 via the address bus 17, and this written address signal outputs the data selector 4 and address buffer 5. is supplied to the memory 11 via the
The incremental value data supplied to the memory 11 via the data 11 bus 18 is transferred to the channel CHO shown in FIG.
are sequentially written in the area corresponding to the state shown in the figure. Next, the key assigner 103 similarly sequentially outputs the initial value data and segment data together with the address signal and memory selection signal MS. As a result, each data is sequentially written in each area corresponding to the channel CHO of the memory 3 shown in FIG. 10 and the memory 5 shown in FIG. 11 in a state not shown in the figure. [3] Transfer the data in memory 1.13.15 to memory 54
, 55, 66, 67, 76 (Figure 6) Figure 12 (A) and (B) are the clock pulses MCLK, respectively.
I, A diagram showing the INITCLK (7) waveform, (C) and (D) are diagrams showing the address signals IA5-O and IA9-6 output from the master counter 2 in FIG. 4, (E),
(to) are address signals PIA5-0 and PISA9-6 respectively output from the vibe line register 3 in FIG.
FIG. As shown in this figure, the address signal I
A5-0 and l5A9-6 are both clock pulses I
rOJ occurs at the rising edge of NITCLK. In addition, address signals PIA5-0 and PICA9-6
are signals obtained by delaying address signals IA5-0 and IA9-6 by one base clock time (250 nsec), respectively. FIG. 12(g) is a diagram showing channel address signals CHA3-O. These channel address signals CHA3-O are signals output from the microprogram memory 47 shown in FIG. 7, and as shown in FIG. , NJ for "r4-7", "2" for r8-11"
...It is a 4-bit signal that becomes "15" when it is "60 to 63". The 8 values of channel address signals CHA3-O correspond to channels CHO-CH15. For example, when channel address signals CHA3-O are rOJ, processing of channel CHO is performed, and when it is "15", channel Processing of CH15 is performed. When transferring data in the memories 11, 13, and 15 to the memories 54 to 76, each of the above address signals is used. Next, reading of each data in the memories 11, 13, and 15 will be explained. Each data in these memories 11, 13, and 15 is always read out in parallel except in the case of data writing as described above. That is, except for the data write described above, the memory selection signal MS is 11Q, 0.
It is turned on, and therefore the data selectors 4, 6, and 8 each output the data of the input terminal A. As a result, the address signals IA5-0 and ISA9-6 output from the master counter 2 are applied to the data selectors 4, 6, 8, . It is supplied to each address terminal AD of the memories 11, 13.15 through the address buffer 5.7.9, and thereby the memory 1
Each data in 1, 13, and 15 is read out sequentially. However, the address signals supplied to the memory 11 are IA5 to O,
l5A9-6, but the address signals supplied to the memory 13 are IA5-0 and l5A6 (master counter 2
The address signals supplied to the memory 15 are IA5-1 (signals of the first to fifth bits of the output of mask counter 2) and I5A8-1.
6 (signal of the 6th to 8th bits). Next, the process of reading data in each memory 11, 13, 15 will be described in detail. Q) Memory 11 First, address signals IA5-0 are "0". When "0" is supplied as tsA9-6, data ΔI+o(0) shown in FIG. 9 is read out (see FIG. 12 (h)), and then "1" is supplied as IA5-0. When "0" is supplied as l5A9-6, the data ΔIze(1) in FIG. 9 is read out, and when "63" is supplied as lA5-0 and "0" as l5A9-6. , data ΔAa (63) are successively output. That is, if l5A9-6 are rOJ, each channel CHO~
CH15 segment ◎ envelope increment value data (
ΔrIo*Δ120. Δ80〉 is read out. Next, I
SA9-6 is 1-1J l'. Then, while IA5-0 changes from "0 to 63", the segment of each channel CHO-CH15
envelope increment value data ΔIn(Oa), ΔI+(
1a)・-ΔA+ (63a) is read out (Fig. 12(
(see h)), and thereafter, each envelope increment value data is sequentially read out in the same manner. Next, when l5A9-6 becomes "8"("1000"), phase increment value data (Δω1@, Δω20 .DELTA..omega..) is read out, and in the same manner, each phase increment value data is sequentially read out. As is clear from the above process,
Each of the multi-values of address signals 15A8-6. correspond to segments ◎~■, and address signal l
QIZI "1'° of 5A9 is area E shown in Fig. 9.
It corresponds to O and E1. Each data read out in the above process is delayed by one base clock time by the buffer register 12 (see FIG. 14) and output (see FIG. 12). Oi) Memory 13 When the address signal l5A6 is “0”, the first
Data IIIINT (0) to AiNT (63) shown in Figure 0
(Envelope initial value data) is read and if address signal l5A6 is "°1", address signal IA5~
While O changes from "0 to 63", data ω+xr(Oa) to ωolNT(63a) (phase initial value data) in FIG. 10 are read out (see FIG. 12 (h)). Each read data is then output after being delayed by one base clock time by the buffer register 14 (
(See Figure 12 (S)). B) Memory 15 When the address signals IA8-6 are rOJ, the data RCD shown in FIG. 11 is generated while the address signals IA5-1 change over "0-31".

[0]~ECD, (31) are read and the address signal l
When 5A8-6 is "1", address signal IA5-1
The data in FIG. 11 RCD + (Oa) ~ E CD+ (31
a) is read out, and thereafter, each segment data is sequentially read out in the same way (see FIG. 12(x)). That is,
Reading from the memory 15 is carried out every two base clock times, and the multiple values of address signals l5A8-6 correspond to segments O-, respectively. Then, each data read from the memory 15 is stored as 1 by the buffer 7 register 16.
The signal is output with a pace clock time delay (see FIG. 12 (L)). Next, the data in memory 11.13.15 is transferred to memory 54.
．． The process of transferring to 55.66.67.76 will be explained. Suppose now that the key assigner 103 assigns the sound of the pressed key to channel CHO. In this case, as described above, the key assigner 103 outputs various data corresponding to the tones and tones of the musical tones to be produced and stores them in the memories 11 and 13.
．． Write in the area corresponding to channel 15 CHO,
Next, a start command ``OO...01'' (16 bits) is output.The Oth bit 1'' in this start command instructs the start of channel CHO. When this start command is output, the 9th
Channel CHO in area EO of memory 11 shown in the figure
Each envelope layer value data corresponding to the channel CHO in area E1 is transferred to the envelope increment value memory 66 in FIG. 6, and each phase increment value data corresponding to channel CHO in area E1 is transferred to the phase increment value memory 66 in FIG. Transferred to 67,
Also, the channel CHO in the memory 13 shown in FIG.
Each envelope initial value data (1+ INT
, I2 v, Av,) are transferred to the envelope calculation memory 54, and each phase initial value data (ω1舅, ω211fr, ωoI
Each of the segment data corresponding to the channel CHO of the memory 15 shown in FIG. 11 is transferred to the segment count memory 76. The above operation will be explained in detail below. When the aforementioned start command "Oo...01" is output from the key assigner 103, this start command is read into the start command register 30 (16 bits) shown in FIG. 5 via the data bus 18. Next When the clock pulse IN[TCLK rises, the output data of the start command register 30 is read into the init register 31 at this rising point, and this read data is supplied to the init multiplexer 34. , the channel address signal @C1-lA3~0 (Figure 12 (G)) is “0”.
”, the signal of the Oth bit of the input data is output, and below,
When CHA3-O are "1" to "15", signals of the 1st bit to 15th bit of the input data are output (parallel-to-serial conversion is performed). That is, when the data (start command) read into the init register 31 is OO...01'', the output signal IN[T-
1 has the waveform shown in FIG. 12 (e). This signal INIT-
The pulse width of 1 is 1μ, and as shown in FIG. 13(b), it occurs 16 times during one period (256μ decrease) of the clock pulse INITCLK (FIG. 13(a)). Data is written into the memories 54 to 76 when this signal INIT-1 is generated 16 times. This signal 1
rlT-1 is supplied to the set input terminal S of flip-flop 37 (FIG. 5). The flip-flop 37 is triggered by the clock pulse MCLK1, delays the signal INIT-1 by one base clock time, and outputs the delayed signal as the signal INIT (FIG. 12(W)). Based on the signals INIT-1 and INIT, data in the memories 54 to 76 is loaded in the following process. (i) Memories 66, 67 (Fig. 6) These memories 66, 67 are the same as areas EO and E1 in Fig. 9, respectively.
It is a memory of @ amount, and at L/S communication jtPrA5~O(
4 and 112 (E)) are supplied as lower addresses, and address signals PSA8 to PSA6 are supplied as upper addresses. Here, address signals PSA8 to PSA6 will be explained. The selector register 21 shown in FIG.
When 1 is “On”, the memory 22 that is supplied to the input terminal A
is read at the timing of the clock pulse MCLKI, and when the signal INIT-1 is 1'°, the address signals l5A9-6 (FIG. 12 (d)) supplied to the input terminal B are read in at the timing of the clock pulse IVIGLKI. Load at the timing of Then, the read signals are output as address signals PSA9 to PSA6. That is, the signal IN(T
When -1 becomes "1", address signals l5A9-6 are delayed by one base clock time in selector register 21 (therefore, they become the same signal as address signals PISA9-6) and are output as address signals PSA9-6. Address signals PSA8-6 supplied as upper addresses to memories 66 and 67 are the lower three bits of address signals PSA9-6 mentioned above. Next, each read/write terminal R/W of the memory 66.67
are respectively supplied with the outputs of AND gates 68 and 69. Further, a signal INIT is supplied to each first input terminal of AND gates 68 and 69, an address signal PSA9 is supplied to a second input terminal of AND gate 68 via an inverter 70, and a second input terminal of AND gate 69 is supplied with a signal INIT. An address signal PSA9 is directly supplied to the end. Here, the address signal PSA9 is a signal obtained by delaying the address signal l5A9 by one base clock time by the selector register 21 (FIG. 5) (provided that the signal INIT-1 is 1''), and therefore, When the address signal PSA9 is "0", the data in the area EO in FIG. 9 is output from the buffer register 12 in FIG. 4, and the address signal @P
When S A 9 is "1", the data in area bit 1 in FIG. 9 is output from the buffer register 12 in FIG. 4. Now, the clock pulse INITCLK rises to the "1" signal, and then the signal I shown as P1 in FIG.
When NIT is output, signal PSA9 becomes “0” at this point.
'', the signal INIT is connected to the AND gate 68.
The signal is supplied to the read/write terminal R/W of the memory 66 via. At this time, as shown in FIG. 12, the envelope increment value data (Δ
, 1°110#ΔI211. ΔAO: Figure 9)
are sequentially output and supplied to the data input terminal of the memory 66 (FIG. 6). Therefore, the signal I denoted by P1
When the NI number is output, the envelope increment value data described above is written into the memory 66. Next, Figure 12 (W)
When the signal INIT indicated by the symbol P2 is outputted, the envelope increment value data (Δ111.ΔI21°ΔA+) of the channel CL (O and the segment ■) is sequentially written into the memory 66, and from now on, the signal INIT is " Each time the signal becomes 1", the segment ■, ■ of channel CHO.
... Each envelope increment value data of ■ is sequentially stored in the memory 66.
written within. Next, when the data in the area bit 1 in FIG. 9 is sequentially output from the buffer 7 register 12 (FIG. 4), the address signal PSA9 becomes 1' as described above, and therefore,
AND gate 69 is opened, and signal INIT is supplied to read/write terminal R/W of memory 67. As a result, from now on, every time NIT is output 8 times, each phase increment value data (
Δω16, Δω211. Δω00ゞΔω17 , Δω
2F. Δωo2 = FIG. 9) are sequentially written into the memory 67. (2) Memories 54 and 55 The initial value data output from the buffer register 14 shown in FIG. 4 is supplied to each input terminal A of the selector registers 51 and 52 shown in FIG. Each of the selector registers 51 and 52 is an AND gate 51a. When the output of AND gate 52a is 1'', the data on input terminal A is read at the timing of clock pulse MCLK3 (see Figure 8), and when the output of AND gates 51a and 52a is 0, the data on input terminal B is clocked. Read at the timing of pulse MCLK3. Signal INIT is supplied to each first input terminal of AND gates 51a and 52a, and address signal PsA6 is supplied to the second input terminal of AND gate 51a via inverter 50. The address signal Pr5A6 is directly supplied to the second input terminal of the AND gate 52a.Here, when the address signal PSA6 is 0, the envelope initial value data (r +
+nr, I21NT, AIN,) are output from the buffer register 14 in FIG. 4, and the address signal PIS
When A6 is 1'', the initial phase (direct data (ω
1lNr, ω21NT, ω0INT) are output from the buffer register 14. The memories 54 and 55 have areas corresponding to each of channels CHO to CH15, as shown in FIG. 14, and each area is composed of four storage slots (1 slot=20 bits). In this case, the four slots in each area are the address signal P
It is addressed by iA1°O, and each area is addressed by address signals PIΔ5-2. These memories 54 and 55 are connected to selector registers 51 .
52 is read at the timing of the rising edge of clock pulse MCLK1. Therefore, the signal IN indicated by the symbol P1 in FIG. 12 (W)
When IT is output, since the address signal P[SA6 is '0' at the timing of this signal INIT, the signal INIT is supplied to the selector register 51 via the AND gate 51a.As a result, the above-mentioned signal I
Channel CHO envelope initial value data (I+ INT, I2 INT, A
Nr, > (see FIG. 12) are sequentially read into the selector register 51, and then each read initial value data is sequentially read into the area corresponding to channel CHO of the memory 54. Next, in Fig. 12 (W), the symbol P2
When the signal INIT shown in is output, since the address signal PISA6 is "1" at this time, the same signal (NI
T is connected to the selector register 52 via the AND gate 52a.
supplied to As a result, the above-mentioned signal I N I T
Phase initial value data (ωIIN) of the channel CHO output from the buffer 7 register 14 at the timing of
F, ω2 whistle, ωowNτ) are sequentially transferred to the selector register 52.
Then, each read initial value data is sequentially read into the area corresponding to the channel CHO of the memory 55. Thereafter, the same operation as above is repeated every time the signal INIT is output. 1゛(to) memory 76 The segment data output from the buffer register 16 in FIG. 4 is input to the input terminal A of the selector register 75 in FIG.
supplied to The selector register 75 has the same configuration as the selector registers 51 and 52 described above, and receives the signal 111.
When r is 1'', data on input terminal A is read at the timing of clock pulse MCLK3, and when signal INFT is “O”, data on input terminal B is read. Segment count memory 76 is a memory shown in FIG. This memory has the same configuration as No. 15, address signals PIA5-1 are supplied as lower addresses, address signals PSA8-6 are supplied as upper addresses, and input data is read at the timing of the rise of clock pulse MC1. Therefore, the signal INr indicated by the symbol P1 in FIG.
When T is output, at this point the buffer register 16 (
Segment data (late count data R) of channel CHO and segment O output from
CDo and Emperor Account Data (ECDo)
are sequentially read into the selector register 75, and then the read data is sequentially read into the segment count memory 76. Thereafter, each segment data of segments ① to ② of channel CHO is sequentially read into the memory 76 every time the signal INIT is output. [4] Segment performance The data transfer to the memories 54 to 76 described above is performed during one cycle period (25 seconds) of the clock pulse INITCLK shown in FIG.
This is done while the signal INIT is output 16 times at 6 μsg). Then, the clock pulse INITCL
When K rises to "1", data "00...01" in the init register 31 shown in FIG. 5 is read into the run register 32. Each of the 16 bits output from the run register 32 is inverted by an inverter 36 and supplied to each bit reset terminal of the init register 31 and start command register 30, respectively. This results in
The bits of registers 30 and 31 corresponding to the "1" bit of run register 32 are reset. Further, a "0" signal among the outputs (16 bits) of the inverter 36 prohibits input of the corresponding bit of the start command register 30. Also, the output of the run register 32 is output from the run multiplexer 3.
5. The run multiplexer 35 outputs the signal of the O-th bit of the run register 32 when the channel address signals CHA3-0 are rOJ, and when the channel address signals CHA3-0 are rOJ,
When IJ, the signal at the first pit of the run register 32 is output, and when CHA3-0 is "15", the signal at the 15th bit of the run register 32 is output (parallel-to-serial conversion is performed). The output of this run multiplexer 35 is the signal RUN
-1 is supplied to the reset terminal R of the flip-flop 37. The flip-flop 31 receives the signal RtJN-1
is delayed by 1 base clock time and output as signal RUN. Note that FIG. 13(c) shows the waveform of the signal RLIN-1. When these signals RLIN-1 and RtJN are output, the blind channel (in the example of FIG. 13,
Channel C) 10) segment calculation, envelope and phase calculation, and tone waveform calculation are performed, thereby forming a musical tone. Further, the output of the run register 32 is supplied to the key assigner 103 (FIG. 3) via the bus driver 33 and data bus 18. The u 1 +t bit of the run register 32 is reset when musical tone formation is completed, and therefore the output of the run register 32 indicates the channel on which musical tone formation is currently being performed. The key assigner 103 uses the output of the run register 32 to detect in which channel tone formation is currently being performed. Next, segment calculation will be explained. First, the segment memory 22 in FIG.
It has 0th to 15th memory slots (1 slot - 4 bits) corresponding to 5, respectively, and a channel address signal CHA.
3 to 0 (see FIG. 15(c)) are supplied to the address terminal AD, and the signal IAI of the first bit of the address signal IA5 to 0 is supplied to the read/write terminal R/W. The 0th to 15th memory slots of this segment memory 22
,°. Each data in the loft is channel C)-to-CH
15 indicates the number of the segment currently being executed. For example, the data in the O-th to third storage slots are each r
3J, r2J, and r5J indicate that musical tones of segments ①, ②, and ② are currently being formed in each of channels CH◯ to CH3. The data read from segment memory 22 is delayed by one base clock time by selector register 21 and output as address signals PSA9-6. Then, the lower three bits PSA8-6 of this address signal PSA9-6
is supplied to address terminal AD2 of segment count memory 76 (FIG. 6). Note that this segment memory 22 is reset in the morning. Immediately, when the sound generation is assigned to channel CHO and the writing of the area corresponding to channel CHO in segment count memory 76 is completed, the data in the Oth storage slot corresponding to channel CHO in segment memory 22 is "0". Therefore, the signal RUN-1 (FIG. 15(d)) rises to "1'", and then the signal RUN (FIG. 15(e)) rises to "1".
At the point in time, address signals PSA8 to PSA6 become "
0'', and this data [0, 1 is supplied to the address terminal AD2 of the segment count memory 76. Also,
The address terminal ADI of the memory 76 is supplied with an address signal P[A5-1 (FIG. 15)). As a result, when address signals PIA5-1 are rOJ, rate count data RCDo corresponding to channel CHO and segment 1-■ is read from segment count memory 76, and address signals PIA5-1 are "1".
When , channel C is sent from segment count memory 76.
Envelope count data ECD corresponding to HO and segment O is output one after another (see FIG. 15(S)).
The signal is supplied to a distribution circuit 77. Distribution circuit 77 is a circuit that outputs input data from output terminal A or B in accordance with signal PIAI. At the time when data 1 (CDO) is read from the segment count memory 76, the signal PIA1 (FIG. 15 (
The rate count data RCO and the envelope data r+co are output from the output terminal B of the distribution circuit 77. a- Data contents of count data ECD and these data RCD, EC
An overview of the processing of D will be explained. First, the envelope count data ECD is, for example, 16-bit numerical data as shown in Table 3. Table 3 Envelope account data ECD as shown in Table 3
In each segment, "1" is repeatedly subtracted from the initial value at a predetermined cycle, and when the subtraction result becomes rOJ, the segment ends and the next segment is started. For example, the data ECD regarding segment O is r167J, N66J,
... "1" and sequentially decrease by "1", then data EC
When D becomes "O", segment (2) ends. Further, the late count data RCD is, for example, 16-bit data as shown in Table 4. The lower 7 bits are numerical data indicating the cycle of repeatedly subtracting "1" from the envelope count data ECD mentioned above, the 7th bit is a HOLD signal, and the upper 8 bits are the lower 7 bits. The data represents the result of subtraction when "1" is sequentially subtracted from the displayed numerical value. In this case, the HOLD signal is a control signal for sustaining musical tones in the same state, and in the case of sustained musical tones (organ sounds, etc.), the rate count
, 1-10LD signal of RCDa (rate count data corresponding to segment 2) becomes "1". Note that it is only in this case that the HOLD signal becomes '1'°. Table 4 The upper 8 bits of this late count data RCD are as follows:
First, the numerical data of the lower 7 bits is transferred as is, and then the data shows the value obtained by sequentially subtracting (°1) from this numerical value at a certain timing.For example, in segment ◎,
Since the data of the lower 7 bits of data RCD is "21", the data of the upper 8 bits are r21j, r20J, r1
9J... will change sequentially to "1". Data R
When the data in the upper 8 bits of the CD becomes "0", the numerical data in the lower 7 bits is transferred to the upper 8 bits again, and at this timing, the envelope count data ECD is subtracted by "1", and henceforth. This is repeated. In this way, envelope account data ECo and rate count data RCD
By determining the time of each segment by
The length of each segment can be finely set arbitrarily using a small number of bits overall. In the following explanation, each of the data ECD and RCD is assumed to be 2'-function data, so subtraction of "1" is performed by addition of "1". Now, the upper 8 bits of the rate count data RCDo output from the output terminal B of the distribution circuit 77 are applied to the input terminal A of the data selector 80, and the lower 7 bits are applied to the input terminal B of the data selector 80. Furthermore, "0" is applied to the seventh bit of the input terminal B of the selector 80. The data selector 80 outputs the data at the input terminal B when the output of the NOR circuit 83 which takes the NOR of each bit of the data supplied to the input terminal A is 1''.
When , the data of input terminal A is output. In this case, the upper 8 bits of rate count data RCD o are all 0''
Therefore, the same data RCD. 8-bit data obtained by adding 0'' to the lower 7 bits of is output from the data selector 80 and input to the input terminal A of the adder
supplied to The adder 81 connects the output of the data selector 80 and the output of the OR gate 84 (II 1 IT or “'O
”). The output of the inverter 72 is supplied to the first input terminal of the OR gate 84, and the seventh pit of the data RCD output from the output terminal B of the distribution circuit 77 is supplied to the input terminal of the inverter 72, that is, , HO1, and D signals are supplied to the second input terminal of the OR gate 84. Furthermore, the decay request signal DEQ mentioned above is supplied to the second input terminal of the OR gate 84. Therefore, when the HOLD signal is "ON", the output of the inverter 72 becomes “1”, and this 1” is the or gate 8
4 to the input terminal B of the adder 81. As a result, "1" is added to the output data of the data selector 80 by the adder 81, and the result of this addition is supplied to the upper 8 bits of the input terminal B of the data selector 73. Further, the lower 8 bits of the input terminal B of the data selector 73 are supplied with the lower 8 bits of the rate count data RCD output from the distribution circuit 77. The data selector 73 outputs the data at the input terminal B when the address signal P[A1 (FIG. 15(G)) is "0", and outputs the data at the input terminal A when the address signal P[A1 (FIG. 15(G)) is "1". In this case, the data at input terminal B is data selector 7.
3 and is supplied to the selector register 75. Then, this data is read into the same register 75 at the timing of clock pulse MCLK3, and then read into the segment count memory 76 at the timing of clock pulse MCLK1. In this way, the time To shown in FIG. At the timing of , data RCDo first reads 8ゎ, 8□ah. . at, -r1J#m'
(“1” is subtracted), and then the data after this addition is used as the upper 8 bits, and the data before the addition RCDo is used as the lower 8 bits is again the data R in the memory 76.
CD, is written to the location. Next, at the timing To+ shown in FIG. 15, the envelope count data ECD is read from the segment count memory 76, and the distribution circuit 77
supplied to At this time, the signal PIAI is the °1"1" signal, and therefore the data ECD is output from the output terminal of the distribution circuit 77 and supplied to the input terminal A of the adder 78. The output of the OR gate 82 is supplied to the input terminal of the adder 78, the dump request signal DAQ (usually "0") is supplied to the first input terminal of the OR gate 82, and the delay circuit (delay circuit) is supplied to the second input terminal of the OR gate 82. time - 2 base clock time)
85 outputs are provided. Further, a signal from the carry terminal CO of the adder 81 is supplied to the input terminal of the delay circuit 85. At the above-mentioned time T'oo, the carry output of the adder 81 is "O", and therefore at the time To+, the output of the delay circuit 85 is "0", and this signal "O" is sent to the adder 78 via the OR gate 82. is supplied to input terminal B. As a result, adder 78
The envelope account data ECDo supplied to the input terminal A of is outputted as is from the adder 78 and supplied to the input terminal A of the data selector 73. At this time, the signal PIAI is 1'', so the envelope count data ECD output from the adder 78 is output from the selector 73, read into the selector register 75, and then read into the segment count memory 76. At time To+, envelope count data ECD,
is read out, and when the output of the delay circuit 85 is "0", the read data ECD is written to the same storage location in the memory 76 again. Thereafter, each time the address signals PIA5 to 1 (FIG. 15(f)) become "0", the rate count data RCDo is set to "1".
” is added, and address signals PIA5-1 are added “1
'', the envelope account data ECD is read from the memory 76 and then written to the same memory 76. Then, when the ``1'' signal is output from the carry terminal CO of the adder 81 (when the upper 8 bits of the data RCDo become ``0''), the ``1'' signal is output from the delay circuit 85 with a delay of 2 base clock times. , is supplied to the input terminal B of the adder 78 via the OR gate 82. As a result, the envelope account data ECDo is supplied with "1".
” is added (“1” is subtracted). Below, fLJ
The process of I is repeated, and when a "1" signal is output from the carry terminal co of the adder 78 (when the data ECD becomes rOJ), this "1" signal becomes the signal F.
It is supplied as CC to the carry-in terminal CI of the adder 25 shown in FIG. The above is the time measurement process for channel CH○ and segment 0. [Blank below] On the other hand, the data corresponding to the channel CHO (rOJ in this case) in the ITO storage slot of the segment memory 22 in FIG.
It is read out and supplied to the register 24 every time it reaches rOJ. The register 24 delays the supplied data by one base clock time and outputs it to the input terminal B of the adder 25. Data ED is supplied to an input terminal A of the 7der 25 from a decay dump control circuit 29 . This data ED is always rOJ, so the output data of the register 24 is the carry-in terminal C of the adder 25.
When the signal FCC (“1” signal) is not supplied to I, it is output as is from the 7der 25, and the AND gate 26
supplied to The AND gate 26 receives the signal R(JN (
When Fig. 15 (e)) is “1”, it is open and the adder 25
The output of the segment memory 22 is supplied to the input end of the segment memory 22. Therefore, the channel of segment memory 22
The contents of the 0th memory slot corresponding to channel CHO, ICHO are "0" in the initial state, and continue to be "0" even after the signal RLIN rises to 1'', and the signal ECC ( It becomes (1) (indicating segment ■) only when the "1" signal) is supplied to the adder 25. When the content of the 0th memory slot corresponding to channel CHO of the segment memory 22 becomes "1", the address signal PSA8 to 6 become "1", and this address signal "1"
is supplied to address terminal AD2 of segment count memory 76 in FIG. As a result, from now on, every time the address signals PIA5-1 become "0" in response to the channel C1 (O), the rate count data RCD+ (corresponding to segment ■) becomes "1" and the signal PIA5-1 becomes "1". Each time, the envelope a-account data ECD+ is read from the segment count memory 76, and the time measurement of segment (2) is performed in the same manner as in the case described above.Then, the signal ECC is outputted from the carry terminal co of the adder 78 again. and channel CHO of segment operation 22 (Figure 5).
The content of the 0th memory slot corresponding to becomes 1°21,
Thereafter, the time measurement of segment (2) is performed, and when the time measurement of this segment (2) is completed, the time measurement of segments (2) to (2) is then performed sequentially. The above is the process of segment calculation. Note that the above process is the segment calculation process for channel CHO, but also for channels C)-11 to CH15, the pronunciation v1
If a guess is made, it is done in the same way. in this case,
The time measurement of channel CH1 is carried out at time T1 shown in FIG.
15 is performed at time T's shown in the figure. In addition, in the above process, when the l-10LD signal is "1", the output of the inverter 72 becomes "OIT", and therefore the output of the OR gate 84 becomes "0", and this
The '' signal is supplied to input terminal B of adder 81. As a result, the addition of "+1" in the adder 81 is not performed,
Segment calculation substantially stops, and thereafter the segment continues in the state of ■. In this case, the segment processing after the 11 hub will be explained in the subsequent key-off processing. [5] Envelope calculation When entering the musical tone calculation period Tg shown in FIG. 13, the area corresponding to the channel CHO of the envelope calculation memory 54 (see FIG. 14) in FIG. , I 21NTIA I
NT are stored respectively, and envelope increment values Δim+Δ1211 . ΔA
,,Δ■11. ΔI21. ΔA+, = Δ117, Δ12
1. ΔA7 is stored respectively (area EO in Figure 9).
reference). In this state, address signals PIA5-0
When becomes [0-1 corresponding to channel Cl-1o, (
At the time T a o shown in FIG. 16A (a)), the initial value TIINT corresponding to the channel CHO is output from the envelope calculation memory 54 (see FIG. 16A (b)).
, the envelope increment value memory 66 outputs an increment value ΔI 10 corresponding to the channel CHO (see FIG. 16A (c)). The output of the envelope increment value memory 66 is also supplied to the input terminal A of the data selector 59.
When the LD signal is "1"), data rOJ is output, and when the output of the inverter 72 is "1", when the dump request signal DAQ is "0", data is output to the input terminal, and the same When the signal DAQ is "1", the data at the input terminal B is output.At time Ta0 in FIG. 16A, the output of the inverter 72 is "1'", and the dump request signal DAQ is
is “0”, and therefore, the output Δ1111 of the envelope increment value memory 66 is supplied to the input terminal B of the adder 57 via the data selector 59. As a result, data (■+11ff+Δll0) is output from the adder 57 and supplied to the input terminal A of the adder 58. External control data is supplied to input terminal B of this adder 58. '-0 External 0''''0-''Data'1/Example 11 Performance* i
b< , ,. This data is supplied when it is desired to directly control the timbre, timbre, etc. of the generated musical tone during a performance, or when it is desired to add periodic modulation to the timbre or timbre, and is normally set to "0". Therefore, normally, the data supplied to the input terminal A of the adder 58 is outputted from the adder 58 as is, and the selector register 51 receives the data at the timing of the clock pulse MCLK3.
is read into. Then, this read data is ENV
It is output from the same register 51 as DATA15~○ (
The signal is supplied to the musical tone calculation circuit shown in FIG. 16A (d) and FIG. 7, and is again stored in the envelope calculation memory 54. In this way, the period Ta during which the signals PIA5-0 are "0"
In o, data I++NT corresponding to channel CHO is read from memory 54, and then this data I++NT is read from memory 54.
Data Δ11G is added to I INT, and the addition result 111NT+ΔI 10 is output as 6ENVDATA15 to O regarding data 1 of channel CH○, and is also written to the location in memory 54 where data 111NT was stored. Next, when the signals PrA3-O become 11'', data I21NT+Δ120 is output as ENVDATAI 5-0, and this data is written into the memory 54, similarly to the case described above. Then the signals PTA5-O
is set to [31], data A+Nr+ΔAo of channel CHO is output as ENVDATA15-0, and this data is also written into the memory 54. The above is the processing for channel CHO, and from now on, signal PIA
When 5-0 are "4-7", processing for channel CH1 is performed, ..., signal PIA5-0 is "60-63"
At this time, processing of channel CH15 is performed. Next, when the signals PIA5-0 become rOJ again, data IIIINT+ΔI 10 is read from the memory 54, ΔI m is added to this read data, and the addition result 111NT+2ΔI IQ is ENVDATAI 5-
It is output as 0 and written again into the memory 54, and the same process is repeated thereafter (see FIG. 16B). The above is the process of envelope calculation, and in this way, the calculations of equations (5) to (a) above, that is, the calculation of A-ΣΔA + A INT B = ΣΔT I+ I I + tir 12 zLΔrz + 121NT are performed. . Note that when the output of the inverter 72 is 0'' (when the H○LD signal is 1'), the output of the data selector 59 is rOJ, and therefore the data read from the memory 54 remains unchanged (the increment value is added). )ENVDATA
It is output as 5-0 and is also rewritten into memory 54. In this case, of course, the envelope data Δ, [I,
12 remains unchanged. Note that, in reality, the output of the inverter 72 is supplied to the data selector 59 via a timing adjustment circuit, but a description of this point will be omitted. [6] Phase calculation The process of this phase calculation is almost the same as the envelope calculation process described above, so a detailed explanation will be omitted.
16A and 768 are the outputs of the phase calculation memory 551 and the phase increment value memory 67, respectively.
REQDATA15-O is shown. This data FREQ
[)ATA15-0 are supplied to the musical tone calculation circuit shown in FIG. This phase calculation is the calculation of equations (2) to (4) described above, that is, ω l t 8 Σ Δ ω tan + ω l
The calculation is l1tTωZ t=ΣΔω2+ω21NT ωojxΣΔω0+ωOllv′r. Note that the external control data supplied to the input terminal B of the adder 61 is frequency modulated (
For example, this data is supplied when applying vibrato), and is "0" when frequency modulation is not applied. [7] Musical sound waveform calculation This musical soundwaveform calculation is a calculation for forming a musical soundwaveform, and is performed by the musical sound calculation circuit shown in FIG.
VDA1'A15~o and FREQDATA15~0
This is done using In FIG. 7, reference numeral 47 is a microprogram memory (ROM), and this memory 47 stores in advance 64 steps (1 step=16 bits) of microinstructions shown in FIG. In FIG. 17, the O mark indicates a "1'' signal, and the blank space indicates an "On signal. For example, the instruction TO in the first line of the figure is the instruction "OO...01111".
The name of each bit signal is written at the top of the diagram. The function of each bit signal is as follows.・Channel address signals CHA3 to 0 (15th to 1st
2 bits) As mentioned above, this is a signal indicating the processing timing for each of channels CHO-CH15 (Fig. 12,
(See Figure 15). - Gate signal GATE MULK (seventh pit) When this gate signal GATE MLILK becomes 1", the gate circuit 92 shown in FIG. 7 becomes open. In this embodiment, this gate signal GATE
MIJLK is not used, so the output of the gate circuit 92 is always at the "O11 signal" (see Figure 18 (power)). However, based on the other equations included in equation (1) above, When performing musical tone signal formation, this gate signal GATE MULK is required. - Select signal FREQ 5FL (6th bit) When this select signal FREQ SEL becomes 0''', the input terminal of selector register R3 in FIG. A is selected,
When it becomes "1", input terminal B is selected. - Load signal LDB (fifth pit) When this load signal LDB becomes "1", data is read into the output buffer 93 in FIG.・Load signal LDR5 (4th bit) When this load signal R5 becomes "1", data is read into register R5 (Fig. 7). ・Load signal LDR4 (3rd bit) This load signal LDR4 becomes “1”, register R
4, the data is read.・Load signal LDR3 (second bit) When this load signal MLDR3 becomes “1”, register R
3, the data selected by the above-mentioned select signal FREQ SEL is read. - Load signal LDR2 (first bit) When this load signal IDR2 becomes II 1 II, data is read into the register R2.・Load signal IDR1 (Oth bit) When this load signal LDR1 becomes 1'', register R
Data is read into 1. In addition, the numbers written inside the O mark in Figure 17 are
Channels CHO to CH1 processed by that signal
It shows the number 5. Each instruction in the microprogram memory 47 mentioned above is read out by address signals rA5-0. That is,
When the address signals IA5-0 are rOJ, the instruction T in FIG.
O is read out, and when it is "1", instruction T1 is read out, and so on.
, "63", instruction T63 is read out. Of the bit signals included in the read instruction, the channel address signals CH3 to CH0 are output to each part of the circuit shown in FIGS. After being delayed by the load time, it is output to FIG. Next, the operation of the circuit shown in FIG. 7 will be explained in FIGS. 17 and 18.
This will be explained with reference to the figures. First, FIG. 18 shows clock pulses MCLK1. Address signals FA5-O, PIA5-O
, ENVDATA15~O. FREQDATAl 5 to 0tiJ: This is a timing diagram showing the interrelationship of the outputs of the numbered part in Figure 7. In this figure, the numbers rOJ and NJ at the lower right corner of the rectangular frame each indicate a channel number. Furthermore, each microinstruction TO-T63 in the microprogram memory 47 in FIG. 7 is constantly and repeatedly read out by the address signals IA5-O (FIG. 18(b)) as described above. , each read microinstruction TO-T63 is delayed by one base clock time by the instruction register 48 and outputted to each section in FIG.
Figure (c)) shows address signals IA5 to IA0 as 1 base square.
☆This is a signal with a lock time delay. Therefore, as shown in FIGS. 18(c) and (f), when the address signals PIA5-O are rOJ, the microinstruction To is output from the instruction register 48, and...
, when address signals PTA5-O are "63", microinstruction T63 is output from instruction register 48. In addition, the data ENVDATA15 to 0 and F
The timings at which REQDATAI 5 to 0 are supplied to the circuit in FIG. 7 are shown in FIGS. 16A, 16B (d) and (
These data are as shown in
It is transcribed in Figures 8 (d) and (e). In addition, the first
In Figure 8 (E), ω blindness, ω2. ω+ instead of ω0
t, ω2t, ωot, as mentioned above (1
This is to make the correspondence with formula a) easier to understand. The operation of the circuit shown in FIG. 7 will be described below with reference to FIG. First, the time 10 (
(See the bottom of FIG. 18), the microinstruction TO is output from the instruction register 48 in FIG. Also, at this time, the input terminal of the register R1 is supplied with the ENVDATAi 5 to 0 (+J) of the channel CHO, and the FREQDATAi 5 to 0 of the channel CHO is supplied to the input terminal A of the selector register R3.
is supplied. When the microinstruction To is output from the instruction register 48, the load signal LDR
1 to LDR4 (see Figure 17) are registers R1 to R, respectively.
4. Here, the load signals LDRI, LDR
3 is a signal for forming a musical tone signal of channel CHO, while load signals LDR2 and LDR4 are signals for forming a musical tone signal of channel CH15. From F
Only the case of forming a musical tone signal of 1 channel V channel CHO will be explained. When load signals DRl and LOR3 are supplied to registers R1 and R3, respectively, register R
The above data It and ω1t are applied to 1a'3 and R3, respectively.
is read (see Figure 18 (G) and (S)). In addition, at this time, the select signal FREQ
SEL is '0'°, and input terminal A of register R3
b<selected. When data ωIt is read into register R3, this data ω1t is stored in design table 96.
ω is supplied from the sign table 96 to
1t is output (see FIG. 18(E)). Next, at time t1, EN is sent to the input terminal of register R1.
VDATAl 5~0rI2J is also sent to input terminal A of register R3 FREQDATAl 5~0[ω2 and 1
are supplied respectively, and the instruction register 4
8, a microinstruction T1 (see FIG. 17) is issued. This microinstruction T1 causes the load signal LDRI to
~LDR4 and select signal FREQ SEL are supplied to registers R1 to R4, respectively. Load signal LDR
When I is supplied to register R1, E is stored in register R1.
NV DATA15~O “■2” is read (first
Figure 8 (g)). Also, load signal LDR2 is input to register R
2, I'l+J is read into register R2 (FIG. 18(h)) and output to multiplier 90. Further, when the load signal LDR4 is supplied to the register R4, "5III ω electric t" is read into the register R4 (FIG. 18(S)), and is output to the multiplier 90. As a result,
The multiplier 90 outputs "r I I 5illω1 t" (FIG. 18 (wa)), and the adder 91
5 is supplied to input terminal B of 5. As a result, adder 95
[ω2 i+ I + smQ)1 t J is outputted from the input terminal B and supplied to the input terminal B of the selector register R3. In addition, load signal LDR3 and select signal FRE
When Q SEL is supplied to selector register R3,
The data at the input terminal B of the register R3, that is, the above-mentioned [ω2i+ll5illω+tJ is
(Figure 18). This register R
The above data is read into the sign table 96.
When supplied to [5Irl
(ω2i:+I+si+ω1t)” is output (first
Figure 8 (e)). Next, when the time reaches 2, the microinstruction T2 is output from the instruction register 48. As a result, the load signals LDR2 and LDR4 are
11 are supplied to registers R2 and R4, and each data shown in FIG. 18 is read into each register R2 and R4. Note that the data in registers R1 and R3 are the same as the data at time t1. At this time, sign table 9
62 multiplier 90. Each output of the adder 91 is as shown in the figure. Next, at time t3, microinstruction T3 is output from instruction register 48. As a result, load signals LDR1, LDR3 and select signal FREQ SEL are supplied to registers R1 to R3, respectively. When the load signal LDRI is supplied to the register R1, data A is read into the register R1. on the other hand,
At this time t3, the data in registers R2 and R4 are the same as the data at time t2. Therefore, the output of the multiplier 90 will be the same as time t2, and this data (
(see FIG. 18(W)) is connected to the adder 95 via the adder 91.
Since the adder 95 supplies ωat+[z
sIi (ωzj+l+s−ω+1) is output and supplied to the input terminal B of the register R3. Therefore, when the load signal LDR3 and the select signal FREQ SEL are each supplied to the register R3 at time t3, the data at the input terminal B of the register R3 described above is read into the same register R3 (see FIG. 18), and the sign It is output to the table 96 (FIG. 18 (e)). Next, at time t4, microinstruction T4 is output from instruction register 48. As a result, the load signals Lr)R1 to LDR4 are supplied to the registers R1 to R4, respectively, and each data shown in the figure is read into the registers R1 to R4. Here, register R2,
Each data read into R4 is data for forming a musical tone signal of channel CHO, but registers R1 and R
The data read into channel CH1 is data for forming the musical tone signal of channel CH1. That is, this time t
Formation of a musical tone signal for channel CHI starts from 4. Data rAJ and data 5ilt (ωot+Izsn(ω2t+I+s+nω) are stored in registers R2 and R4, respectively.
1 t)) is read, the multiplier 90 outputs As+n(ωo 'j+12sin (ω2 t
+Its+na)+t)), i.e., the above (1a) in channel CHO)
The tone waveform data of the expression is output, and this data is added to the adder 9.
1 to the input of register R5. Next, at time t5, microinstruction T5 is output from instruction register 48. As a result, the load signal LDR5 is supplied to the register R5, and the above data is read into the register R5 (first
Figure 8 (see Run). Next, at time t6, microinstruction T6 is output from instruction register 48. As a result, the load signal LDB is supplied to the output buffer 93, and the data As+n(ωot+Izs+n(ωzi+I+s+nω) regarding the channel CHO in the register R5 is
+1)) is read into the output buffer 93 (Fig.
evening)). Then, the data read into the output buffer 93 is converted into an analog signal by the D-Δ converter 94, and is output as a musical tone from a speaker (path shown). The above is the process of forming the musical tone signal of channel CHO, and as described above, the musical tone signal of channel CHO is formed between address signals PIA5-0 of "0-6". Further, each musical tone signal of channels CH1 to CH15 is also formed in exactly the same process. In this case, channel CH
The musical tone signal of channel CH2 is formed when the signals PIA5-0 are "4-10", and the musical tone signal of channel CH2 is formed when the signals PIA5-0 are "4-10".
Formed when 0 is "8 to 14", ..., channel C
The musical tone signal H15 is generated when the signals PIA5-0 are "60-2". Therefore, the operation of the circuit shown in FIG. 7 described above is constantly repeated. Therefore, for example, sound generation is assigned to channel CHO, and then the data transfer period T in FIG.
At t, various data regarding channel CHO are transferred, and then musical tone calculation 11 Tg shown in FIG. 13 is entered, and channel /L, CHO (7) ENVDATA15
~OJ:biFRE +QDATA15~
When 0 is sequentially supplied to the circuit of FIG. 7 at the timing of signals PIA5-0 "0-3", a musical tone signal of channel CHO is formed in the above process. On the other hand, when the sound generation assignment for channel CHO is not performed, the above-mentioned channel CHO (7) ENVDATAl 5~O, FR
Both EQDATA15 to 0 become rOJ, and musical tone formation is not performed. [8] Key-off processing The key that was pressed in the key group 102 (Fig. 3) is +ms
Then, as described above, the key assigner 103 selects the channel (C
Outputs a decay command or a dump command to instruct the end of sound generation of HO to CH15). The processes performed in response to these commands will be described below. Q) Processing for the Decay command For example, when instructing the end of sound on channel CHO, -Key Assigner 1
03 is a 16-bit decay command “00...01
"(0th bit is 1", other bits are "O") is output together with the address signal. This decay command is
The command is read into the decay command register 38 shown in the figure. Then, when the clock pulse INITCLK rises, the decay command in the register 38 is read into the decay register 39 and supplied to the decay multiplexer 40. The decay multiplexer 40 is a component of the init multiplexer 34. It has the same configuration as the run multiplexer 35, and the channel address signals CHA3 to CHA0 are r
When OJ, the signal of the 0th bit of the data (16 bits) at the input end is output, and when CH3-0 is "15", the signal of the 15th bit of the data at the input end is output. The output of this decay multiplexer 40 is delayed by one base clock time by a register 41, and then the signal DE
It is output to the decay dump control circuit 29 as CAY. The decay dump control circuit 29 detects that a decay command is output in the channel CHO based on the signal DECAY, and outputs the decay request signal DEQ at the timing when the address signals PIA5 to 0 are "0 to 3". , perform the following processing. That is, when the data in the 0th memory slot corresponding to channel CHO of the segment memory 22 is output from the register 24, this data is checked and the next data ED is input to the adder 25 according to the value of the data. Output to the terminal. Output of register 24 ED Through this processing, even if the musical tone formation of channel CHO at that point is in any of the segments ◎ to ■, the musical tone formation shifts to segment ■ in a strong III manner,
Thereafter, musical tone formation for segments 1 to 2 is performed. Furthermore, when the musical tone formation of channels CH and O is in any of the segments ① to ②, the musical tone formation continues as it is. The above is the processing for the Decay command. (i) Processing for dump commands For example, when rapidly ending the sound of channel CHO, the key assigner 103 uses the 16-bit dump command "00...01".
n (Oth bit is "1°.") is output together with the address signal. This dump command is read into the dump command register 42 shown in FIG. The dump command within is read into the dump register 43 and supplied to the dump multiplexer 44. The dump multiplexer 44, like the decay multiplexer 40, receives the channel address signal CHA.
The data (16 bits) supplied to the input terminal is converted into serial data based on 3 to 0, and is output to the register 41. Register 41 delays the output of dump multiplexer 44 by one base clock time and outputs it to decay dump control circuit 29 as signal OAMP. Decay dump control circuit 29 detects that a dump command for channel CHO has been output based on this signal DAMP, and thereafter, when address signals PIA5-0 are "O-3", damping and quest signal DAQ ( “1
”) is output to the data selector 59 shown in the lower left part of FIG.
+, rz, and A are each reduced to r-1/6 by the attenuation circuit 63.
4J, and the adder 5 is attenuated through the data selector 59.
7. As a result, the generated musical tones are rapidly attenuated. The above is the processing for the dump command. Note that in the case of berkussive musical tones, segments ◎ to ■ may have already ended at the time of key-off. In such a case, of course, the decay and dump commands are not output from the key assigner 103.

[9] Sound generation end processing Sound generation ends when the data in the segment memory 22 in FIG. In other words, the third bit of the output of the register 24 in FIG. is data rAJ 1.:SekiTruE
When NVDATA15 to 0 become negative, the signal RER (“1
This signal RER is supplied to the second input terminal of the OR gate 27. As a result, when the sound generation ends, the OR gate 27 outputs a "1" signal, which is supplied to the sound generation end processing circuit 28. The sound generation end processing circuit 28 determines which channel (C
It detects whether the sound generation of HO-CHl 5) has ended and outputs a 16-bit signal SFC indicating the ended channel (C)-1o to CH15). For example, channel CHO
is completed, “11...10” is output as the signal SFC.
(The Oth bit is “'O”) is output. This signal SFC
is run register 32. Decay register 39. It is supplied to the dumb register 43, thereby resetting each Oth bit of these registers 32, 39, and 43. When the 0th pit of the run register 32 is reset, since the output of the run register 32 is being supplied to the key assigner 103, the key assigner 103
The end of the HO sound generation is detected, and a new sound generation assignment is made to the channel CHO for the subsequent key-on. In the description of the above embodiments, the present invention is applied to a Unibu generator for an electronic organ, but the present invention can of course be applied to other similar Unibu generators other than electronic organs. [Effects of the Invention] As explained in detail above, according to the present invention, a first frequency signal in the audible frequency range is frequency-modulated according to a second frequency signal also in the audible frequency range, and a signal obtained by this frequency modulation is obtained. The third frequency signal in the audible frequency range is frequency-modulated according to the signal obtained by the frequency modulation, and the signal obtained by this frequency modulation is used to form a musical tone, which has a natural sound with a complex number of harmonic components. This has the effect of allowing musical tones to be formed with a simple structure.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are a block diagram and an envelope waveform diagram of a musical tone signal, respectively, for explaining the basic principle of musical sound waveform formation used in one embodiment of the present invention.
The figure is a block diagram showing the configuration of an electronic organ to which an embodiment of the present invention is applied, FIGS. The figure is a waveform diagram of various clock pulses used in the same embodiment, and FIGS. 9 to 11 respectively show the incremental value data memory 11 and the initial value data memory 1 in the same embodiment.
3. A diagram showing the storage contents of the segment data memory 15. FIG. 12 is a timing chart for explaining the process of transferring data in the memories 11, 13, and 15 to the memories 54, 55, and 66°67.76, respectively. , FIG. 13 shows the signal I
A timing chart for explaining NIT-+'11 and signal RUN-1, FIG. 14 is a diagram showing the stored contents of the memory 54, 55, and FIG. 15 is for explaining the time measurement process of each segment ◎ to ■. timing chart, 16th A
168 is a timing chart for explaining the process of envelope and phase calculation, and FIG. 168 is a continuation of FIG. 16Δ. FIG. 17 is a diagram showing microinstructions output from the microprogram memory 47, and FIG. 18 is a timing chart for explaining the operation of the musical tone calculation circuit shown in FIG. 7. ACCI~ACC3...Accumulator, 5IN1~5
IN3...Sign table, M1~M3...
. . . Multiplier, ADDl, ADD2 . . . Adder, 47 . . . Micro program memory, 48.
...Instruction register, 90...
... Multiplier, 91 ... Adder, 93 ...
・Output buffer? , 95... Adder, 96...
...Nine tables, R1, R2, R4, R5...
...Register, R3...Selector register. l3 Figure 10 15 Figure 11 PtA2-5 Memory 55 Figure 14

Claims (1)

[Claims] frequency modulating a first frequency signal in the audio frequency range according to a second frequency signal also in the audio frequency range, frequency modulating a third frequency signal in the audio frequency range according to the signal obtained by this frequency modulation, and A musical tone forming method characterized in that a musical tone is formed based on a signal obtained by frequency modulation.