JPS6114519B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument that can generate musical tones whose volume, timbre, etc. change in the same way as natural musical instrument sounds. Generally, the volume and timbre of sounds generated by natural musical instruments change depending on the range of the sound. for example,
In the case of piano sounds, the volume is low in the high range and the volume decay time is short, whereas the volume is high in the low range, the volume decay time is long, and the musical sound contains many harmonic components. It has the following characteristics. Similarly, for other musical instruments, the volume and timbre change depending on the range of the sound, depending on the characteristics of the type of instrument. Therefore, when trying to form musical tones corresponding to natural instrument sounds in an electronic musical instrument, it is necessary to control the volume and timbre of the musical sounds so as to match the characteristics of the natural instrument sounds. In consideration of the above points, the present invention provides an electronic musical instrument that fully satisfies the above-mentioned requirements, and allows for the creation of high-quality musical tones that vary in volume and timbre in the same way as natural musical instrument sounds. The purpose is to In order to achieve the above object, the electronic musical instrument according to the present invention includes pitch specifying means for selecting and specifying the pitch of a musical tone;
timbre designating means for selectively designating a basic timbre of a musical tone, and a pitch selected and designated by the pitch designating means;
and a musical tone signal forming means for forming a musical tone signal corresponding to the basic tone selected and specified by the tone color specifying means, and a control waveform for controlling the tone or volume of the musical tone signal formed by the musical tone signal forming means. The control waveform generating means to be generated and the constant data that determines the level of the control waveform generated from the control waveform generating means or the rate of change in the time change of this control waveform, respectively corresponding to each of the plurality of basic tones and a plurality of It has a memory stored in advance corresponding to each pitch or each of a plurality of tone ranges, and the pitch selected by the pitch designation means or the range of this pitch and the basic tone selected and designated by the tone color designation means. The present invention is characterized by comprising constant generating means for reading constant data corresponding to both target tones from the memory and supplying the control waveform generating means to the control waveform generating means. An embodiment in which the present invention is applied to an electronic musical instrument having an 88-key manual keyboard will be described in detail below with reference to the drawings. First, the electronic musical instrument of this embodiment is
A musical tone signal is formed according to a frequency modulation method as disclosed in the publication No. 126406 (Japanese Patent Application No. 49-41602). Formation of a musical tone signal using this frequency modulation method is basically performed by calculating the equation e=Asin [ω _ct + I(t) sin ω _nt ] (1).
In this embodiment, in order to generate high-quality musical tones that are more similar to natural instrument sounds, the musical tone signal forming operation of equation (1) above is performed in multiple series, and the musical tone signals of each series are added and synthesized. There is. That is, the electronic musical instrument of this embodiment further develops the above equation (1) and calculates n=1 to n=S based on the following equation (2).
Musical tones are generated by executing multiple series of musical tone signal forming operations. Here, K _o (K ₁ to _{K s} ) is a total volume constant of each series, which determines the mixing ratio of all series, and by selecting and changing this, the volume and timbre of the musical tone as a whole can be changed. T _oa (t) [T _1a (t) to T _sa (t)] is a volume selection variable for controlling the volume depending on the way the key is pressed, and weights are given to the pressing speed information when pressing the key. It is determined on the basis of an initial constant β _i for assigning the weight to the key, and an after constant βa for weighting the depression pressure information when pressing the key. A _o (t) [A ₁ (t) to A _s (t)] is a variable for giving an amplitude level or an envelope. In order to obtain the amplitude waveform ENV as shown in Fig. 16, the attack waveform part ENV ₁ The attack rate constant AR _A1 is selected to determine the attack rate of
AR _AS , the first decay rate constant 1DR A1 _to 1DR _AS selected to determine the decay speed of the first decay waveform portion ENV ₂ , and the second decay waveform portion ENV ₃
The second decay rate constant 2DR _A1 ~ 2DR _AS is selected to determine the decay speed of 2DR A1 _{~ 2DR} The transition level constant 1DL _A1 to 1DL _AS and the attenuation speed selected to determine the attenuation speed when forming the attenuated waveform portion ENV ₄ when the key is released at time t ₂₄ in the middle of the second decay waveform portion ENV ₃ . Constant DR _A1 ~
Determined based on DR _AS . The variable K _o・T _oa (t)・ in equation (2) with such content is
A _o (t) corresponds to the amplitude constant A in equation (1). Further, B _o [B ₁ to _{B s} ] is a pitch constant selected to determine the musical tone frequency, that is, the pitch, and represents the amount of change in frequency of each series of musical tone signals with respect to the reference angular frequency ω. The variable B _o ·ω in equation (2) having such content corresponds to the carrier wave angular velocity ω _c in equation (1). Furthermore, T _oi [T _1i (t) to T _si (t)] is a timbre selection variable for controlling the timbre depending on the way the key is pressed, and weights information on the speed at which the key is pressed. The initial value for pressing the key is determined based on the constant αi and the after constant αa for weighting the depression pressure information when pressing the key. I _o (t) [I ₁ (t) to I _s (t)] is a timbre variable for determining the temporal change in timbre, and is the initial timbre constant I selected to set the timbre at the beginning of a musical tone. _L1 ~I _LS and a timbre change constant selected to determine the rate of change of timbre over time
It is determined based on DR _I1 to DR _IS and timbre change stop level constants SL _I1 to SL _IS that are selected to determine the timbre change stop level S _I that means the end level of the timbre change. The variable T _oi (t)・I _o in equation (2) with such content
(t) corresponds to the modulation degree I(t) in equation (1). D _o [D ₁ to _{D s} ] is a partial constant selected to determine the modulation frequency, and by changing this constant, the composition of the partial components (consisting of harmonic components and non-harmonic components) included in the musical tone signal can be changed. changes. The variable D _o ·ω in equation (2) having such content corresponds to the frequency modulation angular velocity ω _n in equation (1). By the way, formula (2) is expressed as a general formula, but in the example described below, when S=2,
That is, e=K ₁・T _1a (t)・A ₁ (t)・sin [B ₁・ωt+T _1i (t)・I ₁ (t)・sinD ₁・ωt] +K ₂・T _2a (t)・A ₂ (t)・sin [B ₂・ωt+T _2i (t)・I ₂ (t)・sinD ₂・ωt] …Based on the formula (3), two series of musical tone signals are obtained, and these Musical tones are generated by mixing musical tone signals. The electronic musical instrument according to the present invention includes the following elements as shown in FIG. Reference numeral 1 denotes a keyboard information generation unit, which generates key information IFK containing the pressed key number and touch information containing the strength, weakness, and speed of the key press as key information related to keys operated on the keyboard. Send IFT. Reference numerals 5A and 5B denote first and second series parameter generation circuits, which output parameter outputs PA1 and PA2 regarding musical tone signal waveforms in response to the output of the tone selection switch 6 operated by the performer.
However, the parameter information generated by the generation circuits 5A and 5B is assumed to transmit information regarding timbre other than the touch information IFT of the keyboard information generation section 1 described above. 7A and 7B are first and second series musical tone signal forming units which receive key information IFK and touch information IFT from the key carrying information generating unit 1, and also receive parameter information PA1 and PA from the parameter generating circuits 5A and 5B.
2, and based on this information, two series of musical tone signals e ₁ and e ₂ respectively represented by the first and second terms of equation (3) are generated. Reference numeral 8 denotes a musical tone generating section, which is a sound system such as a speaker and an amplifier, and synthesizes the outputs e ₁ and e ₂ of the first and second series musical tone signal forming sections 7A and 7B.
A musical tone corresponding to the musical tone signal e expressed by equation (3) is generated from a speaker. However, with such a configuration, the musical tone generating section 8
The musical tone generated from the key carrying information generating section 1 has a pitch according to the key and information IFK sent out from the key carrying information generating section 1, and has a tone selected by the range selection switch 6, and furthermore, the musical tone generated by the key carrying information generating section The musical sound waveform is based on the formula of the frequency modulation signal (3).
Formed based on Eq. On the other hand, this musical tone is generated by the damper pedal signal PO musical tone signal forming section 7A generated by the damper pedal 9.
and 7B as a control signal. In this embodiment, each component shown in FIG. 1 has the detailed structure described below. [1] Keyboard information generation unit As shown in FIG. 2, the keyboard information generation unit 1 includes a key operation detection circuit 11 that detects the operation state of each key on the keyboard, and a key operation detection circuit 11 that detects the operation state of each key on the keyboard, and a key operation detection circuit 11 that detects the operation state of each key on the keyboard. A key coder 12 that determines the key number and sends out a key code signal KC that is a corresponding binary code signal, and assigns the output signal of this key coder 12 to any one of an arbitrary number of sounding channels. information
a channel processor 13 that sends out IFK;
An initial touch control circuit 1 that determines the key press speed based on the output of the channel processor 13 and sends it out as initial touch data ITD, which is a binary code signal.
4, and an aftertouch control circuit 15 that determines the strength of key depression based on the output of the key operation detection circuit 11 and sends it out as aftertouch data ATD consisting of a binary code signal. (1-1) The key operation detection circuit 11 includes a key switch group 1 consisting of, for example, two key switches K1 and K2 each having a mechanical contact configuration and provided for each key of a keyboard (88 keys in this embodiment).
1A, and a pressing pressure detection element DT of a piezoelectric element configuration, for example, provided for each key.
A pressure sensing element group 11B is provided. The key switches K1 and K2 are, for example, as shown in FIG. 3A,
As shown in B, the engager 11 is arranged in parallel to face the rear end 11D of the key 11C, and is provided on the rear end 11D when the key 11C is pressed down.
By engaging the movable contacts 11F and 11H, both switches K1 and K2 are closed. Here, the possible contacts 11F and 11H of switches K1 and K2 are connected to the engager 1.
As shown in FIG. 3C, there are stepped portions 11I and 11J of different lengths on the surface that contacts 1E.
Therefore, when the key 11C is operated, the first key switch K1 first engages with the long step 11I to close the contact in accordance with the upward movement of the engaging element 11E, and then the second key switch K2 engages with the short step portion 11J to close the contact. On the other hand, a depression pressure detection element DT is provided below the operation end 11K of the key 11C, and after the second key switch K2 is closed during the depression operation of the key 11C, the detection element DT is applied to the end 11K.
By pressing the lower surface of the 1K, a detection output dt corresponding to the pressing pressure is generated. The contact outputs k ₁ and k 2 of the first and second key switches K1 and _K2 thus obtained by the key operation detection circuit 11 are outputted to the key coder as 88 pairs of key operation detection outputs including the operated key number and operation speed. 12, and the detection output dt of the push-down pressure detection element DT includes the push-down pressure.
It is sent to the aftertouch control circuit 15 as 88 key operation detection outputs. In Fig. 3A and B, 11L is the upper limit stopper felt, and 11M is the pressure detection element.
DT's cradle, 11N is a guide, 11P is a fulcrum, and 11Q is a weight. [1-2] Key coder As shown in FIGS. 4A to 4C, the key coder 12 includes a key switch circuit 12A including key switches _K1 and _K2 , a block detection circuit 12B and its temporary storage circuit 12C, and a note detection circuit. 12D and a step control circuit 12E. The block detection circuit 12B divides the keys of the keyboard (in this embodiment, one row consists of 88 keys) into one unit of block, for example, one octave, and detects and stores the block to which the operated key belongs (into a plurality of blocks). (If the keys are operated simultaneously, the number may span a plurality of blocks), and the block number representing the stored block is stored in the temporary storage circuit 12C as a 3-bit binary code signal. Further, the block detection circuit 12B sends the memory state of the block to the note detection circuit 12D through the key switch being operated on the keyboard. In this embodiment, 88 keys are divided into 8 blocks, 0th block to 7th block, as shown in Table 1.

[Table] On the other hand, the note detection circuit 12D detects the block detection circuit 1 via the key switch of the keyboard.
It detects and stores which note (i.e. note name) the operated key is based on the signal received from 2B (also in this case, if multiple keys belonging to the same block are operated at the same time, multiple notes are stored) ),
The note number representing this memorized note is 4.
The signal is transmitted as a bit binary code signal. Here, when a plurality of blocks are stored in the block detection circuit 12B, the reading of the blocks is executed sequentially with a predetermined priority, and for each block to which this reading operation is performed, the notes of the operation keys belonging to that block are It is stored in the note detection circuit 12D. Reading of the stored notes in the note detection circuit 12D is similarly performed sequentially with a predetermined priority order. The block number code signal BC stored in the temporary storage circuit 12C and the note number code signal NC stored in the note detection circuit 12D are combined and sent out as a 7-bit key code signal KC. The block detection circuit 12B and note detection circuit 12D have the following detailed configuration. The block detection circuit 12B has eight detection circuit bodies BL0 to BL7 of the 0th to 7th blocks corresponding to the 0th to 7th octaves, and the signal input/output terminals _L0 to _L7 are connected to the corresponding blocks ( It is commonly connected to each fixed contact of a pair of key switches K ₁ and K ₂ (Fig. 3) belonging to the octave). The block detection circuit bodies BL0 to BL7 have the same configuration except for the configuration of the readout circuit, and each includes a storage circuit 111, a priority gate circuit 112, a readout circuit 113,
A signal input/output circuit 114 is provided. Now, for example, to describe the detection circuit main body BL0 of the 0th block having a signal input/output terminal _L0 , when a logic "1" signal arrives at the signal input/output terminal _L0 , the memory circuit 111 receives the logic "1" signal from the step control circuit 12E. The "1" state signal IST ₁ is received by the delay flip-flop circuit 117 through an input AND gate 115 which serves as an open control signal, and further through an OR gate 116. The flip-flop circuit 117 reads this "1" signal using the read clock φ _C and then reads it using the read clock φ _D that arrives. However, the "1" signal read out in this way passes through the feedback AND gate 118 and further passes through the OR gate 11.
The data is fed back to the input terminal through 6 and read out at the next clocks φ _C and φ _D. Thus, the flip-flop circuit 117 stores and updates the data each time φ _C and φ _D arrive. This memory is reset by reading the "0" output of the feedback AND gate 118 when it is closed by the clocks φ _C and φ _D. In this way, the block detection circuit body BL
A "1" signal arrives at the memory circuit 111 for 0 to BL7. This is given to the OR gate 119 and sent to the step control circuit 12E as an any block signal AB (indicating that a key belonging to any block is operated). given to. Flip-flop circuit 1 of memory circuit 111
The output of 17 is given to AND gate 120 of priority gate circuit 112. The AND gate 120 is supplied with the read condition signal RCS coming from the block detection circuit body (in this case BL1) which is in charge of one octave high range as an open control signal via the inverter 121.The read condition signal RCS coming from the previous stage is sent as the read condition signal RCS to the subsequent stage together with the output of the flip-flop circuit 117 via the OR circuit 122. In the present explanation, since the 0th block BL0 is the last stage, the read condition signal RCS is sent to the outside. However, the readout condition signal RCS from the previous stage to the block detection circuit body BL7 for the highest range octave is the line 123 connected to the "0" level (in this case, the ground level).
The readout condition signal RCS from the block detection circuit body BL0 of the lowest range octave to the subsequent stage is sent to the step control circuit 12E as a memory block signal MB (indicating that there is memory in one of the blocks). Sent out. In this way, the priority gate circuit 112 is configured such that when there is memory in a block of an octave in a higher range, it can preferentially read out the memory of that block from the memory circuit 111, and if any block detecting circuit main body The memory block signal MB continues to be sent as long as there is memory in the memory. Memory circuit 1 passing through priority gate circuit 112
The storage output of No. 11 is applied to the AND gate 124 of the readout circuit 113. and gate 12
4 is given the "2" state signal _2ST1 coming from the step control circuit 12E as an open control signal, and the priority gate circuit 112
When receiving memory output from
Output line 1 at the timing of state signal 2ST ₁
Give to 25. However, each block detection circuit body BL0~
The output line 125 of BL7 is connected to the input terminals of three code conversion OR gates 126 in a predetermined combination, so that when there is memory in each block detection circuit body BL0 to BL7, the memory block number is converted into a 3-bit binary code. The code signal BC ₁ is sent to the temporary storage circuit 12c at the timing of the "2" state signal 2ST ₁ . The temporary storage circuit 12C is the block detection circuit 1.
Block number code signal coming from 2B
Memory circuit BM that receives each bit of BC ₁ in parallel
1 to BM3, each bit of the block number code signal _BC1 is input to the OR gate 1.
30, a feedback AND gate 132 for dynamically maintaining its memory, and an output AND gate 133. The feedback AND gate 132 receives the "1" and "3" state signals 1, 3ST ₁ coming from the step control circuit 12E during the "1" and "3" states, and controls the period of the "1" and "3" states. Delay flip-flop circuit 131
The storage is canceled in order to store the block number code signal _BC1 sent by the block detection circuit 12B in the "2" state in the delay flip-flop circuit 131 anew. Further, as will be described later, the output AND gate 133 receives a memory note signal MN that arrives from the note detection circuit 12D when a note is stored therein, and thus receives a memory note signal MN when a note number code signal NC is sent from the note detection circuit 12D. At the same time, the temporarily stored block number code signal BC is sent out in parallel as the key code signal KC. The signal input/output circuit 114 of the block detection circuit 12B takes information about the operated keys from the key switch circuit 12A into the block detection circuit 12B, and provides information to the note detection circuit 12D based on this information. A charging/discharging capacitor CB1 connected to the signal input/output terminals L0 to L7 of the detection circuit body BL0 to BL7, and a charging transistor 136 connected between the input/output terminals L0 to L7 and a power supply 135 at logic "1" level. , a discharging transistor 137 connected between input/output terminals L0 to L7 and ground (its logic level is "0"). As described above, the discharge transistor 137 is connected to "2" of the step control circuit 12E.
Readout circuit 1 opened by state signal 2 ST ₁
13 AND gate 124 to memory circuit 11
When the memory of 1 is read out, it is received through the OR gate 138 and turned on, thereby discharging the capacitor CB1 and connecting the terminals L0 to L7.
Reset the level to "0". Similarly, a "0" state signal is sent from the step control circuit 12E via the OR gate 138.
When it receives OST ₁ , it turns on and discharges capacitor CB1. On the other hand, the charging transistor 136
is further “2” through the inverter 139.
Receives the output of the AND circuit 120 of the priority gate circuit 112 through the AND gate 140 which receives the state signal _2ST1 as an open control signal;
As a result, when the memory circuit 111 is not in the memory state, it turns on and sets the capacitor CB1 to logic "1".
charge to the level, thus input/output terminal L0~
Maintain the level of L7 at "1". Note that, in practice, the wiring capacitance of the cords connected to the input/output terminals L0 to L7 can be used as the charging/discharging capacitor CB1. Signal input/output circuit 114 having such a configuration
As will be described later, signals are exchanged with the signal input/output circuit 149 of the note detection circuit 12D via the key switch circuit 12A in accordance with the state signal of the step control circuit 12E. On the other hand, the note detection circuit 12D has the following detailed configuration. The note detection circuit 12D has 12 note detection circuit bodies NT1 to NT12 corresponding to notes (C to C#) belonging to one octave, and a pair of input/output terminals TC ₁ # and TC ₂ # to TC ₁ and TC ₂ has a pair of key switches for each key with a corresponding note.
At the movable contacts of K ₁ and K ₂ , diodes d ₁ and
Connected through _d2 . The note detection circuit bodies NT1 to NT12 have the same configuration except that the configuration of the memory circuit 148 portion is different, and the first memory circuit ₁₄ corresponding to the first key switch K1 respectively
5, a second memory circuit 146 corresponding to the second key switch _K2 , and a priority gate circuit 14.
7, readout circuit 148, and signal input/output circuit 1
49. For example, note detection circuit body NT of note "C#" which has input/output terminals TC ₁ # and TC ₂ #
1, the first memory circuit 145
When a "0" state occurs at the input/output terminal _TC1 # (this state occurs when the key switch _K1 is closed), this is inverted to a "1" signal by the inverter 150, and then the step control circuit 12E The “2” state signal 2ST ₂ coming from
2 through the delay flip-flop circuit 153
Receive at. This flip-flop circuit 15
3 is the memory circuit 1 of the block detection circuit 12B.
In the same manner as described above for No. 11, the received "1" signal is read by the reading clock φ _C , then read by the reading clock φ _D , and then passed through the feedback AND gate 154 and the OR gate 152 to its input terminal. and feeds it back to the next clock φ _C , φ _D
The angle is read in and read out, thus dynamically memorized. This storage state means that the read condition signal is “1”.
RDS is maintained as long as it is applied to the feedback AND gate 154, and this read condition signal
When RDS no longer arrives (that is, when it is "0"), the "0" output of gate 154 is read by the clocks φ _C and φ _D and is reset by reading. On the other hand, when the input/output terminal TC ₂ # is in the "0" state (that is, when the key switch K ₂ is closed), the second memory circuit 146
It has the same configuration as the first memory circuit 145 except that it performs a memory operation. Note that in this embodiment, the first memory circuit 1
An OR gate 165 is inserted between the 45 inverter 150 and the input AND gate 151, and the output of the inverter 160 of the second storage circuit 146 is input to the flip-flop circuit 153 of the first storage circuit 145 through this OR gate 165. Thus, if for some reason the data is not stored in the first storage circuit 145 when the first key switch _K1 operates, the signal from the second key switch _K2 is used to back up this malfunction. There is. However, in the first storage circuit 145 of the circuit bodies NT1 to NT12, the input terminal of the flip-flop circuit 153 is connected to the OR gate 166, thereby creating a delay flip-flop circuit that dynamically stores a "1" signal through the feedback gate 154. If there is even one 153, an any note signal AN (indicating that a note is stored in any of the circuit bodies NT1 to NT12) is sent out. On the other hand, the outputs of flip-flop circuits 153 and 163 of memory circuits 145 and 146 are applied to AND gates 170 and 171 of priority gate circuit 147, respectively. The AND gates 170 and 171 are supplied with a read condition signal RDS as an open control signal, which comes from the note detection circuit main bodies NT12 to NT2 of a note name one note higher according to the note name arrangement of one octave, via an inverter 172. . The read condition signal RDS that has arrived from the previous stage is used as an open control signal for the feedback AND gates 154 and 164 of the first and second storage circuits 145 and 146 as described above, and is also used as an open control signal for the feedback AND gates 154 and 164 of the first and second storage circuits 145 and 146. Together with the output of the flip-flop circuit 153, it is sent out via the OR circuit 173 as a read condition signal RDS to the subsequent stage. However, the note detection circuit for the highest note name C
Read condition signal from previous stage for NT12
Using the input from the line 174 connected to the "0" level (ground level in this case) as the RDS, the note detection circuit body NT12 with the highest pitch name C is configured to read the stored data with the highest priority. There is. Also, the note detection circuit body for the lowest note name C#
The read condition signal RDS from NT1 to the subsequent stage is used as the memory note signal MN in the temporary storage circuit 12C.
is applied to the output gate 133 of the note detection circuit 12D.
When there is data to be read out in any of the blocks 12 to 12, the block number data stored in the temporary storage circuit 12C can be sent out. AND gate 17 of priority gate circuit 147
The storage outputs through 0 and 171, respectively, are sent to output lines 175 and 176. One output line 175 of the note storage circuit body NT1 to NT12 is connected to four code conversion OR gates 1.
77 in a predetermined combination, so that when the memory of the circuit body NT1 to NT12 is read out, the memory note number is 4.
Note code signal of bit binary code signal
Note number output terminal TN1 to TN4 as NC
is output to. In contrast, the memory circuit itself
The other output line 176 of NT1-NT12 is connected to the input of an OR gate 178, thereby outputting a second key switch operating signal _KA2 representing the closing of the key switch _K2 and the timing of its delay from key switch _K1 . Output to TKA2. The signal input/output circuit 149 takes in information sent from the signal input/output circuit 114 of the block detection circuit 12B via the key switch circuit 12A, and connects the signal input/output terminals TC ₁ # and
A first charging capacitor CN1 and CN2 connected to TC ₂ #~TC ₁ and TC ₂ , respectively, and a first charging/discharging capacitor CN1 and CN2 connected between the first terminal TC ₁ #~ _{TC 1} and a logic "1" level power supply 179 and a second charging transistor 182 connected between the second terminals TC ₂ # to TC ₂ and the power supply 181 at logic “1” level. In this example capacitors CN1 and CN
2 utilizes the wiring capacitance between the note detection circuit 12D and the key switch circuit 12A, similarly to the capacitor CB1. These transistors 180 and 182 are turned on by the "1" and "3" state signals 1 and 3ST1 sent from the step control circuit 12E, and charge the capacitors CN1 and _CN2 to the logic "1" level. The above is an example of the structure of the block detection circuit 12B and the note detection circuit 12D, and these operate as follows in synchronization with the state signal of the step control circuit 12E via the key switch circuit 12A. For example, assume that keys for scale notes C ₁ , C ₂ , and E ₂ are being operated simultaneously. Therefore, the key of scale note C ₁ belongs to the 0th block, and the keys of scale note C ₂ and E ₂ belong to the 1st block. The "0" state is a standby state, and the "0" state signal _OST1 turns on the discharging transistor 137 of the signal input/output circuit 114 for all detection circuit bodies BL0 to BL7 of the block detection circuit 12B, and connects the capacitor through this.
Discharge CB1. Therefore, input/output terminal L0
The levels of ~L7 are all "0" levels. At this time, since the key switch of scale note _C1 is closed, the terminal L0 of the block detection circuit 12B of the 0th block is connected to the note detection circuit 12D through the key switches K1 and K2.
"C" Note detection circuit main body NT12 terminal
Similarly, the terminal _L1 of the block detection circuit BL1 of the first block is connected to the _" C" note detection circuit main body NT12.
TC ₁ , TC ₂ and “E” note detection circuit body NT
It is connected to terminals TE ₁ and TE ₂ of 4. Therefore, the capacitors CN1 and CN2 connected to the terminals TC ₁ and TC ₂ and TE ₁ and TE ₂ are also discharged by the transistor 137 through the diodes d1 and d2 and the key switches K1 and K2, and are at the "0" level. When the state changes from this state to the "1" state, the step control circuit 12E sends the "1" state signal 1ST ₁ , "1", and "3".
State signals 1 and 3 ST ₁ are sent out. These “1” and “3” state signals 1 and 3 ST ₁
are "C#" to "C" of the note detection circuit 12D
The signal is applied to the note detection circuit main bodies NT1 to NT12, and their transistors 180 and 182 are turned on. Therefore through this capacitor
CN1 and CN2 are charged simultaneously. At the same time, a capacitor CB1 is connected to the terminals L0 and L1 of the block detection circuit 12B through the diodes _d1 and _d2 and through the key switches K1 and K2 of the operated keys " _C1 ", " _C2 " and " _E2 ". is charged. However, key switches K1 and K2 corresponding to keys that are not operated are not closed, so the capacitor
CB1 is not charged. Therefore, a logic ``1'' is applied to the input/output terminals L0 and L1 of the block to which the operated key belongs (that is, the 0th block to which the "C ₁ " key belongs, and the 1st block to which the "C ₂ " and "E ₂ " keys belong).
Input is given. Therefore, from the block detection circuit 12B to the step control circuit 12E
An any block signal AB is sent out. On the other hand, the "1" state signal _1ST1 is detected by the block detection circuit BL0~ of the block detection circuit 12B.
The input gates 115 of the memory circuits 111 are opened all at once. Therefore, the memory circuits 111 of the 0th and 1st block detection circuit bodies BL0 and BL1 to which the "1" input is applied enter the memory state, and the block numbers to which the operated keys belong (in this case, the 0th and 1st blocks) are stored. 1 block) is block detection circuit 1
Stored in 2B. When the state changes from this state to the "2" state, a "2" state signal _2ST1 is sent out from the step control circuit 12E. This "2" state signal _2ST1 is the block detection circuit main body BL of the block detection circuit 12B.
0 to BL7, and its readout circuit 113
are given as an open control signal to the output gates 124 of all at once. However, at this time, the detection circuit bodies BL0 and BL1 of the 0th and 1st blocks
Since only the first block is in the memorized state, the read condition signal RCS is applied only to the AND gate 120 of the priority gate circuit 112 of the detection circuit body BL1 of the first block, which has a higher priority. Therefore, the stored contents from the storage circuit 111 of the detection circuit main body BL1 of the first block pass through the priority gate circuit 112 and the readout circuit 113, and the binary code signal "100" becomes the block number code signal.
Sent as BC ₁ . This 3-bit block number code signal _BC1 is sent to the temporary memory circuit 12.
C, and its respective bit storage circuit BM1
- Stored through the input OR gate 130 of BM3. Note that the data stored in the detection circuit main body BL1 of the first block of the block detection circuit 12B is read out, and thereby the readout circuit 113
When the output of the output gate 124 becomes "1", this closes the feedback gate 118 via the inverter 128. Therefore, the flip-flop circuit 117 receives the next period's clock φ.
"0" is read and read by _C and _φD . Thus, the memory circuit BL1 of the first block is reset. At this time, the read condition signal to the next stage is
By setting RCS to "0", the conditions for reading the next lowest priority block (in this case, the 0th block) are set. On the other hand, the first block number storage output of logic "1" read from the readout circuit 113 via the priority gate circuit 112 is applied to the discharging transistor 137 of the block detection circuit body BL1 to turn it on. Therefore, capacitor CB1 of the first block is transistor 1
37. Not only this, the circuit body (in this case, " C” and “E”
The capacitors CN1 and CN2 of the note detection circuit bodies NT12 and NT4 are also discharged through the transistor 137 of the block detection circuit body BL1. "C" and "E" note detection circuit body corresponding to the note name of the key operated in this way
Logic "0" inputs are provided to NT12 and NT4. On the other hand, a second "2" state signal _2ST2 is given from the step control circuit 12E to each note detection circuit body NT1 to NT12, and the input gates 151 and 161 of the first and second storage circuits 145 and 146 are opened all at once. By this, "C" is given "0" input.
and "E" note detection circuit body NT12 and
The storage circuits 145 and 146 of the NT4 enter the storage state, and the notes of the keys belonging to the first block (in this case, "C" and "E") among the operated keys are stored in the note detection circuit 12D. However, at this time, among the "C" and "E" note detection circuit bodies NT12 and NT4, the "C" detection circuit body NT1, which has a higher priority,
By applying the read condition signal RDS of logic "0" to the second priority gate circuit 147, the first and second memory circuits 145 and 14
6 is read out, thus the readout circuit 148
A binary code signal “0111” representing the note number is sent to the first memory circuit 1 through the gate 177 of the
45 to the output terminals TN1 to TN4 as a note code signal NC, and also to the readout circuit 1.
The second key switch operation signal "1" indicating that the second key switch K2 has been operated is transmitted to the second memory circuit 14 through the gate 178 of 48.
6 to the output terminal TKA ₂ . In addition, in practice, key switches K1 and K2 are
As described above with reference to FIG. 3, after the first key switch K1 is operated, the second key switch K2 is operated, and the difference in operating time corresponds to the operating speed of the key. However, as will be described later, the periods of the clocks φ _C and φ _D are selected so that this difference in operating time is sufficiently large compared to the periods of the clocks φ _C and φ _D. Therefore, the storage and readout operations of the first and second storage circuits 145 and 146 of the note detection circuit bodies NT1 to NT12 are not actually performed at the same time, but are performed with a time difference. On the other hand, since "C" and "E" note detection circuit bodies NT12 and NT4 are stored, the note detection circuit body NT of the lowest rank
The output gate 133 of the temporary storage circuit 12C is activated by the memory note signal MN sent from 1
is opened, and the block number code signal BC1 "100" stored in it is sent to the output terminal TB1.
~ Sent to TB3. Therefore, output terminals TN1 to TN4 and TB1 to
Among the operated keys, TB3 contains the key that is layered in the highest octave (in this case, the first octave) and has the highest note name (in this case, the "C ₂ " key). A 7-bit key code signal "0111100" containing a number is sent out as a key code signal KC. In this way, the note detection circuit body NT1
~ When one or more of the memory circuits 145 of the NT12 performs a memory operation, an any note signal AN is sent to the step control circuit 12E, and on this condition, the state enters the "3" state following the "2" state, and the step The "1" and "3" state signals 1, 3ST ₁ are sent out again from the control circuit 12E. This "1"/"3" state signal 1/3ST ₁
turns on the charging transistors 180 and 182 of the note detection circuit body NT1 to NT12 again, and thereby the capacitors CN1 and CN2
Recharge the battery. On the other hand, "1" and "3" state signals 1 and 3ST ₁
is the feedback gate 132 of the temporary storage circuit 12C.
As a result, when the first clocks φ _C and φ _D arrive, the output of the flip-flop circuit 131 is fed back to the input terminal, and therefore the temporary storage circuit 12C stores the same block number code signal BC ₁ . Try again. On the other hand, the “C” note detection circuit body
In NT12, the first clock φ _C ,
φ _D resets the memory in memory circuit 145 (because feedback gate 154 is closed due to the logic ``0'' signal from line 174), while the logic ``1'' signal in ``E'' note detection circuit NT4 is reset. is memorized again (the feedback gate 154 is the “C” note detection circuit body)
(This is because it is opened by the read condition signal RDS of "1" from NT12). Therefore, in the first period of these clocks φ <sub>C</sub> and φ <sub>D</sub> , the “C” note detection circuit body NT
12's memory is reset, and this causes "E"
When the read condition signal RDS to the priority gate circuit 147 of the note detection circuit main body NT4 becomes "0", the "E" note detection circuit main body NT
4's "1" output is read out by the readout circuit 148 through the output gate 170, and thus the "E" note code "0010" is output from the readout circuit 148.
is read out. In this way, output terminals NT1 to NT4 and
A key code signal "0010100" representing that the key belonging to the first block and having the note "E", that is, the "E <sub>2</sub> " key, has been operated is sent to TB1 to TB3. When all the notes stored in the note detection circuit 12D are thus read out, the memory of the "E" note detection circuit NT4 is reset by the second cycle of the clocks φ <sub>C</sub> and φ <sub>D</sub> , and the any note signal AN is reset. It becomes "0". At this time, the step control circuit 12E receives the memory block signal from the block detection circuit 12B.
Next, return to the "2" state again, subject to the presence of MB. That is, the "2" state signal <sub>2ST1</sub> is again applied from the step control circuit 12E to the readout circuits 113 of the circuit bodies BL0 to BL7 of the block detection circuit 12B. At this time, the 0th block number is coded into the temporary storage circuit 12C in the same manner as in the case of the first block described above, except that the memory of the 0th block that remains unread is read out through the readout circuit 113. At the same time, the discharge transistor 137 is turned on and the capacitor CB1 and the capacitors CN 1 and CN2 of the "C <sub>"</sub> note detection circuit body NT12 are read out as the signal "000" via the key switches K1 and K2 of the "C <sub>1</sub> " key. Discharge this "C" note detection circuit body NT1
The second storage circuits 145 and 146 are set to the storage state. At this time, the state shifts to "3" again, and the stored data in the memory circuits 145 and 146 is immediately read out and sent out from the readout circuit 148 as a "C" note code signal "0111", thus output terminals TN1 to TN4 and TB1 to TB3. A key code signal "0111000" representing that the key of the "C" note code belonging to the 0th block, that is, the key of the "C <sub>1</sub> " note, has been operated is transmitted. By the way, when this operation is finished, "C"
Memory circuit 14 of note detection circuit main body NT12
5, feedback gate 154 is closed (read condition signal RDS from line 174
is "0"), the note detection circuit 12D does not generate the any note signal AN, and the block detection circuit 12B also does not generate the memory block signal MB, so the memory is in the "0" state, that is, the standby state. Return to state. Start of memory operation of block detection circuit bodies BL0 to BL7, and block circuit bodies BL0 to BL7
From BL7 to note detection circuit body NT1 to NT1
The operation of each part of the key coder 12, such as outputting signals to the key coder 2, is controlled by the step control circuit 12E.
It is controlled by a step control signal generated in synchronization with the master clock. The step control circuit 12E is activated by the activation pulse TC generated by the activation pulse generation circuit 12F, and thereafter generates the step control signals OST <sub>1</sub> , 1ST <sub>1</sub> , 2ST <sub>1</sub> in synchronization with the data transfer clocks φ <sub>C</sub> and φ <sub>D.</sub> ，
Generates 2ST <sub>2</sub> , 1/3ST <sub>1</sub> . In this embodiment, starting pulse generation circuit 1
2F has a low frequency clock oscillator 181 having a rectangular wave generation circuit configuration, for example, and a delay flip-flop circuit 182 connected to its output terminal, and outputs the output of the oscillator 181 to a two-input AND circuit 183 as one of the condition inputs. give,
In addition, the output of the flip-flop circuit 182 is inverted by the inverter 184 and applied to the AND circuit 183 as the other conditional input, so that when the output of the oscillator 181 becomes logic "1" level in the AND circuit 183, the flip-flop circuit is then inverted. 182 sends out a starting pulse TC which becomes logic "1" from when the logic "1" signal is read by the clock φ <sub>C</sub> until when it is read by the clock φ <sub>D.</sub> Here, the oscillation frequency of the low frequency clock oscillator 181 is determined mainly by taking into consideration the conditions for detecting keyboard operations, such as avoiding the influence of chattering. For example, the frequency is selected to be approximately 200 μs to 1 ms. be done. On the other hand, the data transfer clocks φ <sub>C</sub> , φ <sub>D</sub>
has a cycle that is short enough to transfer the data of each note in one round corresponding to the maximum number of simultaneous notes, and the channel processor 13
A periodic signal generating circuit 13A as shown in FIG. 7C arranged in FIG. The periodic signal generation circuit 13A includes a four-stage full adder 185 and four delay flip-flop circuits 186 connected to each stage. Each stage of the flip-flop circuit 186 is supplied with a master clock φ <sub>1</sub> (φ <sub>1</sub> in FIG. 5) having a period τ of 1 μs, which is generated by a separate master clock oscillator (not shown), as a read <sub>clock</sub> . The master clock <sub>φ2</sub> is delayed by 1/2 period.
(φ <sub>2</sub> in FIG. 5) is given as a read clock. Therefore, the full adder 185 operates in response to the operation of the flip-flop circuit 186 every period τ of the master clocks φ <sub>1</sub> and φ <sub>2</sub> , and thus the output terminal of each stage of the flip-flop circuit 186 receives the period τ of the master clocks φ <sub>1</sub> and φ <sub>2</sub> . A binary coded hexadecimal code output (having ``1'', ``2'', ``4'', and ``8'' bits) is sent out in steps of . By appropriately combining the binary coded hexadecimal code outputs generated in this way, a timing pulse with a period of 16τ can be formed with a pulse width of one period τ of the clock pulse _φ1 , and In the case of the embodiment, the synchronizing signal generating circuit _13A is shown in FIG _.
As shown in 9Y ₁₆ and 16Y ₁₆ , the first, second,
9th and 16th timing pulse 1Y ₁₆ ,
2Y ₁₆ , 9Y ₁₆ , 16Y ₁₆ and circuit 18
8, 189, 190, and 191, of which the 16th and second timing pulses 16Y ₁₆ and 2Y ₁₆ are used as data transmission clocks φ _C and φ _D of the key coder 12. The reason why a timing signal with a period of 16τ is generated here is based on the fact that the number of tones to be generated simultaneously is selected to be 16 tones. In other words, since the electronic musical instrument of this embodiment has a single-level keyboard structure with 88 keys like a piano, there is a possibility that keys for 10 fingers of both hands will be operated simultaneously, and how many keys have already been operated? Taking into consideration the possibility that the sound may have a decay waveform, a total of 16 sounds can be generated simultaneously. However, the master clocks φ ₁ and φ ₂ are divided into 16 cycles, each cycle within the 16 cycles is used as a time slot, and the data of each sound that should be generated simultaneously is assigned, and the corresponding data is generated within the assigned time slots. (hereinafter also referred to as the relevant data). Therefore, below, in FIG. 5, the first, second......16th cycle sections _T1 , _T2 ...... _T16 of the master clock _φ1 are the first, second......
...It will be called the 16th Channel. Based on this idea, the channel processor 13 processes data for each tone in synchronization with the master clocks φ ₁ and φ ₂ . Therefore, in cooperation with this, a step control circuit 12E is generated in the periodic signal generating circuit 13A in synchronization with the manta clocks φ ₁ and φ ₂ in order to cause the key coder 12 to perform an operation to determine which key has been operated. The timing signals φ _C and φ _D are used. The synchronization signal 16 generated in this way
Y ₁₆ and 2Y ₁₆ are used as the read and readout clocks φ _C and φ _D for each delay flip-flop circuit in key coder 12, thus all delay flip-flop circuits are continuously clocked once every 16 cycles of master clocks φ ₁ and φ ₂ . Reading and reading operations will be repeated. The step control circuit 12E includes a step counter 203 consisting of two delay flip-flop circuits 201 and 202 which receive a read clock φ _C and a read clock φ _D , and control the stepping operation of the step counter 203 and output each state signal based on the stepping state. Gate circuit 2 forming
04. The gate circuit 204 is the starting pulse generation circuit 1
It is activated by the activation pulse TC arriving from the 2F, and receives the any block signal AB and memory block signal MB generated by the block detection circuit 12B, and the any note signal AN generated by the note detection circuit 12D. ,
Gives rise to four states. In other words, the "0" state (standby state), the "1" state (detection state of the block to which the operated key belongs), and the "2" state (detection of the note of the key belonging to the detected block among the operated keys). A total of four states are generated: a "3" state (an operating state in which a key code is sent out based on the detection result of a block or a note); These states are shown in Table 2,
The outputs Q of flip-flop circuits 201 and 202 are connected to inverters 205 and 206.
It is established as follows by the inverted output obtained through .

【table】 Step control circuit 12E is “0”
state (i.e., flip-flop in standby state)
The Q outputs of the top circuits 201 and 202 are "0"
and “0”), the state signal input
“0” from AND gate 215 of circuit 214
state signal OST₁is being sent. this
When the start pulse TC arrives when the state is “0”
Then, this is the state control of the gate circuit 204.
given to the AND gate 207 of the control circuit 206.
It can be done. At this time, the flip-flop circuit 201
and 202 outputs “1” and “1” are other
Since it is given as a condition,
The input conditions for 207 are met and a “1” output is generated.
is applied to the second flip-flop circuit 202.
is given via the input OR gate 212 of
Ru. Therefore, the read and read clock φ_Cand φ_D
flip-flop circuits 201 and 2 by
“0” and “1” are stored in 02, and “1”
Becomes a state state. At this time, the circuit 201
output and the Q output of circuit 201 are state signals.
applied to the AND gate 217 of the signal output circuit 214.
From this gate 214,
"1" state signal 1ST₁is sent. Therefore, as mentioned above, this “1” state belief
No. 1ST₁As a result, the block detection circuit 12B
It operates and the key switch circuit 12A is operated.
Detects and stores the block to which the key switch belongs.
do. However, if the key of one of the blocks is
If operated, any block signal AB will be activated.
sent back to step control circuit 12E
Also, either block detection circuit body
If BL0 to BL7 perform memory operation, the memory
Lock signal MB is the step control circuit
Sent back to 12E. Any block signal AB is the state control circuit.
It is sent back to Route 12E. Any block signal AB is the state control circuit.
AND gate 211 (circuit 201
and the Q output of circuit 202 are already given.
given) and this gate 21
1 to the input OR gate 213 of the circuit 201
“1” output is input. On the other hand, Ste.
to the AND gate 207 of the gate control circuit 206.
has not already been given the startup pulse TC
Therefore, the input OR gate 212 of the circuit 202
``0'' output is input. Therefore, the circuits 201 and 202 have the following period.
reading and reading clock φ_Cand φ_DYo
"1" and "0" are memorized and "2" step
It will be in the default state. Therefore, the amplifier of the state signal output circuit 214
first “2” state signal from gate 216;
No. 2ST₁is sent, and at this time the block
Memory block signal MB from detection circuit 12B
and games on the condition that it has arrived.
second “2” state signal 2 from port 218
ST₂is sent. This first “2” state signal 2ST₁Habu
applied to the readout circuit 113 of the lock detection circuit 12B.
Most of the blocks acquired and memorized
Code the block number with the highest priority.
While reading to the temporary storage circuit 12C, the signal input
Through the output circuit 114, the key switch is
The circuit 12A is connected to the note detection circuit 12D.
Sends a signal for the note of the key being created. one
At this time, the second "2" state signal 2ST₂
are the first and second memories of the note detection circuit 12D.
provided to circuits 145 and 146 and sent to
Memorize the notes that came. However, in the "2" state, the note
The note is stored in the detection circuit 12D.
and any note signal AN is step control.
It is sent back to the roll circuit 12E, and this
to the AND gate 208 of the gate control circuit 206.
Given. On the other hand, ANDGATE 210 is a memo
Reblock signal MB and Q output of circuit 201
is given, so generate a “1” signal.
There is. Therefore, the circuits 201 and 202 have the following
Periodic clock φ_C,φ_Dinput or game by
"1" and "1" through ports 212 and 213
The “1” signal is memorized and thus the “3” step
becomes the default. However, at this time, the note detection circuit 12D
, prioritize the notes you have memorized.
The circuit 148 reads out the highest note number.
coded through the output terminals TN1 to TN4.
Send. At this time, a block is connected to the output terminal of the temporary storage circuit 12C.
The lock number is read out and this is the output terminal TB.
1 to TB3. Therefore, terminal TN1~
Key code signal KC is on TN4, TB1 to TB3.
It will be sent out. On the other hand, in the "3" state, the step control
Q output of circuit 202 of control circuit 12E
is "1", "3" state signal 1/3ST₁year
This is generated again by the note detection circuit 12.
D is applied to the signal input/output circuit 149, and thus
Detect the note from the block detection circuit 12B.
Reset the note detection signal transmission status to circuit 12D.
Set. Along with this, "1" and "3" stages
Signal 1/3ST₁is applied to the temporary memory circuit 12C.
and refresh its memory. Here, the note detection circuit 12D stores
If there is only one note, the first and
The memory of the second memory circuits 145 and 146 is
Since it is reset in the "3" state, the error
The knee note signal AN no longer arrives. obey
The stage of the step control circuit 12E
In the gate control circuit 206, the gates 208,2
The output of 09 becomes "0". Here, one block is connected to the block detection circuit 12B.
When all I remembered was the lock,
Memory block signal in “3” state
Since MB becomes "0", state control circuit 2
The AND gate 210 of 06 has a “1” output.
Therefore, in circuits 201 and 202,
A "0" signal is input. By the way, the circuits 201 and 202 are in the next cycle.
reading and reading clock φ_Cand φ_DYotsu
The state becomes “0” and “0” memory state, and the
to the “0” state, that is, to the standby state.
I'll have to go back. In contrast, the block detection circuit 12B
If the above blocks are stored, 1
When in “3” state for one block
However, the memory block signal MB continues to arrive.
Since the gate of the state control circuit 206
A “1” output is obtained at 210, which is the circuit 2
01. Therefore, circuits 201 and 202 are
Read clock φ_Cand read clock φ_Din
“1” and “0” are stored and the status is
from the gate 216 of the gate signal output circuit 214.
Degree “2” state signal 2ST₁Send out. mosquito
When the state becomes "2", then
Perform the next read and read clock in the same manner as described above.
Tsukφ_Cand φ_D“3” state state by
become. This type of repetitive operation is caused by the block detection circuit.
Until the block stored in path 12B disappears.
, but the result is a memorized blot.
When the block runs out, the block will appear in the “3” state.
Memory block signal from block detection circuit 12B
MB no longer arrives, and the next period's clock
Tsukφ_C,φ_Dto return to the "0" state. In the above, the detected blocks are
I mentioned the case of numbers, but the number of blocks included in one block is
If there are multiple detected notes, the note detection
to all detected notes in output circuit 12D.
"3" state until the reading of the
maintain the condition. That is, in the "3" state,
Any note signal from note detection circuit 12D
As the issue AN continues to arrive,
The gate 209 of the state control circuit 206 is
Then "1" output is obtained, and therefore "3" output is obtained.
Clock φ whose state is next cycle_C,φ_Dof
This is because it will be maintained even when it arrives. As described above, step control circuit 1
2E performs a stepping operation as follows. (a) When one key is operated. "0" → "1" → "2" → "3" →
A cycle of "0" state is performed once. (b) Multiple keys for one block key.
When the root key is operated. "0" → "1" → "2" → "3" →
"3"......"3" → "0" state
Until all notes have been read out
Maintain the "3" state. (c) One block for each block.
when a key is operated. "0" → "1" → "2" → "3" →
"2" → "3" ...... "2" → "3" →
Like the "0" state, all blots
"2" until the reading of the
Repeat the step from "3" to "2" state. (d) For multiple blocks, each
when a note is memorized. "0" → "1" → "2" → ["3" →
"3" ...... "3"] → "2" → ["3" →
「３」……「３」〕→「２」……「２」→
[“3” → “3”……”3”] → “0”
Like Tate, [“3” → “3”……
“3” state maintenance operation consisting of “3”]
Repetition and “2” → “3” → “2” stage
This is combined with the repetition of the stepping motion. The step control circuit 12E is as follows.
In addition to configuration, key-off detection timing signal
It has an output circuit 220. Key-off detection is performed here.
The output timing signal
In relation to the generation operation of the key code signal KC,
Used as a guide to whether or not a key has been released.
Therefore, it is supplied to the channel processor 13.
Ru. Key-off detection timing signal output circuit 22
0 comes from the starting pulse generation circuit 12F
AND gate 221 receiving starting pulse TC
and 222, the flip-flop circuit 2
01 and 202 output and hexadecimal counter structure
Timing counter 12G ends counting
“0” after receiving the output TMO from the output terminal
When startup pulse TC arrives during state
Pulse “1” output from AND gate 222
Generates force and outputs it as signal X
It is sent to TX and also sent via OR circuit 223.
and starts counting to timing counter 12G.
Give as the first pulse TMI. At this time cow
The counter 12G has a clock φ_Cand φ_Dis coming
The addition operation is performed by adding "1" for each
Sometimes the output TMO is set to "0". In other words, the output TMO is
It is "0" until the maximum value is reached. The signal output circuit 220 outputs this "0"
Invert TMO with inverter 224 and
input to gate 221, which causes the activation pulse
Starting pulse TC arrives from pulse generation circuit 12F
When this happens, “1” is output through the or gate 223.
By applying force to counter 12G
Add “1” operation. This counting operation
is the starting pulse to the starting pulse generation circuit 12F.
A starting pulse TC is generated in the TC generation circuit 12F.
is repeated every time, thus the number of low frequency oscillations
When a period of 16 cycles of 181 outputs has elapsed
All bits of counter 12G output become “1”.
After that, the output TMO becomes “1”.
Counting operation via AND gate 221
and start in the next “0” state
It is designed to wait for the arrival of a pulse. In addition, timing counter 12G
226 is a four-stage full adder, and 227 is its
Read and read clock φ connected to each stage_C，
φ_DDelayed flip-flop memory operated by
228 is a 4-stage flip-flop circuit.
All using the output of circuit 227 as the input condition
Output that sends out “1” output TMO when “1”
And gate. Summary of the operation of the key coder 13 configured as described above
If shown as a flowchart, the result shown in Figure 6 is as follows.
It becomes like this. In other words, step 235 is in the "0" state.
In the step that obtains the state, the step controller
“0” state signal 0 from circuit 12E
ST₁The block detection circuit 12B is controlled by
Capacitor CB1 is maintained in a discharged state, and the entire
and is on standby. Next, in step 236, if TC=1?
In other words, starting pulse generation circuit 12F
It is confirmed whether the starting pulse TC is generated from
If it has not occurred, it will still be in the “0” state.
maintain the default state. But what is happening
Once confirmation is obtained, proceed to the next step 237.
nothing. This step 237 is in the "1" state.
In the step of obtaining ``1'' and ``3'' state
No. 1, 3ST₁Note detection circuit 12D by
capacitors CN1 and CN2 are charged, and this
Key switches K1 and K that are currently being operated
2 to the block detection circuit 12B.
Charge sensor CB1. On the other hand, at the same time
The key switch K of the block detection circuit 12B
1. Memory times corresponding to the block to which K2 belongs
Input gate 115 to path 111 is in “1” state.
Start signal 1ST₁opened by the capacitor
The charging state of CB1 is read into the memory circuit 111.
Thus, the currently operated key belongs to
The operating state is stored in the block. This result is sent by any block signal AB.
In step 23, check whether AB=1 or not.
This is done by checking in step 8. The result
result AB = 1 (i.e. in any block
(means there is a key being operated)
If so, proceed to the next step 239;
If not, the “0” state in step 235
Return to standby state. Step 239 obtains the "2" state state.
Step control circuit 1
2E “2” state signal 2ST₁By
Activates the readout circuit 113 of the lock detection circuit 12B.
Let them make it. However, the readout circuit 113
The block with the highest priority
Read something and send the block code of its contents.
No. BC₁Send out. At the same time, read operation
The controller connected to the block detection circuit body
Discharge capacitor CB1. At this time, this
Attach key switches K1 and K2 to capacitor CB1.
Note detection circuit connected through
Capacitors CN1 and CN2 are also connected through this connection loop.
is discharged. On the other hand, the note detection circuit 12D
The first and second memory circuits 145 and 146 are
"2" step from step control circuit 12E
Start signal 2ST₂By capacitor CN1,
Read the discharge state of CN2. Next, in step 240, block detection is performed.
Memory block detection signal MB from circuit 12B
is given to the step control circuit 12E.
(i.e. any block
is memorized), and confirm that the
Note detection circuit 12D in step 241?
The any note detection signal AN is output from the step controller.
What is given to the troll circuit 12E
(i.e. if any note is memorized)
After confirming that, the process moves to the next step 242. child
Here, in step 240, MB is not 1.
There are no blocks to process, so wait.
Return to step 235 for the status. Step 242 obtains the "3" state.
At this time, the note detection circuit 12
Is the memorized note a high priority for D?
are read out sequentially. Along with this, the step control
“1” and “3” state signals of the control circuit 12E
1,3ST₁The note detection circuit 12D is
Charge capacitors CN1 and CN2 and hide
to block the input to the note detection circuit 12D.
do. And at this timing, the note detection time
Memory circuits 145 and 146 of path 12D read
Read from notes with higher priority
The memory contents are converted into a note code through the circuit 148.
and send it out. However, the operating state is determined in step 243.
Check the presence or absence of any note signal AN at
is repeated as long as the step is
243 returns to step 242). this
When AN=1 for , the note
All notes stored in the detection circuit 12D
Now that I have finished retrieving my memory for everything.
Therefore, the process advances to the next step 244. This step 244 checks whether MB=1 or not.
If it is confirmed, it will not be processed yet.
The data of the target block is sent to the block detection circuit 1.
This means that it remains in 2B, so
Return to step 239 and see what remains of this block.
process the data of the deny this
If the result is obtained, step control circuit
12E is “0” state signal 0ST₁send out
After all the operations are completed, the screen
The process returns to the standby state at step 235. The above operation is performed by the starting pulse generation circuit 12F.
Repeatedly every time the starting pulse TC is generated from
be done. However, in relation to the starting pulse TC, the key
The frame detection timing signal X follows the steps described below.
Based on the starting pulse TC,
The above key code signal KC sending operation and
Related information is sent as follows. First, in step 245, a starting pulse is generated.
The starting pulse TC generated in the raw circuit 12F is
Counter 12G counts and overflows.
When the low output TMO is output, go to step 246.
Detect this and proceed to step 247.
nothing. At this time, the step control circuit 12E
is the "1" addition signal for counter 12G
Stop sending TMI. In that state, the step control circuit 12
E is “0” state signal 0ST₁letter to send
This is detected in step 248.
Then, in the next step 249, the activation pulse is
Check the timing when the TC was sent. child
Once confirmation is obtained, proceed to the next step 250.
key from the step control circuit 12E.
-Send off timing signal X. However, when the sending of this signal
Return to step 245 and start pulse TC again
Start counting. Thus, the key-off timing signal
Occurs after sending the code signal KC
Count the starting pulse TC and its count
When the number becomes "15", then the
The sending operation of the key code signal KC is completed.
It will be sent out after waiting. (1-3) Channel processor Channel processor 13 will sound simultaneously.
Data of each sound to channels 1 to 16
Memorize assignments and master these memorized data
Clockφ₁,φ₂Send sequentially in synchronization with
It has the configuration shown in FIGS. 7A to 7C. here
Number of storage channels (16 in this example)
Figure) corresponds to the maximum number of simultaneous polyphony as mentioned above.
of all channels.
Channels with no data (hereinafter referred to as empty channels)
), if there is a key to this empty channel.
-New key code day from code 12
Read and set the data. thus remembered
The key code data will be displayed when the corresponding key on the keyboard is
It will not be reset as long as the key is held down, and it will not be reset as long as the key is pressed.
Even after being locked, a decay is necessary for the sound.
If the amplitude of the decay part reaches the specified value,
It will not be reset unless Key code decode for channel processor 13
The memory of the data is the data of channels 1 to 16.
master clock φ₁,φ₂in series by
dynamically by repeatedly circulating the
to be done. In this way, the dynamic cycle
The data of channels 1 to 16 are in a circular loop.
Monitored at one point, 16 channels
The data of each channel is read out sequentially in each round.
be done. Therefore, the contents of each channel are master
Clockφ₁,φ₂A period with a length of 16 periods of
It will be read out and checked. The channel processor 13 is a key coder.
7-bit key code signal coming from 12
KC, key-off detection timing signal X and
2nd key switch operation signal KA₂Temporary import
Sample and hold circuit 13B for storing and
The input key code signal KC is sent to 16 channels.
Record the key code assigned to one of the files.
Storage circuit 13C and sample hold circuit 13
Key code signal KC and key temporarily stored in B
- Record of each channel of code storage circuit 13C
Based on the comparison results,
Key code comparison control that sends control condition signals
Circuit 13D and data related to key operation touch
Key operation discrimination circuit 13E for obtaining data
and these elements allow data to be captured and recorded.
Control the timing of remembering, comparing, etc.
Timing control circuit 13F to control
and empty channels for all 16 channels.
New key code data arrives when the key code is missing.
If the old key code data is
- Trunque for exchanging code data
and a gate circuit 13G. Sample hold circuit 13B is a key coder
The key code signal KC (no
Each bit N1 to N4 of the code signal NC and
Each bit B1 to B of block code signal BC
3) and key-off detection timing signal
X and second key switch operation detection signal KA2
and gates set up correspondingly to each
Stored in storage element 232 via circuit 231
Ru. In this embodiment, the gate circuit 231
Synchronous signal generation circuit made of effect transistors
13A (Fig. 7C) 1st channel tie
Mining signal 1Y₁₆(Figure 5 1Y₁₆) by one
When opened simultaneously, the input logic “1” or
is the “0” level storage element of the capacitor configuration.
232. Thus, the data stored in storage element 232
The next cycle timing signal 1Y₁₆but
is held in the storage element 232 until the arrival of the
At this time, the same data is sent to key coder 12.
If the memory has arrived from the memory element 232,
The key code that arrives for this is left as is.
If the contents of the code change, the contents change accordingly.
Change the memory state of the memory element of the changed bit
It is made to be. However, each bit of the key code signal KC
The storage contents of the storage element 232 for the
Input data timetable of key code storage circuit 13C
It is applied to the storage circuit 233. Temporary memory circuit 2
33 is the ninth channel of the synchronization signal generation circuit 13A.
Channel timing signal 9Y₁₆(Fig. 5 9Y₁₆)
The read operation is performed by the first
Channel timing signal 1Y₁₆(Figure 5
1Y₁₆) Delayed flippuff with read operation
It is composed of lops. In this way, the temporary storage circuit 233 has
First timing signal 1Y₁₆sump by
Data read into ring hold circuit 13B
After the holding state of the data has stabilized, the timing signal
9Y₁₆Read this stable data by
and timing signal 1 of the next second cycle
Y₁₆Read it with . Therefore, this second cycle
Timing signal 1Y₁₆sampling by
The opposite logic level is stored in the hold circuit 13B.
Even if the
Mining signal 1Y₁₆of one cycle until obtaining
Try not to change the memory state at least for a while.
has been done. However, the temporary memory circuit
The data stored in 233 is a timing signal
1Y₁₆input game as necessary during one cycle of
AND gate 235 and OR gate circuit 234
of the memory circuit main body 237 via the gate 236.
Empty channel among channels 1 to 16
is memorized. The memory circuit main body 237 receives the key code signal KC.
7 16-steps corresponding to each bit of
It consists of stage shift registers RG1 to RG7, and each
At the stage, the first master clock φ₁
reads the contents of the previous stage by
Master clock φ₂The content read by
It is designed to be read out. Therefore, there are 7 layers.
The contents of registers RG1 to RG7 are the master clock.
φ₁,φ₂One stage at a time by
I'm going to go. However, the appearance of the 16th stage
The power is the input gate circuit 234's circulating AND gate.
via gate 238 and or gate 236.
It is fed back to the input end of one stage, and therefore each stage
Dynamic memory without losing the memory of the stage
do. So regarding registers RG1 to RG7
A specific stage at any point in time (i.e.
1st stage to 16th stage)
Displays the 7-bit key code KC for the Yannel.
I will miss it. For example, the first channel
Timing signal 1Y₁₆Regis at the arrival of
The contents of the first stage of RG1 to RG7 are 1
Representing the key code KC for 7 bits of sound
become. Therefore, the memory circuit main body 237 is
Memorize key codes KC for large polyphony and 16 notes.
Ru. 16th stage of shift registers RG1 to RG7
The second output is derived from output terminals WN1 to WN3.
Therefore, it passes the 1st to 16th stages.
to the key code output terminals WN1 to WB3 for each
Read out. Thus, the output terminals WN1 to WB
The memory data read out in 3.
Copy the key code KC of the sound by time division multiplexing.
coded simultaneous key code signal KC and
and then sent out. On the other hand, among registers RG1 to RG7, the notebook
Registers RG1 to RG4 that store the code NC
The output is passed through the OR gate 239 to the first key
Ittsuchi key-on detection signal WK1 output terminal
Sent to WTK1. This orgate again
When a “1” output is obtained on the 239, this is
G signal A1 (chi that passed the 16th stage)
In other words, there is memory data in Yannel.
(indicates that it is not an empty channel)
and use it. The data in the temporary memory circuit 233 is transferred to the memory circuit main page.
Which channel of the body 237 is assigned and memorized?
Whether it should be determined by the AND of the input gate circuit 234
Gate 235 and feedback AND gate 238
is set in the timing control circuit 13F.
Opening/closing control by switch signal S and reset signal
It is executed by controlling the However, Thailand
The timing control circuit 13F is a key coder.
The contents and memory of the key code that arrived from 12
stored in each channel of the circuit body 237
Match based on the contents of the key code KC
Set signal S or reset depending on the presence or absence of
act to send or not send a
make Data from key coder 12 and memory circuit book
Comparison with body 237 memory data is a key code
This is performed in the comparison control circuit 13D. this
Comparison control circuit 13D is key code comparison circuit 2
40 and a matching channel storage circuit 241.
That's what happens. The key code comparison circuit 240
Key code held in hold circuit 13B
Each bit N1 to B3 of signal KC is input to one side.
Signals and corresponding registers RG1 to RG
Exclusive OR with the output of 7 as the other input signal
circuit 242, and the OR circuits 242.
The output is given to the NOR gate 243 for coincidence detection output.
I can do it. Here, the exclusive OR circuit 242 is the key code
All bits of signal KC are in register RG1~
Memory contents of any channel of RG7
When there is a match (however, as explained later, both logical
(used only when it is “1”), logic “0” output
Sending out power, therefore Noah Gate 243 is logical
“1” match detection output EQ₁match the channel
It is input to the memory circuit 241. The matching channel storage circuit 241 is
Master clock as well as registers RG1 to RG7
φ₁,φ₂16 stages driven by
It consists of a shift register. Ta
The output of the 16th stage is the output of the 1st stage.
It does not have a feedback loop, so once it is input
The data is sent to the master clock φ₁,φ₂of
16 cycles of time (this is the timing signal 1Y₁₆
~16Y₁₆after an elapsed time equal to one cycle of
– is lost due to overflow. However, the sampling hold circuit 13B
is timing signal 1Y₁₆One cycle depending on
The output signal from the key coder 12 is memorized during
On the other hand, registers RG1 to RG7 are
Timing signal 1Y₁₆16 channels during one cycle of
Because all the data in the channel goes through one cycle, eventually
Coincident channel storage circuit 241 is newly arrived
The same key code data as the key code data
If there is a channel that remembers the data, use this
Synchronized with the shift operation of registers RG1 to RG7.
You will memorize it while shifting it. In this way, the key code comparison circuit 240
- When the code signal KC arrives, its contents and
Data with the same content is stored in the memory circuit main body 237.
The purpose of detecting whether or not it has already been memorized is
Motsu. In this case, the key code signal KC arrives.
Match detection output EQ when not₁do not send
to prohibit this. i.e. key code
The key code signal KC is detected by the detection circuit 244.
A key code that is “0” when the
Obtains the mode detection output DEQ and sends it to inverter 2.
NOR gate 24 for match detection output via 46
3, and thus the key code signal KC arrives.
When the output does not come, the output of Noah gate 243 is always turned on.
is set to "0". Here, the key code detection circuit 244
Of the outputs from the sample hold circuit 13B
OR that receives note code bits N1 to N4
At gate 245, the key code signal KC is
held in sample hold circuit 13B
Sends confirmation output DEQ of logic “1” when
Ru. Match detection output EQ₁is a key code memory circuit book
To prohibit reading data into the body 237
Generates the read inhibit signal REG used for
It is applied to the read inhibit circuit 247 if possible. reading
The intrusion prohibition circuit 247 has a coincidence storage circuit 248,
It consists of a reading end signal circuit 249. The coincidence storage circuit 248 receives the timing signal 1
Y₁₆Coincidence detection output of "1" during one cycle of
EQ₁Remember this when obtained, and that memory
Memory times are stored from the temporary memory circuit 233 by the output.
Prohibits reading of data into the path body 237
established for a purpose. This is the new arrival
The content of the key code data is stored in the memory circuit itself.
stored in any channel of 237
If so, load this new key code.
Ru. This is because there is no need. The coincidence storage circuit 248 has a switch at the output terminal.
switching transistor 250 and capacitor 251
A delay filter connected to an output holding circuit 252 consisting of
The storage element 253 of the lip-flop circuit configuration is
Equipped with match detection output EQ₁input and gate
254 and further via the OR gate 255.
The master clock φ₁,φ₂
Read and read. read out to the output end
The “1” output is passed through the feedback AND gate 256.
Furthermore, the input terminal is connected via the OR gate 255.
was returned to the world, and thus dynamically remembered.
It can be done. The switching transistor 250 is the first transistor.
Timing signal 1Y corresponding to Yannel₁₆to
Therefore, it is opened only during that pulse width, and this
Depending on the storage state of the storage element 253,
A logic level “1” or “0” is applied to the capacitor 251.
is retained. On the other hand, the same timing signal 1
Y₁₆Returned via inverter 257 by
gate 256 is closed, which causes the storage
The memory of element 253 is reset. Thus one timing signal 1Y₁₆has arrived
After the memory element 253 is reset
2nd timing signal 1Y₁₆until it arrives
1 to 16 of the memory circuit main body 237.
As a result of channel comparison,
Match detection output EQ1 is on either channel.
If obtained, storage element 253 is set.
Accordingly, the second timing signal 1
Y₁₆Logic “1” of capacitor 251 by
charged to the level. And this condition is
3rd timing signal 1Y after₁₆has arrived
will be retained until This holding level signal is the output OR gate 25
8 as a read inhibit signal REG.
is applied to the switching control circuit 13F. Note that the input gate 24 of the coincidence storage circuit 248
5 from a key-off memory circuit 293, which will be described later.
The key-off detection signal D1 of the inverter 259
key-off storage circuit 293
remembers the channel that was keyed off.
Then, the channel is read out and its output D
When 1 becomes "1", the input gate 254 is
It is made to close. On the other hand, the read end signal circuit 249 is a temporary memory circuit.
Data from path 233 to memory circuit body 237
Immediately after reading the input gate circuit
No malfunction will occur after 235 is closed.
The purpose is to do so. i.e.
The read end signal circuit 249 is a delay flip-flop.
It has a storage element 260 with a double circuit configuration, and
Set signal from timing control circuit 13F
When the number S is sent, enter this and game
via the gate 261 and the or gate 262.
master clock φ₁,φ₂Yo
Read and read. read out to the output end
“1” output is passed through the feedback AND gate 263.
Furthermore, the memory request is sent via the OR gate 262.
is fed back to the input end of the die element 260, thus
Memorized by Namitsuku. Such a memory state is
Inverter for AND gates 261 and 263
Timing signal 16Y via 264₁₆(No.
Last timing signal corresponding to 16 channels
is cleared when given the
Ru. In this way, it is stored in the storage element 260.
The “1” output is read through the OR gate 258.
Timing control as the interference prohibition signal REG
is applied to the control circuit 13F. Sample and hold circuit 13B as described above
Key from to key code storage circuit main body 237
Input operation of code data or storage data
Rewriting operation is performed by timing control circuit
13F set signal S and reset signal
It is then executed. There are three timing control circuits 13F.
It has several control modes. The first control mode is key
- There is an empty channel in the code storage circuit 13C.
New key code data arrived while
Tokiko key code data to empty channel
The content is to allocate. This control model is shown below.
This mode is called the new key-on control mode. The second control mode is key code storage circuit 1
3C is full (in other words, empty channel is
When the new key code data arrives
key code that has already been released.
about the channel in which the code data is stored.
is generated based on the stored data.
When the sound is about to disappear, the corresponding channel
Newly arrived key code with memory data of le
The content is to replace data. below
The control mode is called truncate control mode.
cormorant. The third control mode is already released
Key codes for sounds that are involved in the keying process
about the channel that stores the code data.
If the amplitude of this decay waveform part is less than a predetermined value,
Reset the memory state of the channel when
The content is to set This control below
This mode is called reset control mode. Obtain control signal for new key-on control mode
Therefore, the timing control circuit 13F
is AND circuit 2 for new key-on control mode
71. This AND circuit 271
Key code storage circuit 1 as input condition signal
Sent from the 3C output OR gate 239
The busy signal A1 is passed through the inverter 272.
is received and prohibited from being read as the second input condition signal.
Invert read inhibit signal REG of circuit 247
a third input condition signal;
The key code of the key code detection circuit 244 is
Receives arrival confirmation output DEQ. Thus, the amplifier for new key-on control mode
The key code circuit 271 receives a new key code signal KC.
is held in the sample hold circuit 13B.
(The output of the OR circuit 245 is “1”)
), read inhibit signal from read inhibit circuit 247
provided that the number REG is not sent.
(In other words, the memory of the key code storage circuit 13C
key code during one cycle of code data.
If no match is obtained from the code comparison circuit 240 and
), key code storage circuit 13C
A busy signal A1 is generated from the output gate 239 of
(The empty channel is memorized)
Shift to the final stage of the circuit body 237
), it sends an output of "1".
AND circuit for this new key on control mode
“1” output of 271 is OR for set signal output.
Key code storage circuit 1 through gate 274
Open control signal to input AND gate 235 of 3C
as well as the reset signal output
Further, through the or gate 275 for
AND gate 238 for feedback via gate 276
is given as a close control signal. Thus, the input AND gate 235 opens.
When the feedback AND gate 238 is closed,
Therefore, the final stage of the memory circuit main body 237
For channels located on
The contents can only be blocked using the return AND gate 238.
The memory contents of the temporary memory circuit 233 are recorded all at once.
The data is read into the first stage of the storage circuit main body 237. However, in this way, the set signal is output once.
A set signal S is sent from the power gate 274.
The first stage of the memory circuit main body 237
When the new data is read, a read completion signal is sent.
The signal circuit 249 performs a set operation and therefore stores
Reading of data into the circuit body 237 is completed.
The read inhibit signal REG is generated when
AND circuit 27 for new key-on control
The output of 1 becomes “0”, which causes the key code to
AND gate 2 for input of the code storage circuit 13C
35 is closed and the feedback AND gate 238 is closed.
Open and prepare for the arrival of the next channel. write
Then, the memory circuit main body 237 receives the newly arrived key.
- Assign code data to empty channel and store
That's what I did. Next, the timing control circuit 13F
Timing signal in truncate control mode
and for truncate control mode to get
It has a circuit 277. This AND circuit 277
is the truncate circuit as the first input condition signal.
Truncated signal sent from route 13G
Receives MTCH and serves as the second input condition signal
Read inhibit signal REG of read inhibit circuit 247
received via the inverter 273, and the third input
As a condition signal, the key code detection circuit 244
Receives key code arrival confirmation output DEQ. Here, the truncate circuit 13G is the key code.
The storage capacity of the card storage circuit 13C (i.e., the
Key code signal KC with more than 16 channels
When the new key code arrived,
A key whose sound is already disappearing
Enter the channel that stores the code data.
It was replaced and memorized, and thus a new arrival occurred.
To ensure that key code data is memorized
It is established for the purpose of Truncate circuit 13G performs minimum value storage comparison
It has a circuit 280 and generates an envelope as described below.
Master clock φ from the generator₁,φ₂synchronized to
Regarding channels that arrive sequentially in time division
Sequentially compare the value E of the envelope signal ΣKA of
and the smaller value of the envelope signal ΣKA
is stored as the minimum value Q.
The value E of the coming envelope signal ΣKA is memorized.
When it is smaller than the minimum value Q (that is, when E<Q)
), outputs the minimum value detection signal Z of logic “1”
It is sent out via the AND gate 281. This AND gate 281 has key operation determination.
Key-off detection signal generated in circuit 13E
D1 is given as an open control signal, thus
The key code of the released key is assigned
Channel data is stored in key code storage circuit 1
Read from the memory circuit main body 237 of 3C,
At the timing, the envelope value E is the minimum
Sends minimum value detection signal Z when smaller than value Q
It is made to be. The minimum value detection signal Z is the minimum value storage comparison circuit.
The signal given to the fetch command terminal FETCH of path 280 is
At this time, the circuit 280 is actually arriving.
Let the contents of the envelope signal ΣKA be the minimum value Q.
and refreshed the memory, thus the 1st to 16th chiyanne
The sound that corresponds to the key code stored in the
Always remember the minimum envelope value of
It is done like this. The minimum value detection signal Z of “1” is the minimum envelope
stored in the loop value channel storage circuit 282.
Ru. The memory circuit 282 is the memory circuit described above.
Shift registers RG1 to RG7 of main body 237
Similarly, master clock φ₁,φ₂by
16-stage shift for reading and reading operations
It consists of registers and the final stage
“1” output is passed through the output AND gate 283.
and sends it as a truncated signal MTCH.
Ru. This output AND gate 283 has an open control
Receives the output of the 1st to 15th stages as a signal
The output of the Noah gate 284 is given, and thus
and the contents of the 1st to 15th stages are "0"
That is, it is stored in stages 1 to 15.
The sound encoder corresponding to the channel key code.
envelope means not the minimum value)
In other words, only the memory of the 16th stage
is “1”, the truncate signal MTCH is
Trunque through output AND gate 283
For AND circuit 277 for automatic control mode
give. Therefore, the AND times for truncate control mode
Path 277 indicates that new key code data has been sampled.
When held by pull-hold circuit 13B
and a read prohibition signal is sent from the read prohibition circuit 247.
Provided that REG is not sent
When the truncate signal MTCH arrives,
Sends an output of “1” at the timing and sets this.
key code via or gate 274 for
AND gate 235 for input of memory circuit 13C
to open this and reset the
via the port 275 and further to the inverter 276.
to the feedback AND gate 238 via
Close this. Therefore, the truncate signal MTCH is generated.
content of the channel (currently in the 16th stage)
) is stored in this master clock.
φ₁,φ₂Envelopes stored until now by
Temporary storage starts from the rope's smallest key code data.
New key code stored in memory circuit 233
will be replaced with the first stage data.
be remembered. As the output condition of the minimum value storage comparison circuit 280,
The key-off detection signal D1 used for
It is generated in the operation determination circuit 13E. The key operation determination circuit 13E
Key switch key-on memory circuits 291 and 2
92 and a key-off memory circuit 293.
Ru. These memory circuits 291, 292 and 2
93 is the same as the above-mentioned memory circuit main body 237,
Master clock φ₁,φ₂Shift movement by
Consists of a 16-stage shift register that operates
The memory contents of each channel are stored in the return amplifier.
through gates 294, 295, 296
and thus preserve memory dynamically.
It is designed so that First key switch key-on memory circuit 291
The key that has arrived at the sample hold circuit 12B
- Channel to which code data is assigned
Memory, for the purpose of retaining the key while it is being pressed.
It is provided. However, the key code when the key is pressed
As a response operation of the memory circuit 13C, a new
All contents that match the contents of the key code data are displayed.
The first place where there are already memorized channels.
case, and a second case where there is no such channel.
In the first case, there is a matching content.
Without updating the memory contents of the channel,
On the other hand, in the second case, a new data is added to the empty channel.
(or truncate if full)
Minimum Envelope Tilt Control Mode
(Replace with Jannel data). In either case, no keys are being operated.
Therefore, the channel corresponding to this
The "1" signal indicating that the pressing operation is in progress
Must be remembered. For this reason, the first key switch key-on memory time is
The line 291 is the timing control circuit 1.
Data to 3F key code storage circuit 13C
key-on in synchronization with the channel assignment operation.
Store the data in that channel location. That is, the memory circuit 291 first
Set signal output of switching control circuit 13F
It is received via the power OR gate 297. write
and send the newly arrived data to the empty channel.
When storing, the channel or
Insert new data with old data in Kate mode.
If the channel is changed, a logic “1” signal is sent to that channel.
is memorized. In addition, the memory circuit 291 secondly controls timing.
1st key switch of control circuit 13F
The output of the ON memory AND circuit 298 is input to the ON memory.
Received through Agate 297. Shikaruniko
The AND circuit 298 is the key code detection circuit 2
44 or gate 245 output DEQ and one
Match memory output of match channel memory circuit 241
EQ and match the new key code data.
The channel with the memory contents is the memory circuit itself.
This happened when he returned to the first stage of 237.
In synchronization with this, a logic “1” is stored in the memory circuit 291.
Read and store the signal. Here, the first key switch key-on memory circuit
The return AND gate 294 of 291 has a tie.
clearing control circuit 13F
The output of the control circuit 299 drives the inverter 300.
given through. AND circuit for clearing this
299 has a key-off detection timing signal X.
is given, which causes the signal X to become “1”
When all channels of memory circuit 291
It is designed to clear the memory of. Thus, the memory circuit 291 receives the signal X when it arrives.
assigned to channels 1 to 16 each time
The key with the specified key code is still being pressed.
It is necessary to check intermittently to see if there is a
Ru. Second key switch key-on memory circuit 292
are the 1st to 16th keys of the key code storage circuit 13C.
Key code data is stored in the channel
If the key code corresponds to
Turning on operation of key switch K2 (Fig. 3)
Remember the state. However, the memory circuit 292
The memory contents of channels 1 to 16 are stored in the master
Clockφ₁,φ₂It goes around in 16 cycles of
However, at this time, the data read from the output terminal is
As the second key switch on operation signal TK2
Send from output terminal WTK2. The input of the storage signal to the storage circuit 292 is through a tie.
2nd key of timing control circuit 13F
Output of AND circuit 301 for Itsuchi key-on memory
Input power through input or gate 302
To do this. This AND circuit 301
-Second key switch coming from coder 12
Motion detection signal KA2 and matching channel memory
With the output EQ of the circuit 241 as the input condition,
Key arriving at sample hold circuit 13B
Code data and key code storage circuit body 2
The record for any of the 37 channels.
When the stored data matches, the second key switch
Outputs "1" when the motion detection signal KA2 arrives.
Send out. Therefore, the memory circuit 292 is a key code memory circuit.
Arrival from channels 1 to 16 of Route 13C
A channel that remembers the same data as the data
is in the first stage of the memory circuit main body 237.
When you return, a “1” signal is sent at that timing.
and thus the second key switch K2
After turning on and until turning off, this
Dynamically outputs the “1” signal for the operation key.
memorize it clearly. In addition, for the feedback of the memory circuit 292
Timing control for AND gate 295
The reset signal of the control circuit 13F is given.
Ru. However, as mentioned above, the sample hole
Key code data arrived at the key code circuit 13B
is determined by the operation of the first key switch K1.
is formed, whereas the detection signal KA2 is
2 by the operation of key switch K2.
It can be done. Therefore, a new key code storage circuit 13C is required.
key code data is memorized.
output terminal for this storage channel.
The fact that “1” output was sent to WTK1 means that
The moment when the key switch K1 of No. 1 is turned on is
In contrast, the memory circuit 292
"1" output was sent to output terminal WTK2
This means that the second key switch K2 is turned on.
It represents the point in time. Therefore, the output terminal
Is it the time when signal TK1 is sent to WTK1?
, signal TK2 is sent to output terminal WTK2.
The time between the corresponding key presses is
The size corresponding to the pressing speed of the
It's going to be. Thus, regarding the speed of key operation
Channel data with signal TK1, TK2 type
It is now possible to send data from the processor 13.
Ru. The key-off memory circuit 293 stores key codes.
stored in each channel of circuit 13C
When the key corresponding to the key code is released, the key
The key code that is the same as the code is key coder 12
(i.e. the key
when the channel is turned off)
Remember. The key-off memory circuit 293 is the first key mentioned above.
Based on the output of the switch memory circuit 291
In the timing control circuit 13F
Memory operation is performed by the control signal generated.
do. i.e. timing control circuit
13F is an AND circuit 30 for key-off memory control
5 and has a first key as its first input signal.
- Output of switch key-on memory circuit 291
TA1 is received via the inverter 306, and the
Key code storage circuit 13 as input signal of 2
C's busy signal A1 is received, and the third input signal
The step code of the key coder 12 described above as
Key-off detection timing of control circuit 12E
receiving the switching signal X. Therefore, the key-off memory control AND circuit 30
5, the key-off detection timing signal X arrives.
If the first key switch is
If the "1" signal is not stored in the channel 291,
When the Yannel is returned to the input terminal (at this time
Memory output TA1 becomes “0”), busy signal
No.A₁provided that the arrival of
Sends a “1” signal and uses this as a key-off memory time.
via its input OR gate 308 to path 293.
and memorize it. In this way, the key-off memory circuit 293
Every time timing signal X arrives, memory times are
A channel that is not an empty channel of the channel body 237
key code corresponding to the key code.
Checks and memorizes whether the key is released or not.
That will happen. Note that the memory in the key-off memory circuit 293 is
Reset from timing control circuit 13F
Each time the output signal R is sent out, this
AND gate 29 for feedback via data 276
Cleared by being given to 6. Each channel of key code storage circuit 13C
The memory of is based on the sound of the key code that is its content.
After the key is released, the decay waveform part attenuates and stops.
Timing control circuit 13F
By the output of the AND circuit 309 for clearing
cleared. The clear AND circuit 309 has the first
Musical tone signal forming sections 7A and 7B serve as condition signals.
Decay end signal 2DF generated at
is given, and the second condition signal is the key
The key-off detection signal D1 of the key-off storage circuit 293 is
is given and its logic “1” output is used for reset.
Further, through the gate 275, the inverter 27
Return of key code storage circuit 13C via 6
and gate 238 is closed. However, the DAYK end signal 2DF is key.
At the 16th stage of the code storage circuit 13C,
Keycos stored in existing channels
Detects the end of Decay for the sound of the
Since there is data about this channel
It became impossible to return to the channel, and in the end the channel
will be cleared. Thus
This channel is called an empty channel.
and waits for the next data allocation. As described above, the channel processor
13 are sent sequentially from the key coder 12.
Requires simultaneous pronunciation of multiple key code data
Channels 1 to 16 depending on
Memorize the assignment and contents of each channel
(In other words, key keys for multiple sounds that should be sounded simultaneously)
information signals that are multiplexed in a time-division manner.
output from output terminals WN1 to WB3 as
Ru. However, the contents of this output information signal are shown in Figure 2.
Key information about the key code as shown in
It's IFK. The first information is key code information
In KC, memory times of key code memory circuit 13C
Note code obtained from path body 237
Consists of NOTE and block code OCT. Ma
The second information is key switch operation information.
Output OR gate 23 of code storage circuit 13C
Regarding the first key switch K1 obtained from 9.
key-on detection signal TK1 and the second key-on detection signal TK1.
Obtained from Itsuki key-on memory circuit 292
Key-on detection for second key switch K2
It becomes output signal TK2. Third information is key off
Key-off information that represents the state of the key-off record.
Key-off detection signal obtained from storage circuit 293
It will be TDO. These key information are as shown in Figure 1.
and second series parameter generation circuits 5A and 5
When sent to B as a parameter generation signal
Both contain information about key press operations, so-called
In order to form the touch information IFT,
serial control circuit 14 and afterco
control circuit 15 (second
figure). (1-4) Initial control circuit The initial control circuit 14 is operated by key press operation.
Determine the pressing down speed that is decreasing during operation.
Regarding the amplitude in equation (2) mentioned at the beginning,
variable T_oi(t) and T_oa(t) control constant
Purpose of generating a conditional signal to generate
A timekeeping logic circuit 14A and a variable circuit are provided.
14B (FIG. 2). The timekeeping logic circuit 14A is activated when a key is pressed.
When the first key switch K1 is turned on,
until the second key switch K2 is turned on.
time is memorized in the channel processor 13.
Supports channels for each simultaneous sound
This is shown in Figure 8.
As shown, the timekeeping clock oscillator 311 and the
Calculator 312 and operation time calculation storage circuit 313
and. The operating time calculation memory circuit 313 has 16 stages.
6-bit 16 with 6 columns of shift registers
It has a stage shift register configuration and a mass
Takurotsukφ₁,φ₂all bits by
The shift registers now shift all at once.
being done. Here, the shift register status is
It is the aforementioned Chiyan who set the number of stages to 16.
Channels 1 to 16 of Channel Processor 13
is determined in response to
Rosetsusa 13 is the key for channels 1 to 16
Each time the information IFK is sent, it is
key press speed for the corresponding channel key.
It is designed to memorize calculations. In other words, the input of the operating time calculation storage circuit 313
A 6-bit adder 312 is provided on the power side.
The output of each bit is input to the AND gate.
314 respectively in the memory circuit 313.
given to the bit register. Adder 312
implements a half adder as an addition element for each bit.
E, given from the clock oscillator 311 for time measurement.
"1" addition input 1AD and memory circuit 3
13 and the output of the 16th stage and store it.
To read it into the first stage of circuit 313
is being done. However, in the path of "1" addition input 1AD,
An input AND gate 315 is provided, the opening of which
Output of AND circuit 316 for starting calculation of closing operation
controlled by. That is, the AND circuit 31
0 is time division multiplexed from channel processor 13.
Channels 1 to 16 arrive with the formation of heavy signals
1st key switch key-on detection for
Receive signal TK1 as the first condition signal and
A similar second key switch is used as the second condition signal.
Convert the key-on detection signal TK2 to inverter 3
Receive via 17. Therefore, the amplifier for starting calculation is
For each channel of information, the code circuit 316
The first key switch, K1, is turned on and the key is turned on.
– When ON detection signal TK1 becomes “1”
(At this time, the second key switch K2 is still on.
Since it is not working, key-on detection signal TK2
is “0”), the output of logic “1” is disabled.
It is given to the AND gate 315 as a control signal, and its
After that, the second key switch K2 turns on.
When key-on detection signal TK2 becomes "1"
Until then, the AND gate 315 is controlled to be open. Therefore, the timekeeping clock oscillator 311
“1” addition signal 1AD is given to adder 312.
It can be done. On the other hand, at this time, the adder 312 and the operating time
The AND game provided between the arithmetic memory circuits 313
The key-on detection signal TK1 is applied to the gate 314.
is given as a control signal and therefore the adder 312
The key information of channels 1 to 16 is changed.
Every time it is transferred from the channel processor 13
The memory contents of the memory circuit 313 are synchronized with this.
is added to “1” and written in the memory circuit 313 again.
Repeat the action to memorize. This result storage circuit 3
13, the first key switch K1 turns on.
After that, the second key switch K2 turns on.
The time until the first
~Number of cyclic operation cycles of the 16th channel
It will be calculated and stored as . The calculation result (key-on signal TK2 arrives)
The result is the time measurement result) is the memory time.
16th stage of each bit register in path 313
Output terminal as binary code signal IND from eye
It is sent to U1 to U32. By the way, the second key switch K2 is turned on.
When the key-on detection signal TK2 is
By changing from "0" to "1", and
Gate 316 is closed, thus the "1" addition signal
1AD is no longer provided to adder 312.
Therefore, the adder 312 receives the data from the storage circuit 313.
Output as is without adding anything to the incoming data
data in the memory circuit 313.
The data is further input via the adder 312 and the AND game.
dynamically stored via port 314;
This stored data continues to the output terminals U1 to U32.
It will be sent out. This operation is performed sequentially after the key is released.
Are key-on detection signals TK2 and TK1 “1”?
This continues until the signal TK1 returns to “0”.
The gate 314 closes when the value becomes “0”.
By this, all the bits of the memory circuit 313 are
The memory becomes "0" and therefore the output terminals U1-U
The process ends when the output of 32 becomes “0”.
It becomes. In this embodiment, the output of the memory circuit 313
Power is applied to the NAND circuit 318, thus
The contents of all bits in the memory circuit 313 are
When it becomes "1", we get "0" output, and this is
Give it to AND gate 316 as a close signal.
Thus, the memory circuit 313 performs time measurement.
The keys are pressed more slowly than possible.
If the time measurement output is reached, this will happen after the maximum time measurement output is reached.
It is designed to maintain this. Thus, from the operation time calculation storage circuit 313
The sent time measurement output is sent to the code conversion circuit.
(ROM) 14B, which allows the subsequent stage
Initialize by translating into code signals that are easy to process.
Sent as reference data ITD. (1-5) Aftertouch control circuit The aftertouch control circuit 15 is a key press.
The pressing strength is determined during operation and the
Variable T related to amplitude in equation (2)_oi
(t) and T_oaGenerate the control constant of (t)
is provided for the purpose of generating conditional signals for
and receives the multiplexer 15A and its output.
A/D converter 15B (second
figure). The multiplexer 15A is as shown in FIG.
, key code of channel processor 13
KC (note code NOTE and block code
(in the OCT) and apply this to all keys.
Of the 88 output lines provided corresponding to
Line output g1 to g88 to the corresponding one (that
The logic level of the output line changes to "1"
The decoder 321 converts into
The line output g1 to g88 can be checked by key operation.
In the output circuit 11, each key is
Pressure pressure detectors DT1 to DT88 provided
(Figure 9)
Give it as an open control signal to G1 to G88.
It is being done. However, the key code KC is 16 as mentioned above.
Within the time-division multiplexing of channel data
Since the decoder 321 has a key code
Each time KC channel data arrives
, the corresponding key among gates G1 to G88
The gates are sequentially switched and controlled to open.
and the corresponding key for each arrival of each channel.
Pressing pressure detection outputs dt1 to dt88 are sequentially sampled.
is pulled and sent to the output terminal VDT.
It turns out. This output signal is an analog value, but this
is converted into a digital signal by the next stage A/D converter 15B.
Aftertouch data ADT after being converted to
Sent as . Aftertouch control in this way
Aftertouch control formed in circuit 15
Roll data ATD is the initial code described above.
The initialization formed in the control circuit 14
Keyboard information is generated along with control data ITD.
Sent as touch information output IFT of raw part 1
Ru. [2] First and second series parameter generation circuit The first and second series parameter generation circuits 5A and
and 5B are required when calculating equation (3).
The constant signal is time-divided in the keyboard information generator 1.
The 1st to 16th channels generated by multiplexing
Occurs sequentially each time key code KC arrives
key code KC as shown in Figure 10.
and tone selection signal VSS of tone selection switch 6.
The first constant of the ROM configuration controlled by both
Generation circuits 325 and 326 and tone selection switch
Controlled only by the tone selection signal VSS of 6
Second constant generation circuit 327 and 3 in ROM configuration
It becomes 28. First series (or second series) parameter occurrence times
First constant generation circuit 32 of path 5A (or 5B)
5, (or 326) is first the first series (or the second series)
The total volume constant K that determines the total volume of the series)₁(or
is K₂) occurs. Second, the timbre that determines the temporal change of the timbre in equation (3).
variable I₁(t) (or I₂(t))
Decide on the necessary constants, that is, the timbre at the beginning of the sound.
initial timbre constant IL₁(or IL₂) and the time of the tone
Tone change constant DR that determines the target change_I1(or
DR_I2) and the sound that determines the end level of Decay.
Color change stop level constant SL_I1(or SL_I2) and
Occur. Thirdly, the vibration for determining the envelope of equation (3) is
width level or envelope variable A₁(t) (also
is A₂(t)) are all constants necessary to calculate
In other words, the attack speed constant that determines the attack speed
AR_A1(or AR_A2) and determine the first decay speed.
rate constant 1DR_A1(or 1DR_A2)
and a second decay speed that determines the second decay speed.
Degree constant 2DR_A1(or 2DR_A2) and the decay after key release.
Decay rate constant DR that determines the speed_A1(or DR_A2)
and from the first decay speed to the second decay speed
Decay transition level constant that determines the level to which to move
1DL_A1(or 1DL_A2) and occur. Also, the first series (or second series) parameter generation
Second constant generation circuit 3 of raw circuit 5A (or 5B)
27 (or 328) first determines the frequency of the generated sound.
pitch constant B₁(or B₂) occurs, and the second part
Composition of diacritic (including harmonic and nonharmonic) components
The partial constant D that determines₁(or D₂) occurs. Third, the volume is determined according to the key touch operation.
Constant T for volume selection_1a(t) (or T_2a(t)
Constants necessary for calculation, i.e. initialization
The initial constant βi (or
δi) and the after constant β that responds to the after touch
a (or δa). Fourth, determine the tone depending on the key touch operation.
Tone selection constant T_1i(t) (or T_2i(t))
The constants necessary to calculate
The initial constant αi (also
is γi) and the after-definition that responds to the after-touch.
The number αa (or γa) is generated. First constant generation circuit 325, 3 which is ROM
26 is selected by the tone selection switch circuit 6.
corresponding to each basic tone, and
corresponding to each pitch or range of the key.
Each parameter K₁,IL₁,DR_I1,SL_I1, AR_A1，
1DR_A1,2DR_A1,DR_A1,1DL_A1,K₂,IL₂，
DR_I2,SL_I2, AR_A2,1DR_A2,2DR_A2，
DR_A2,1DL_A2(constant data) is memorized in advance.
put. Then, the first constant generation circuit 325, 3
26 has a tone selection switch as shown in Figure 10.
Tone selection signal VSS and key code from circuit 6
KC is input as an address signal,
The tone selection signal VSS and this address signal
The first constant generator circuit is
Reading of ROM of 325 and 326 is performed.
Ru. Therefore, this first constant generation circuit 32
Each parameter K generated from 5,326₁，
IL₁,DR_I1,SL_I1, AR_A1,1DR_A1,2DR_A1，
DR_A1,1DL_A1,K₂,IL₂,DR_I2,SL_I2，
AR_A2,1DR_A2,2DR_A2,DR_A2,1DI_A2is the sound
color selection signal VSS (i.e. basic timbre) and
The value of key code KC (i.e. key position (key note)
high) or key range (the range assigned to the key).
It changes depending on the situation. [3] Tone selection switch circuit The timbre selection switch circuit 6 imparts to the generated musical tone.
Generates tone selection signal VSS for the desired tone
and convert this into the first and second series parameter generation times.
11 to provide for paths 5A and 5B.
configuration can be applied. In other words, selectable tones, i.e. piano,
Harpsichord, Vibrafon......Xylophone
Correspondingly, normally closed contact b and normally open contact a and this
Tone selection switch consisting of movable contact c corresponding to
Chi CH₁,CH₂,CH₃......CH_ois provided
Ru. However, these switch CH₁,CH₂，
CH₃......CH_oThe movable contact c and the normally closed contact b are
Connected in series, that switch CH_oThe side edge
Connected to “1” level power supply, each switch
Selection output of each tone VSS1, VSS from normally open contact a
2, VSS3……VSS_oto send out
It is. Thus, switches CH1, CH2, CH3...
…CH_oSelection output VSS1, VSS2, VSS3...
…VSS_ohas the opposite order of priority and the same
When multiple switch selection operations are performed at the same time
Also, one tone selection output with the highest priority
It is designed to send out only the [4] First and second series musical tone signal forming section First and second series musical tone signal forming sections 7A and 7
B is the first and second term of equation (3), respectively.
The calculation is performed using the key information IFK and the key information of the keyboard information generator 1.
Touch information IFT and first and second series parameters
The constant output of the data generator circuits 5A and 5B and the damper
Execute based on the output of the pedal 9 (first
figure). First and second series musical tone signal forming sections 7A and 7
B has exactly the same configuration. Therefore, this specification
Now, let's talk about the first series musical tone signal forming section 7A.
The detailed configuration will be described. The first series musical tone signal forming section 7A is shown in FIG.
As shown in Figures B and B, the calculation of the amplitude term in equation (3) is
Amplitude term calculation circuit 331 to execute and conveyance of equation (3)
Carrier wave term calculation circuit 3 that executes wave term part calculations
32 and execute the calculation of the modulation wave term part of equation (3).
It has a modulation wave term calculation circuit 333. (4-1) Carrier term calculation circuit The carrier wave term calculation circuit 332
Key code storage circuit 13C of Rosetsusa 13?
Among the key codes KC that arrive from
Frequency converter 334 with ROM configuration
This is then converted into the standard note name (standard octave).
Convert to a binary number corresponding to the frequency of the pitch name (tone).
exchange. This conversion output is passed through an adder 335.
is applied to shifter 336. This shifter 3
36 is the reference pitch name tone that comes from the converter 334
The value corresponding to is included in the key code KC.
Octa assigned to block code OCT
Shape upward or downward by the amount corresponding to the curve number.
Thus, the output terminal is operated with a key press.
Consists of a binary value proportional to the pitch frequency of the key.
Send out frequency output FS. On the other hand, the adder 335 has a block code
Constant generation circuit for simulating tuning curve undergoing OCT
337 outputs are given. The number of times this constant occurs
Route 337 is a high octa even if it has the same note name.
The lower octave ones are slightly smaller than the lower octave ones.
Is there a need to tune to a higher frequency?
It was established to satisfy this, and the coming
The oct assigned to the block code OCT
The tuning output corresponding to the turb number is converted into a binary value.
and sends it as
By adding the frequency outputs of converter 334
The effect of tuning is obtained. The output of the shifter 336 is the accumulator 33
given to 8. This accumulator 338
is the output of the shifter 336 as the master clock φ
₁,φ₂Iteratively adds each time given,
Output when an overflow occurs in the addition contents
It is designed to send out pulses. deer
The output of shifter 336 is controlled as described above.
The size is proportional to the pitch frequency of the created key.
Therefore, within the addition of the accumulator 338
The rate of increase in volume increases as the pitch frequency increases.
As a result, sound is output to the output terminal of the accumulator 338.
An output ωt with a frequency proportional to the high frequency is sent out.
will be done. In this way, it is sent out by the accumulator 338.
The frequency output ωt output from the multiplier circuit 339 (first
2B), where the first series parameter
Second constant generation circuit 327 of data generation circuit 5A
is multiplied by the pitch constant B1 arriving from
The output B1・ωt of the multiplier circuit 339 is the carrier of equation (3).
It is sent out as the calculation output of the transmission term part. However, this calculation output B1・ωt is the key press.
It will have the pitch frequency of the operated key.
Ru. (4-2) Modulation wave term calculation circuit The modulation wave term calculation circuit 333 calculates the modulation wave term of equation (3).
A sin function generation circuit 341 configured in ROM to obtain
, and the circuit of the carrier term calculation circuit 332 described above.
The wave number output ωt is input to the first
Second constant generation of series parameter generation circuit 5A
Partial constant D1 coming from circuit 327
Calculated and input to the sine function generation circuit 341,
Therefore, the output terminal has a modulating wave frequency D1・ωt.
The sine wave output sinD1・ωt is sent out, and this
Sine wave output sinD1・ωt to multiplier circuit 343
given constant T_1i(t)・I₁Multiplication result with (t)
T_1i(t)・I₁(t)・_sioD1・ωt is the modulation wave term
It is sent out as the calculation output of the calculation circuit 333. Here, the constant input to the multiplication circuit 343
T_1i(t)・I₁(t) as shown in Figure 13
based on the output of the timbre function generation circuit 344.
will be accomplished. The timbre function generation circuit 344 basically generates timbre.
Something that generates the timbre waveform that determines the time change
In this example, as shown in Figure 14,
generates a basic timbre waveform output. Sunawa
The waveform output VW is the second key switch operation check.
When the output signal TK2 arrives (time t₁₁) to maximum value
MAX, then directly or curved
descending (e.g. exponentially) and level SL_I
After that, the value is maintained.
There is. In addition to this, the waveform output VW is a falling part.
W₁₁point in time t₁₂When the key is released with
It is designed to maintain the value at that time. In addition
In this waveform output VW, the falling period is M11
and the fixed period is M12. Such a waveform is shaped by the configuration shown in FIG.
will be accomplished. That is, the timbre function generation circuit 344
is a linear calculation circuit to form a linear descending waveform.
path 345 and for forming a curved descent waveform.
It has a curve calculation circuit 346, and a straight line calculation circuit.
345 has a subtraction operation as its basic operation, and curve calculation
The basic operation of the circuit 346 is addition.
Ru. The linear calculation circuit 345 is a channel processor.
16 key codes KC coming from Sa 13
16-stage shift corresponding to the channel
Memory consisting of registers arranged in parallel for 6 bits
It has a circuit 347, and these six shift registers
Master clock φ₁,φ₂
By reading and reading by
Channels 1 to 16 of key code KC
The contents of the memory circuit 347 are periodically shifted by the shift operation.
output of the 16th stage.
Connect the tone reference signal VOC to the input terminals Y1 to Y32.
and send it. However, the memory circuit 347 stores all the bits.
An input OR gate 348 is provided for the
through which a logic “1” set signal is output.
By giving XX to all bits,
The chip existing in the first stage of the storage circuit 347
Add “1” data to all bits in the channel
Let it read. Record a “1” signal in all these bits.
The memorized channel is read from the 16th stage.
This is the time t in Figure 14.₁₁in
The maximum value of the timbre reference signal VOC
It is sent to children Y1 to Y32. The set signal XX is the set signal forming circuit 34
At 9, from the channel processor 13
Incoming 2nd key switch key-on detection signal
Formed on the basis of TK2. i.e. detection
Signal TK2 is sent to the 2-input AND circuit 350 on one side.
It is given as a condition signal for
The subtraction signal M1/ of the subtraction signal control circuit 351
M2 is connected to the other condition via inverter 352.
given as a signal. Here, the calculation signal M
1/M2 is the drop in waveform output VW as described later.
Logic when in the lower interval MI1 (Figure 14)
``1'', whereas the other section M1
2 (i.e., an interval where the waveform output VW is constant)
At some point, it becomes logic "0". So the second key
Switch key-on detection signal TK2 arrives
Previously, the subtraction signal M1/M2 was “0”.
Since there is a detection signal TK2 in the AND circuit 350
When the channel whose value is "1" arrives, the
The output of the command circuit 350 becomes “1”, and this
are sent as set signals XX, XY. Therefore, as described above, all of the memory circuit 347
A “1” signal is set for all bits.
However, once from the AND circuit 350,
When “1” output is sent, subtract as described below.
When the signal M1/M2 becomes “1”, the
It is not possible to send out a “1” output from the command circuit 350.
It becomes. The input side of the memory circuit 347 has 6 stages of full addition.
An adder circuit 353 having an adder configuration is provided.
Stored as the first addition input of each stage of path 353
As each bit output of circuit 347 is given,
, the second addition input of each stage of the addition circuit 353
“1” input ADD with period controlled as<sub>1</sub>but
All stages given at once from AND gate 354
Thus, in the adder circuit 353, the storage times are
The value “1” is determined from the contents of each channel of path 347.
Subtract. This subtraction output is ORGATE 34
8 to the first stage of the storage circuit 347.
is read into. Here, given from the AND gate 354,
"1" input ADD<sub>1</sub>The rising width of is the memory circuit
Master clock used for 347 shift
Tsukφ<sub>1</sub>,φ<sub>2</sub>preselected to a length of 16 cycles.
Therefore, channels 1 to 16
Which channel is read out to adder circuit 353?
Now you can perform subtraction operations uniformly, regardless of the situation.
has been done. In this way, the calculation contents of the memory circuit 347
is read from the 16th stage.
Input “1” from AND gate 354 ADD<sub>1</sub>
Only "1" on the condition that has arrived.
subtracted, and conversely, if it has not arrived, no subtraction
The data is read into the memory circuit 347 as is without being
It can be done. Therefore, the subtraction speed of the contents of the memory circuit 347
The degree is given by the AND gate 354
"1" input ADD<sub>1</sub>In other words, the frequency of arrival of
It will be determined by the cycle. The output of AND gate 354 is a rectangular wave oscillator
355, and its repetition period is
Changed in programmable divider 356
After being controlled, through the AND gate 354
Sent out. However, the programmable divider 356
is the first constant of the first series parameter generation circuit 5A.
The timbre change generated in the number generation circuit 325
constant DR<sub>I1</sub>is given and corresponds to the value
Change the period of the output of the oscillator 355 to the magnitude
Ru. However, this timbre change constant RD<sub>I1</sub>is the tone
Basic sound selected by selection switch 6
Selected according to color and key pressed
Therefore, in the end, the subtraction of the linear calculation circuit 345
The velocity, and therefore the descending slope of the reference tone waveform VW,
selected basic tone and pressed key.
It is decided according to the pitch (or timbre).
Ru. On the other hand, the AND gate 354 receives its open control signal.
As a signal, the output M of the subtraction signal control circuit 351
1/M2 is given. This subtraction signal control time
The line 351 is used for the memory circuit 347 described above.
A similar 16-stage shift register 358
from the set signal forming circuit 349 described above.
A logic “1” through input OR gate 359
The set signal YY for specifying the subtraction channel arrives.
When we arrive, we will make sure that this is actually present in the first stage.
stored in the current channel. Shikaruniko
The channel that stores the “1” signal is the
When reaching the 16th stage, subtract this command signal
Provided to AND gate 354 as M1/M2
Eh, therefore, the output of the divider 356 is generated.
time (period of 16 cycles of the master clock)
), the corresponding “1” signal is sent to the register 358.
The section of the channel read from
and game only during the period of one lock period).
354 is opened, and at this time, the memory circuit 347 is opened.
Channels being read at the 16th stage
``1'' is subtracted from the contents of
ing. Shift register of subtraction signal control circuit 351
358's "1" signal is stored in the feedback and game.
circulation through port 360 and further through 359.
It is surrounded. Therefore, the subtraction finger is
command signal M1/M2 is generated, and the corresponding “1” signal
Subtracting the data of the channel that memorized the issue
The operation is repeated, and as a result, the linear calculation circuit 3
45 output end of the corresponding channel (i.e. push button).
The key to which the sound of the key being operated is assigned
waveform output falling linearly from
VOCs can be obtained. Recording of “1” signal of subtraction signal control circuit 351
Clear the memories by closing the return AND gate 360
There are two cases:
Ru. The first is the timbre reference waveform VW (Figure 14)
Falling waveform part W at₁₁is the planned level SL_I
In this case, the linear calculation time is
The output of line 345 is sent to comparator circuit 361 to determine one ratio.
It is given as comparison input B. On the contrary
The comparison circuit 361 has a second comparison input A as another comparison input A.
1st constant generator of 1 series parameter generator circuit 5A
Tone change stop level constant from raw circuit 325
SL_I1is given and satisfies the condition A>B
When (in other words, the falling waveform part W₁₁is selected
Determined according to the basic tone selected and the key pressed.
Maru level SL_I1(when it gets lower)
A signal TDF is sent out. This clear signal
TDF is the input OR of the subtraction signal control circuit 351
Through gate 362 and further inverter 36
Close control signal to AND gate 360 via 3
, thus actually register 35
Channels that exist in the first stage of 8.
Clear the contents to "0". Therefore, from now on, the subtraction information will be applied to the corresponding channel.
No. M1/M2 is no longer sent, and therefore
Close the AND gate 354 for "1" subtraction input
Regarding the contents of the memory circuit 347,
The subtraction operation is no longer performed, and the linear calculation time ends up being
The outputs of terminals Y1 to Y32 of path 345 are constant values.
(constant waveform in Figure 14)
Department W₁₂). In addition, in the case of the second clear, the tone reference waveform
Falling waveform part W in VW (Fig. 14)₁₁of
point in time t₁₂When the key is released in
Channel processor 13 key-off memory times
Key-off detection signal read from path 293
TDO passes through AND gate 364, and further
via OR gate 362 and inverter 363
and as a close control signal to AND gate 360.
given, thus currently register 358 no.
The contents of the channel that exists in the first stage
Clear to "0". So in this case as well, do the same as in the above case.
Outputs of terminals Y1 to Y32 of the linear calculation circuit 345
The force will maintain a constant value (Fig. 14)
Constant waveform part W₁₃). However, in the path of the key-off detection signal TDO
The inserted AND gate 364 has its closure
As a control signal, it comes from the damper pedal 9.
Damper pedal signal PO (logic “0” and
) is given via the inverter 365.
Thus, the arrival of the key-off detection signal TDO
When the damper pedal 9 is stepped on, the above-mentioned
The corresponding channel of the subtraction signal control circuit 351
Immediately perform Nell's memory clearing action and follow.
The linear arithmetic circuit 345 immediately stops the subtraction operation.
constant waveform part W of output waveform VW₁₃(1st
Figure 4) will be formed. The effect of the damper pedal 9 is as follows.
If the stepping on pedal 9 is stopped, then
Since it is stopped from the point, the linear calculation circuit 3
45 output waveform VW is when damper pedal 9 is released.
From the point where the waveform part W₁₂to go down to
Become. On the other hand, the curve calculation circuit 346 operates as described above.
The first line formed by the linear calculation circuit 345
4. Based on the basic timbre waveform VW as shown in Figure 4.
Makes it difficult to hear when a sound is generated.
It has been established to improve the following points. In other words, only by the linear calculation circuit 345
When forming the basic timbre waveform VW, the 14th
As is clear from the waveform in the figure, there is a linear descending section.
W₁₁followed by constant waveform part W₁₂Or W₁₃occurs
The transition will necessarily involve sudden changes.
This is done at a certain angle, and this sudden change is
This is one of the reasons why it is difficult to hear. So this
For example, if the change is close to an exponential change,
You can make it less difficult to hear by modifying it. In order to achieve this purpose, the curve of this example is
The arithmetic circuit 346 performs the writing of the linear arithmetic circuit 345.
In the memory circuit 347, the number of bits is reduced to 3 bits.
A memory circuit with a similar configuration except that
367 and addition circuit 3 of linear calculation circuit 345
In 53, the number of stages is 3 and the highest
I made it possible to send out a carry from a bit.
An adder circuit 368 having the same configuration except for
and. However, the 16th stage of the memory circuit 367
Each bit output of adder circuit 368
Input and game provided for each row
``1'' addition input coming from port 369
ADD<sub>1</sub>and the addition result is stored in the memory circuit.
It is directly fed back to the first stage of 367. Inputs for the first to third stages of the adder circuit 368
The force AND gate 369 is the linear calculation circuit 34
The output obtained from the storage circuit 347 of
In other words, the upper 3 bits output, that is, the 4th to 6th bits
Close control of output via inverter 370
Take it as a signal. Therefore, the memory circuit 34 of the linear calculation circuit 345
All contents of 7 are set by set signal XX.
From the state where a “1” signal is stored in the bit of
In the process of being subtracted by 1,
When the content of the 4th bit becomes "0"
(The contents of this bit are subtracted 8 times.
becomes ``1'' or ``0'' alternately each time)
“1” for the first bit of adder circuit 368
Addition input ADD<sub>1</sub>and thus memory circuit 3
Add the contents of 67 by ``001''. Also, the contents of the fifth bit of the memory circuit 347
becomes “0” (the contents of this bit are
Alternately every 16 subtraction operations
becomes “1” or “0”), the adder circuit 368
Give “1” addition input to the second bit,
Thus, the contents of the memory circuit 367 are changed to "010".
Add one. Furthermore, the 6th bit of the memory circuit 347
When the bit value becomes “0” (the contents of this bit
is alternately after every 32 subtraction operations.
becomes “1” or “0”), the addition circuit 368
Give “1” addition input to the third bit and hide
The contents of the memory circuit 367 are added by 100.
I'll go. As a result of this addition operation, the addition circuit 368
When a carry occurs in 3 bits, this is
The “1” addition input to the line calculation circuit 345
ADD₂given as. Note that given via AND gate 369
As the "1" addition input, the linear calculation circuit 34
5 through AND gate 354
A logical "1" input is used. The above-mentioned curve calculation circuit 346 is a straight line calculation circuit.
345 as follows. The memory circuit 347 of the linear calculation circuit 345
After being set to "11111111", it becomes "111000".
During the eight subtraction operations until
The contents of the 4th to 6th bits of the output of 347 are
Since it is "111", the linear calculation circuit 345 is originally
Performs a linear subtraction operation. After this 8th subtraction operation, the 16th
Until the subtraction operation is performed, the memory circuit 347
The 6th to 4th bits of the output are "110"
From, the addition circuit 368 of the curve calculation circuit 346
The content of the memory circuit 367 is “001” (in decimal notation).
``1'') is added, and the result of this addition increases.
Carry ADD at intervals according to speed<sub>2</sub>Outputs
Ru. However, this carrier ADD<sub>2</sub>The output of
The timing is the addition circuit 3 of the linear calculation circuit 345.
The timing when 53 performs the subtraction operation of “1”
Since they match, the adder circuit 353
Calculation input and addition circuit 3 of curve calculation circuit 346
Carry ADD from 68<sub>2</sub>(i.e. additional
force) at the same time. Therefore, Ki
Yarii ADD<sub>2</sub>Linear calculations are performed each time
Path 345 will not perform a subtraction operation. After this 16th subtraction operation, the 24th
Until the operation is performed, the output of the memory circuit 347 is
Will the 6th to 4th bits of power be “101”?
The addition circuit 368 of the curve calculation circuit 346 is
The contents of the memory circuit 367 are “010” (in decimal notation)
``2'') is added, and the result of this addition increases.
Carry ADD at intervals according to speed₂Outputs
Ru. That is, the 8th to 16th times mentioned above.
Carry ADD twice as fast as when₂send out
That will happen. Therefore, the linear calculation circuit 345
The subtraction operation will be thinned out at this frequency, and this
decrease in the output VOC of the linear calculation circuit 345
Speed decreases. In the same manner, the linear calculation circuit 345 is written.
The 6th to 4th bits of the output of the storage circuit 347 are
As "100", "011"......
The addition value from the calculation circuit 346 to the addition circuit 368 is
“011”, “100”……(“3” in decimal notation,
"4"......) and so on.
Therefore, carry ADD₂The output frequency is also 2
times, 2²Exponentially larger
I'm getting tired. According to this, the linear calculation circuit 3
The thinning frequency for the subtraction operation of 45 is also exponentially related.
becomes numerically larger, and therefore the memory circuit 347
Subtraction speed, in other words, the falling speed of the output waveform VW
The intensity will decrease exponentially. By providing the curve calculation circuit 346 in this way,
Therefore, the falling waveform part VW of the reference tone signal VOC
is the constant waveform part W₁₂Or W₁₃The sudden transition to
You can make the odd part rounder, making it easier to hear.
It can reduce the difficulty. In this way, the timbre function generation circuit 344
Reference tone formed by linear calculation circuit 345
The signal VOC is sent to the multiplication circuit 371 (Figure 12B)
is given to the first series parameter generation circuit 5
The constant coming from the first constant generating circuit 325 of A
number IL₁The variable I in equation (3) is multiplied by₁Output of (t)
Gain power. This variable output I₁(t) is then multiplied
Variable output T in circuit 372_1i(t) multiplied by
, the variable T in equation (3)_1i(t)・I₁(t) is obtained. Here, the variable output T_1i(t) is the keyboard information
Initial touch control circuit of raw part 1
14 and aftertouch control circuit 15
Initial touch signal ITD coming from
Formed based on aftertouch signal ATD
Ru. In other words, the initial touch signal ITD is
In the calculation circuit 373 (FIG. 12A), the first system
The input signal coming from the column parameter generation circuit 5A
is multiplied by the serial constant αi, and the after
The touch signal ATD is applied to the multiplier circuit 374.
The signal coming from the first series parameter generation circuit 5A
are multiplied by the after constant αa, and these multiplications
The results are added in adder 375 and added to the variable
T_1i(t) is applied to the multiplication circuit 372 described above.
available. The variable T obtained in this way_1i(t) is
After-touch signal ATD is activated while the player is pressing a key.
It responds to changes in the pressing force applied to the key.
becomes a temporal variable by changing over time.
It is something. Output T of multiplication circuit 372_1i(t)・I₁(t)
is a sine function generation circuit in the multiplication circuit 343
341 output_sioIt is multiplied by D1・ωt, and its
The multiplication result is the modulation wave term T of equation (3)_1i(t)・I₁
(t)・_sioModulation wave term calculation circuit representing D1・ωt
333. (4-3) Amplitude calculation circuit The amplitude term calculation circuit 331 calculates the amplitude term of equation (3).
K₁・T_1a(t)・A₁provided to obtain (t)
As shown in Figure 15, the volume function generation time is
381. This volume function generation circuit 381 generates a generated sound.
Basic amplitude including volume or envelope
The equation shown in Figure 16 that determines the time change of
Generates output AOC with envelope waveform ENV
be done. i.e. envelope waveform output
ENV can be set to the second key by pressing the normal key.
-Channel Pro when switch K2 is closed
Second key switch detection signal from setter 13
At the time TK2 arrived_{twenty one}a predetermined steep slope from
The voltage rises from the lowest value MIN to the highest value MAX.
Tack waveform section ENV₁And this waveform part ENV₁to
Next is the first day, which descends at a relatively steep slope.
Waveform section ENV₂And this waveform part ENV₂Followed by
Down to the minimum level MIN with a relatively warm slope
Falling second decay waveform part ENV₃It becomes. However, the second decay waveform part ENV₃in the middle of
If the damper pedal 9 is operated in
Operation point t_{twenty four}Minimum level with steep slope from
Dump ramp descending to Le MIN ENV_Fouris formed
be done. The volume function generating circuit 381 is shown in FIG.
The following structure is used to obtain the envelope waveform output AOC.
It has a structure. That is, the tones described above with respect to FIG.
A linear calculation circuit 345 of the function generation circuit 344,
Curve calculation circuit 346, programmable device
356, a straight line almost similar to the comparison circuit 361
Arithmetic circuit 382, curve arithmetic circuit 383, professional
It includes a grammar divider 384 and a comparison circuit 385.
Eh, the subtraction operation in the linear arithmetic circuit 382
A program that receives the period from the output of the oscillator 386
The period of the output pulse of the marble divider 384 is
Change by changing, thus falling
The basic structure is to create a falling waveform section.
, the same as the timbre function generation circuit 344 described above.
It's like that. However, the output pulse of the divider 384
ADD₃The period of each waveform part ENV₁~ENV_Fouragainst
Accordingly, an error occurs in the slope change control circuit 387.
The first
The constants coming from the sequence parameter generation circuit 5A
The number signal is used as a period setting signal to the divider 384.
It is set by giving it as a number. First, attack waveform part ENV₁caused
Therefore, the opening is controlled by the first gate signal M1.
The first series parameters are
Attack rate constant coming from data generation circuit 5A
Number AR_A1is given to the divider 384, which causes
Output pulse ADD of divider 384₃period of
the constant AR_A1control the size to correspond to
Therefore, the addition operation frequency of the linear calculation circuit 382,
In other words, the rising slope of the output waveform ENV is
Selected basic tone type (e.g. peer
harpsichord, etc.) and pressed keys.
Set accordingly. Also, the first decay waveform part ENV₂cause
Therefore, the gate is opened by the second gate signal M2.
The first series para
The first detector coming from the meter generating circuit 5A
i rate constant 1DR_A1is given to the divider 384,
Thus, in the same way as above, the output waveform ENV is
1st Decay waveform part ENV₂Select a downward slope of
Type of basic tone played and key pressed
Set accordingly. Furthermore, in the same manner, the second decay waveform section
ENV₃In order to generate
constant 2DR_A1by the third gate signal M3
Divider through gate GT3 which is controlled open
384 and thus selected basic sounds.
Depending on the color type and the key pressed, the second
Good waveform part ENV₃The slope of the first Decay wave
Shape ENV₂Set to a value greater than the slope of . On the other hand, the dump waveform part ENV_Fourgenerate
When the gate is set by the fourth gate signal M4,
Open GT4 and set the damping rate constant through this.
Number DR_A1is applied to the divider 384, and the second data
K waveform part ENV₃Even bigger slopes
Dump waveform section ENV_FourSet. Gate signal M for gates GT1 to GT4
1 to M4 are from the slope change control circuit 387,
2nd key switch key-on detection signal TK2
They are generated sequentially after arrival. The slope change control circuit 387 has 16 stages.
Memory circuit with shift register for 3 bits
388 and "1" to the output of the memory circuit 388.
Addition to be added and re-stored in the storage circuit 388
It has a circuit 389. The memory circuit 388 is
The memory circuit 390 of the linear calculation circuit 382 and
and the storage circuit 393 of the curve calculation circuit 383.
Similarly, the master clock φ₁,φ₂By
1st to 16th channel by moving the foot
Dynamically stores step data for each wheel.
Ru. Thus, as the output KT of the memory circuit 388
A 3-bit binary signal is sent and this is decoded.
4 line outputs M1 to M4 by Da396
converted. However, the output of the memory circuit 388
When KT is “000”, decoder 396
Similarly, when the signal M1 is “001”
Sends gate signal M2, and when it is "010", the gate signal M2 is sent.
Gate signal M3 is sent, and when it is “011”, the gate signal
No. M4 is sent, thus the slope change control circuit
387 indicates that the content of the memory circuit 388 is "000".
``1'' is added from the state to ``011''.
The gate signals M1 to M4 are arranged in the order according to the
Send sequentially. However, the adder circuit 389 and the memory circuit 388
There is a second key switch detection signal between
AND gate 39 with TK2 as open control signal
7 is provided, which causes the detection signal TK2 to be
When “0”, the memory circuit 38 of that channel
Set the memory contents of 8 to all bits ``0'' and output the detection signal.
When the number TK2 becomes "1", the memory circuit 38
Addition of the addition circuit 389 to the memory contents of 8
Start operation from "000" state
being done. However, the gate signal M1 of the decoder 396
2nd key switch detection signal in the output path of
AND gate 39 with TK2 as open control signal
8 is provided, which causes the detection signal TK2 to be
When it arrives, it first sends out the gate signal M1.
Ru. This gate signal M1 is given to gate GT1.
Therefore, divider 384 is constant AR_A1to
"1" signal ADD of corresponding period₃andgame
It is sent via port 399. here and
The gate 399 has a record of the linear calculation circuit 382.
A minimum value detector provided at the output end of the storage circuit 390
Inhibition signal 2 from output AND circuit 400
DF' is received via an inverter 401. death
The first condition for the Karuni AND circuit 400 is
All of the outputs of the storage circuit 390 as signals
The output of the NOR circuit 402 that receives the bit output is
is given and the second condition signal is
3. OR circuit receiving the fourth gate M3, M4
403 output is given. Therefore andgame
If the memory circuit 390 has no memory, the memory card 400 is
If the gate signal M3 or M4 is generated
(i.e., the second decay waveform part ENV₃
Or dump waveform part ENV_Fouris occurring
) works. Therefore, and gate 399
It is not prohibited when gate signal M1 is generated.
So, the divider that passed through the AND gate 399
384 output ADD₃is the bottom of the adder circuit 391
input to the lowest bit. On the other hand, the bits other than the least significant bit of the adder circuit 391
AND gate 404 for the bit input terminal
is provided, and this is controlled by the gate signal M1.
Prohibition control is performed via inverter 405.
Therefore, when the gate signal M1 is generated, addition is performed.
Circuit 391 comes to its least significant bit
The "1" signal will be added, depending on the
The waveform ENV of the output AOC of the memory circuit 390 is
constant AR_A1It rises with a slope equivalent to
Thus, the attack waveform part ENV₁is formed
Ru. In this state, the contents of the memory circuit 390 are
until all bits are logical ``1''
maintained. However, all bits are logical
If it becomes "1", use this as an AND circuit to detect the maximum value.
The logic “1” output is detected at the path 406.
The step circuit 407 of the slope change control circuit 387
It is given as step input signal AF. The step circuit 407 is an addition circuit for input signal AF.
389 via its input OR gate 408
In response, “001” is added to the memory contents of the memory circuit 388.
, and thus the decoder 396
2 gate signal M2 is generated. This second gate signal M2 is the gate GT2
is given, therefore the divider 384 is a constant
1DR<sub>A1</sub>“1” signal ADD with a period corresponding to<sub>3</sub>of
It is sent out through gate 399. Shikaruniko
When the addition circuit 391 of the linear calculation circuit 382
The prohibited operation for the input gate 404 is resolved.
has been excluded. Therefore, all of the adder circuit 391
“1” signal ADD to all bits<sub>3</sub>is given
As a result, the adder circuit 391 becomes the memory circuit 390.
We will subtract the contents of ``1'' at a time.
Therefore, the output waveform ENV of the memory circuit 390
is constant 1DR_A1Descending at a slope equivalent to
Thus, the first decay waveform part ENV₂is the shape
will be accomplished. At this time, the output AOC of the memory circuit 390 is
The first series parameter is generated in the comparison circuit 385.
Decay transition level coming from raw circuit 5A
Constant 1DL_A1and the output AOC is compared to this constant
1DL_A1The detection output 1DF is turned off when the
gate 409 (opened by gate signal M2)
controlled). This detection output
The force 1DF is the input gate 408 of the stepping circuit 407.
input as a step signal to the adder circuit 389 via
Powered. Therefore, the step circuit 389 is a memory circuit.
Add “001” to the memory contents of 388 and write
and the third gate signal M from the decoder 396
Generate 3. This third gate signal M3 is the gate GT3
is given, therefore the divider 384 is a constant
2DR_A1“1” signal ADD with a period corresponding to₃of
It is sent out through gate 399. At this time,
All of the addition circuit 391 of the line operation circuit 382
A “1” signal is given to the bit of
Therefore, the addition circuit 391 stores the contents of the storage circuit 390.
is subtracted by ``1'', depending on
The output waveform ENV of the memory circuit 390 is a constant.
2DR_A1a slope equivalent to (usually constant 1DR_A1phase
lower than the slope
Then, the second decay waveform section ENV₃is formed
Ru. In this way, the output waveform of the linear calculation circuit 382
ENV is the decay transition level constant whose value is
1DL_A1The slope will be eased at this point. In principle, this state (damper pedal 9
is not operated) of the linear calculation circuit 382.
The output waveform changes as the content becomes “0”.
The value of ENV becomes the minimum value M1M (Figure 16)
will be maintained until However, the contents of the memory circuit 390 become "0".
Then, the minimum value detection AND circuit 400 is discussed.
The detection output 2DF′ of the logic “1” is generated, and this
is the AND circuit 410 for generating the Decay end signal.
(Figure 12B). In this state, if the key is released, the second key
Switch-on detection signal TK2 is logic “0”
Therefore, the addition of the slope change control circuit 387
Disposed between the circuit 389 and the memory circuit 388
By closing the AND gate 397,
The contents of memory circuit 388 are cleared. Also
Output gate 398 of gate signal M1 is closed.
Thus, the control circuit 387 also enters the standby state.
Doru. The above operation is possible without operating the damper pedal 9.
This is the operation when the second decay waveform part
ENV₃Damper pedal 9 is operated in the middle of
(Time t in Figure 16_{twenty four}) and as follows
and dump waveform part ENV_Fouris formed. In other words, the step on the input side of the adder circuit 389
The circuit 407 includes an AND circuit for forming a dump waveform portion.
411 is provided, the first condition signal and
and the third gate signal M3 is applied, and the second gate signal M3 is applied.
The damper pedal signal PO is activated as a condition signal.
the third article.
The key-off detection signal TDO is given as the input signal.
It will be done. Thus, the second decay waveform section ENV₃
During the period when the key is released, the key release operation is
At the same time, the damper pedal 9 is operated.
, the AND circuit 411 outputs a logic “1”.
This is sent via the input OR gate 408.
and is inputted to the adder circuit 389 as a step signal.
It can be done. At this time, the addition circuit 389 is connected to the storage circuit 388.
, and thus the decoder
396 to generate a fourth gate signal M4.
Ru. This fourth gate signal M4 is the gate GT4
is given, therefore the divider 384 is a constant
DR_A1“1” signal ADD with a period corresponding to₃game
It is sent via port 399. At this time, the straight line
All of the addition circuit 391 of the arithmetic circuit 382
A “1” signal is given to the bit, and
The adder circuit 391 reads the contents of the memory circuit 390.
We will subtract "1" at a time, so
The output waveform ENV of the memory circuit 390 is a constant DR_A1
(usually the second decay waveform part)
ENV₃(sufficiently larger than the slope of)
then descends to the minimum level M1N and thus Dan
waveform section ENV_Fouris formed. As described above, the linear calculation circuit 382 is written.
The waveform output AOC obtained from the storage circuit 390 is
Volume function generation via output terminals Z1 to Z32
Amplitude level or envelope of circuit 381
Variable output A₁(t), multiplication times
415 (Figure 12B) for volume selection.
variable T_1a(t) and the multiplication result is
In the next multiplication circuit 416, the first series parameter
Overall volume constant coming from the data generator circuit 5A
K1, thus the amplitude term K in equation (3)
1・T_1a(t)・A₁(t) is obtained. Here, the volume selection variable T_1a(t) is the keyboard
Initial touch control of information generator 1
control circuit 14 and aftertouch control circuit
Initial touch signal coming from path 15
Based on ITD and aftertouch signal ATD
(Fig. 12A). In other words, Inishi
The alternation signal ITD is sent to the multiplication circuit 417.
comes from the first series parameter generation circuit 5A.
When multiplied by the initial constant βi,
, the aftertouch signal ATD is applied to the multiplier circuit 41.
8, the first series parameter generation circuit 5A
is multiplied by the after constant βa arriving from
These multiplication results are added in an adder 419.
and the variable T_1aThe multiplication circuit described above as (t)
415. The variable T obtained in this way_1a(t) is
After-touch signal ATD is activated while the player is pressing a key.
It responds to changes in the pressing force applied to the key.
becomes a temporal variable by changing over time.
It is something. (4-4) Output circuit The output circuit 421 (FIG. 12B)
Output T of harmonic term calculation circuit 333_1i(t)・I₁
(t)・sinD₁・ωt and carrier term calculation circuit 3
32 output B1・ωt and the amplitude term calculation circuit 3
31 output K1・T_1a(t)・A₁(t) Based on Toni
What forms the output of the first term of equation (3)
First, the output of the carrier term calculation circuit 332 and
The output of the modulation wave term calculation circuit 333 is sent to the adder 42.
After adding in step 2, the sin function of the ROM configuration is generated.
In the device 423, the output sin {B1・ωt+T_1i
(t)・I₁(t)・sinD₁・ωt}
Ru. The output of this sin function generator 423 is then multiplied by
In the calculation circuit 424, the amplitude term calculation circuit 331
is multiplied by the output of , thus making the first term of equation (3)
Achieved output K1・T_1a(t)・A₁(t)・sin
{B1・ωt+T_1i(t)・I₁(t)・sinD₁・ω
get t. By the way, this first term output is the first series of musical tones.
The key information IFK and
Tatsuchi information IFT is a time division multiplexed digital
Corresponding to the signal, time division multiplexing is also performed.
The result obtained after being processed as a digital signal of
and such digital signals are D/A
converted into an analog signal by converter 425
and finally a time division multiplexed analog signal.
The musical tone signal e of the first term to the musical tone generating section 8 as₁
Sent as . The same applies to the second series musical tone signal forming section 7B.
Similarly, time-division multiplexed analog signals are used to generate musical tones.
Musical tone signal e of the second term to the generating section 8₂sent as
be done. On the other hand, the amplitude term of the first series musical tone signal forming section 7A
The minimum value detection formed in the arithmetic circuit 331
Similarly, the output output 2DF' is the second series musical tone signal.
Formed in the amplitude term calculation circuit of the signal forming section 7B.
along with the minimum value detection output 2DF′
b. Input conditions to AND circuit 410 for generating end signal.
given as a condition, both series have an envelope
When the waveform output ENV reaches the minimum value M1N
Decay end signal 2 from AND circuit 410
Generates DF. This signal 2DF is a channel
Processor 13 timing control circuit
Clear signal generation condition signal for path 13F
given as. Therefore, the timing control circuit 13F
is cleared for key code storage circuit 13C
Sends a signal, which causes the memory circuit main body 2
Chiyan who actually exists in the first stage of 37
Clear Nell's memory. Therefore, from now on
The key code KC stored in Yannel
The pronunciation of the corresponding sound is stopped, and this change
becomes an empty channel. Further, the amplitude of the first series musical tone signal forming section 7A
Output K1・T of term operation circuit 331_1a(t)・A₁
(t) is the same as that of the second series musical tone signal forming section 7B.
The output K2・_2a(t)・A₂Add with (t)
The addition result is added in the circuit 430.
is the envelope signal ΣKA of the aforementioned channel.
Minimum value storage comparison circuit of channel processor 13
280. However, the envelope signal ΣKA is simultaneously
Regarding channels 1 to 16 to be pronounced,
represents the envelope of the musical sound occurring in
Therefore, each channel has an envelope.
is stored in the minimum value storage comparison circuit 280.
This is the maximum value when the
is stored as the minimum value in the small value storage circuit 280.
Ru. [5] Musical tone generator The musical tone generator 8 is a support system consisting of an amplifier, speakers, etc.
The first and second series
The signals arrive from the two-series musical tone signal forming sections 7A and 7B.
Time division multiplexed analog signal e₁and e₂include
The musical tone signals of the 1st to 16th channels are successively reproduced.
(Figure 1). However, the musical tones of the 1st to 16th channels are sequential.
Generated periodically by the master clock,
Since the period is short, in reality, all channels are heard by the human ear.
gives the same effect as if the sounds of
That will happen. The above is an example of the configuration of an electronic musical instrument according to the present invention.
However, in the above configuration, the overall operation can be controlled by key commands.
As described above for the reader 12 (Fig. 4 A to C).
The scale note of the 0th block “C”₁” key and the first block.
Rock scale note “C”₂”, “E₂” key is operated.
As an example, when a key is operated,
First, the first key switch K1 closes, and then the key is pressed.
The second key switch K is activated after a period of time corresponding to the speed has elapsed.
2 closes. However, the key coder 12 first uses the first key switch.
As the clock K1 is closed, the master clock φ
₁,φ₂(with a period of 1 μs)
A clock φ with a length of 16 cycles_C,φ_Dby
All delay flip-flop circuits are operated simultaneously.
Block the 0th and 1st blocks by
It is stored in the detection circuit 12B, and the priority order is
High block numbers (2nd, 6th in this example)
. . . The data is transmitted sequentially starting from the 0th block). Matako
The notes included in the sent block are notes.
Detected by the detection circuit 12D, among which priority
High note numbers (in this example, note names C, B...
. . . C# order). Thus
From the key coder 12, all keys currently being pressed are
Key code signal KC for the key of
By combining the code signal BC and the note code signal NC
) will be sent out sequentially. Thus, the channel processor 13 (FIG. 7A)
The key code signal KC that sequentially arrives at ~C) is
Master clock φ is connected to pull-hold circuit 13B.₁，
φ₂is held for a time of 16 cycles, and this 16
During the cycle interval, the key code storage circuit 13C
Notes on the 16 channels of the memory circuit body 237
Ratio of stored data to sample-held data
The comparison completes the cycle, thus resulting in three empty channels,
Each incoming key code signal KC is memorized.
Ru. In this way, the separate chips of the memory circuit body 237 are
Each key code KC stored in Yannel is set as the content.
The data stored will continue to be retained even if the key is subsequently released.
and the first and second series musical tone signal forming section 7A and
Decay end signal at 7B (Figure 12 A and B)
When 2DF occurs (i.e. the sound disappears)
), timing control circuit 13F (7th
The output of the clearing AND gate 309 in Figure A)
It will be cleared. Therefore, the key code storage circuit 1
3C usually contains the key code of the key currently being pressed.
The key has already been released, but there is still a decay wave.
The key code KC of the key that generates the shape part sound.
will be remembered. On the other hand, the key code data is stored in the memory circuit main body 237.
Once memorized, this will be used as the first key switch information.
first key switch key-on memory circuit 291
(Fig. 7B) is stored in the corresponding channel.
Ru. From the above key operations, the key code memory circuit body 2
37 and first key switch key-on memory circuit 29
The operation up to memorization of 1 is based on the startup pattern of the key coder 12.
The starting pulse TC is generated from pulse generation circuit 12F.
The result is a channel process.
The content of the key code signal KC that arrived at Tsusa 13 is
Stored in the key code storage circuit main body 237
If it matches any of the data, the arrival data will be returned again.
Let the data disappear without memorizing it.
Ru. Eventually, when the second key switch K2 closes, the
1 key switch K1 as described above.
The operation is performed in the key coder 12 and is currently
Regarding keys with key switch K2 closed
High priority block number and high priority
Detection is performed sequentially starting with the note number with the highest number.
The detection result is stored in the second memory of the note detection circuit 12D.
146 (FIG. 4B). This detection signal KA2 is sent to the channel processor 1.
3 timing control circuit 13F (7th timing control circuit 13F)
Figure A) through its second key switch for memory control.
2nd key switch key via AND circuit 301
The corresponding channel of the ON memory circuit 292 (FIG. 7B)
stored in the channel. In addition, the channel processor
The second key switch detection signal arrived at 13
Load KA2 into which channel of memory circuit 292
Each channel of the memory circuit main body 237
By comparing the contents of the incoming data with the contents of the incoming data,
The matched channel is stored in the matched channel storage circuit 2.
This is done by making a determination via 41. In this way, the first key switch K₁to the operation of
Accordingly, the memory data stored in the memory circuit main body 237
1st key switch key-on detection obtained based on data
Signal TK1 and 2nd key switch key-on memory time
Obtained based on the memory data stored in the path 292
The second key switch key-on detection signal TK2 is
Western touch control circuit 14 (Fig. 2)
is given by a large area corresponding to the interval between their arrival points.
Generate initial touch data ITD
Ru. On the other hand, the second key switch K2 is activated by key operation.
Pressure pressure detector located under the key after closing
Press the keys for DT1 to DT88 (Figure 9)
When the pressing pressure is changed, the
The detected outputs dt1 to dt88 are aftertouch controllers.
key press circuit 15 (FIG. 2), thus
Regarding the key code KC of the key
After-touch operation depending on the size of the after-touch operation.
Generate data ATD. Initial touch data thus generated
ITD and aftertouch data ATD is touch information
As IFT, key code KC as key information and
Both the first and second series musical tone signal forming sections 7A and 7
given to B. These forming portions 7A and 7B are
1st to 1st assigned to the Jannel processor 13
16 channels of data (i.e. time division multiplexing)
data), key information IFK and touch information
Based on the contents of the information IFT and the selection of tone selection switch 6.
Next, the first and second series parameter generation circuit 5A
and the parameters generated in 5B.
The waveform output is sequentially clocked by the master clock φ.₁,φ₂
It is transmitted with a period of 16 periods. In this way, the musical tone generator 8 outputs the 1st to 16th channels.
Regarding the channel, multiple tones obtained by equation (3) can be simultaneously
A musical tone with the same effect as the one produced is generated,
The musical tone is key information about the key of each channel.
Has a pitch compatible with IFK and has touch information IFT
Synthesis of sound with timbre and volume changes corresponding to
It has a structure as a sound. Note that the calculation operations of the musical tone signal forming sections 7A and 7B are as follows.
2nd key switch key on for each channel
On the condition that the detection signal TK2 has arrived.
It is executed (Figures 13 and 15), so it
emit unnecessary musical tones for previously arriving data.
Not alive. Stop pressing the key that corresponds to the musical tone being generated.
When you release the key, this musical tone enters the decay mode.
Then, the corresponding channel of channel processor 13
Regarding the first key switch key-on memory circuit 29
1 (Figure 7B) is the key-off detection timing.
By being cleared by signal
Key-off detection is performed by the timing signal
- is stored in the OFF storage circuit 293. In contrast to this
If the damper pedal 9 is not operated, the day-care period ends.
Slowly generate the musical tone signal until signal 2DF is generated.
Attenuate. Therefore, the first series and second series musical tone signal forming section 7
A and 7B are when damper pedal 9 is operated
Rapidly attenuates the musical tone signal. To the above code storage circuit 13C (Fig. 7B)
The key code data KC assignment storage operation is
If an empty channel exists in the code storage circuit 13C,
truncated if there is no empty channel.
stored in the boot circuit 13G (Fig. 7C).
the channel that is currently generating the musical tone signal with the minimum amplitude.
The key code data that is currently arriving
Rewrite it as data. Therefore, the new key information is then
It will be utilized while satisfying the optimal conditions.
Become. According to the embodiment described above, the key is pressed in response to a key operation.
The musical tone that corresponds to the pitch of the key that was pressed is output after
A phone that can produce multiple notes at the same time with trolling.
You can get child instruments. In addition, each musical tone signal type
In Naribe (7A and 7B in the above example)
For example, piano sounds and guitar sounds are different from each other.
In addition to forming a musical tone signal of timbre,
Furthermore, the total volume constant (K in the above example)₁and
k₂) changes according to the pitch of the pressed key.
For example, when operating keys in the low range of a keyboard,
Correspondingly generates the musical tone of the piano sound, and the key of the high range
It can generate musical guitar sounds in response to operations.
can. As described above, according to the present invention, the musical tone signal
Control waveform level for controlling volume and tone
or rate of change (rise time and fall time of control waveform)
time), pitch (key position) or range (key range).
and selected basic tones.
Since it is now possible to set the
Adjust the volume and timbre of the musical tones played on the piano, harpsichord, etc.
Compatible with various natural instrument sounds such as chord, vibrafon, etc.
Accordingly, the volume or timbre changes unique to each instrument sound can be adjusted.
It can be changed according to the chemical properties of various types.
High-quality musical sounds that closely resemble natural instrument sounds
Can occur over a range of sounds. Furthermore, in this invention, the above control waveform
Set the level or rate of change (time) to a constant
I'm trying to do it numerically using data.
Then, compare this value to pitch (range) and basic timbre.
You only need to change it accordingly, and the configuration for that is also non-trivial.
This is always easy and since it is numerical data.
It is also easy to preset the values of
This can be implemented very easily using a tall circuit.

[Brief explanation of the drawing]

Fig. 1 is a system diagram showing an example of an electronic musical instrument according to the present invention, Fig. 2 is a system diagram showing its keyboard information generating section, and Figs. 3 A, B, and C apply the key operation detection circuit of Fig. 2. A plan view, a side view, and a partially enlarged perspective view showing the operating mechanism of the key switch that can be operated, FIG. 4A,
B and C are connection diagrams showing the key coder in Fig. 2 divided into three drawings; Fig. 5 is a signal waveform diagram showing the master clock and timing signals related thereto;
FIG. 6 is a flowchart for explaining the operation of the key coder in FIG. 4, FIG. 7 is a connection diagram showing the channel processor in FIG. 2 divided into three drawings, and FIG. FIG. 9 is a connection diagram showing the initial touch control circuit in FIG. 2, FIG. 9 is a connection diagram showing the after touch control circuit in FIG. 2, FIG. 10 is a block diagram showing the parameter generation circuit in FIG. 1, and FIG. Figure 1 is a connection diagram showing the tone selection switch; Figures 12A and B are connection diagrams showing the musical tone signal forming section in Figure 1 divided into two drawings;
Figure 3 is a connection diagram showing the timbre function generation circuit.
FIG. 4 is a waveform diagram showing the reference timbre waveform, FIG. 15 is a connection diagram showing the volume function generating circuit of FIG. 12, and FIG. 16 is a waveform diagram showing its output waveform. DESCRIPTION OF SYMBOLS 1... Keyboard information generation section, 5A, 5B... First series, second series parameter generation circuit, 6... Tone selection switch, 7A, 7B... First series, second series musical tone signal forming section, 8... ...Musical sound generator, 9...Damper pedal, 11...Key operation detection circuit, 11A...
...key switch group, 11B...pressure detection element group,
12...Key coder, 12A...Key switch circuit, 12B...Block detection circuit, 12C...Temporary memory circuit, 12D...Note detection circuit, 12E
... Step control circuit, 12F ... Start pulse generation circuit, 13 ... Channel processor, 13A ... Periodic signal generation circuit, 13B ... Sample hold circuit, 13C ... Key code storage circuit, 13D ... Key code comparison control circuit, 13
E...Key operation discrimination circuit, 13F...Timing control circuit, 13G...Truncate circuit, 14...Initial touch control circuit, 14A...Timekeeping logic circuit, 14B...Conversion circuit, 15...Aftertouch control circuit ,1
5A...multiplexer, 15B...A/D converter, 331...amplitude term calculation circuit, 332...carrier wave term calculation circuit, 333...modulation wave term calculation circuit, 3
44...Tone color function generation circuit, 381...Volume function generation circuit.

Claims (1)

[Scope of Claims] 1. A pitch specifying means for selecting and specifying the pitch of a musical tone, a tone specifying means for selecting and specifying a basic timbre of a musical tone, and a pitch selected and specified by the pitch specifying means, and a musical tone signal forming means for forming a musical tone signal corresponding to the basic tone selected and specified by the tone color specifying means; and generating a control waveform for controlling the tone or volume of the musical tone signal formed by the musical tone signal forming means. a control waveform generating means for generating a control waveform, and constant data for determining the level of the control waveform generated by the control waveform generating means or the rate of change in the time change of the control waveform, each corresponding to a plurality of basic tones, and for a plurality of It has a memory stored in advance corresponding to a plurality of famous pitch ranges for each pitch, and includes a pitch selected and specified by the pitch indicating means or a range of this pitch and a basic selected and specified by the tone color specifying means. 1. An electronic musical instrument comprising: constant generating means for reading constant data corresponding to both target tones from the memory and supplying the constant data to the control waveform generating means.