JPH0140357B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an improvement in a function waveform generator used in an electronic musical instrument, and particularly to one that generates a function waveform by digital calculation. In electronic musical instruments, a function waveform generator (envelope generator) is used to generate a function waveform (envelope waveform) used to control the volume and timbre of musical tones over time. Conventional function waveform generators generate function waveforms by storing the values of each sample point of a function waveform in a waveform memory in advance, and sequentially reading each sample value from this waveform memory. However, in this type of function waveform generator, all sample values of the function waveform must be stored in the waveform memory, which requires a large amount of memory. In this case, a waveform memory must be provided for each function waveform. Therefore, the structure of the function waveform generator becomes complicated and the cost becomes high. The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a function waveform generator that has an extremely simple configuration and can generate a desired function waveform at low cost. In order to achieve the above object, the present invention includes a storage means for temporarily storing a function waveform value corresponding to the current value of the function waveform, and a predetermined operation is performed on the function waveform value stored in the storage means. calculation means for calculating a new function waveform value and storing the calculated new function waveform value in the storage means, and the calculation means repeatedly executes the calculation operation for calculating the new function waveform value at a predetermined timing. By configuring it to do so, a function waveform that changes sequentially over time is generated. Here, in the first generation, in order to generate a plurality of function waveforms at the same time, a plurality of storage locations are provided in the storage means, and the new function waveform value calculation operation is time-divided for each of the plurality of function waveforms by the calculation means. What is done, and constant generation means (ROM325,
326) is characterized in that it includes calculation control means for controlling function waveform calculations in accordance with constant data representing the waveform change rate of the function waveforms stored in 326). Also,
In the second invention, a new function waveform value calculation operation similar to the first invention is performed, and a second invention includes a second invention that stores data representing the current formation interval (state) in a storage location corresponding to a plurality of function waveforms. storage device (shift register 358 or storage circuit 388 in the embodiment), control means for updating and controlling data in this second storage device, and calculation control means for controlling function waveform calculation according to this data (in the embodiment). The present invention is characterized in that it includes an adder circuit 389, etc.). Further, in the third invention, the calculation control means (in the embodiment) controls the calculation of the function waveform value according to key information indicating the position of the key operated on the keyboard.
It is characterized by comprising ROMs 325 and 326, a rectangular oscillator 355, a program divider 356 or gates GT1 to GT4, a divider 384, an oscillator 386, and the like. An embodiment in which the present invention is applied to an electronic musical instrument having an 88-key manual keyboard will be described in detail below with reference to the drawings. First of all, the electronic musical instrument of this example is JP-A-50-
A musical tone signal is formed according to a frequency modulation method as disclosed in the publication No. 126406 (Japanese Patent Application No. 49-41602). Formation of a musical tone signal using this frequency modulation method is basically performed by calculating the formula e=ASin[ωct+I(t)Sinωct]...(1).
In this embodiment, in order to generate high-quality musical tones that are more similar to natural instrument sounds, the musical tone signal forming operation in equation (1) above is performed in multiple series, and the musical tone signals of each series are added and synthesized. ing. That is, the electronic musical instrument of this embodiment further develops the above equation (1) and calculates n=1 to n=5 based on the following equation (2).
A musical tone is generated by executing a plurality of series of musical tone signal forming operations. e= _s 〓 〓 ⁿ⁼¹ K _o・T _oa (t)・A _o (t)・sin [Bn・wt＋T _oi (t)
・I _o (t)・sin (D _o・wt)]...(2) Here, K _o (K ₁ ~ _{K s} ) is the overall volume constant of each series, and this determines the mixing ratio of all series. By selecting and changing these settings, you can change the volume and tone of the entire musical tone. T _oa (t) [T _1a (t) to T _sa (t)] is a volume selection variable for controlling the volume depending on the way the key is pressed, and the weight is given to the pressing speed information when pressing the key. an initial constant βi for assigning a value, and an after constant βa for weighting information on the pressure of pressing a key.
It is decided based on. A _o (t) [A ₁ (t) to A _s (t)] is a variable for giving an amplitude level or an envelope, and the 16th
To obtain the amplitude waveform ENV as shown in the figure, the attack speed constant AR _Ai ~ AR _As is selected to determine the attack speed of the attack waveform portion ENV1.
and a first decay rate constant selected to determine the decay rate of the first decay waveform section ENV ₂ .
1DR _A1 ~ 1DR _As , a second decay rate constant 2DR _A1 ~ 2DR _As selected to determine the decay speed of the second decay waveform section ENV ₃ , and the second decay waveform section ENV2 from the first decay waveform section ENV2 to the second decay waveform section ENV3. The decay transition level constants 1DL _A1 to 1DL _As selected to determine the level IDL when transitioning, and the attenuation when the attenuated waveform portion ENV4 is formed when the key is released at time t ₂₄ in the middle of the second decay waveform portion ENV3. Decay rate constant selected to determine velocity
It is determined based on DR _A1 to DR _As . The variable K _o・T _oa (t)・A _o in equation (2) with such content
(t) corresponds to the amplitude constant A in equation (1). Further, B _o [B ₁ to _{B s} ] is a pitch constant selected to determine the musical tone frequency, that is, the pitch, and represents the amount of change in frequency of each series of musical tone signals with respect to the reference angular frequency W. The variable B _o ·W in equation (2) having such content corresponds to the carrier wave angular velocity Wc in equation (1). Furthermore, T _oi (t) [T _1i (t) to T _si (t)] is a timbre selection variable for controlling the timbre depending on the way the key is pressed, and information about the pressing speed when pressing the key is used. It is determined based on an initial constant αi for weighting information on pressing pressure when a key is pressed, and an after constant _αa for weighting information on pressing pressure when a key is pressed. I _o (t) [I ₁ (t) to I _s (t)] is a timbre variable for determining the temporal change in timbre, and is the initial timbre constant I selected to set the timbre at the beginning of the musical tone. _L1 ～
I _Ls and the timbre change constant DR _I1 , which is selected to determine the rate of change of the timbre over time.
It is determined based on DR _Is and timbre change stop level constants SL _I1 to _{SL Is} selected to determine the timbre change stop level S _LI which means the end level of the timbre change. The variable T _oi (t)・I _o (t) in equation (2) with such content
corresponds to the modulation degree I(t) in equation (1). D _o [D ₁ to _{D s} ] is a partial constant selected to determine the modulation frequency, and by changing it, the composition of the partial components (consisting of harmonic and nonharmonic components) included in the musical tone signal can be changed. changes. The variable D _o ·W in equation (2) having such content corresponds to the frequency modulation angular velocity W _n in equation (1). By the way, formula (2) is expressed as a general formula, but in the example described below, when S=2,
That is, e=K ₁・T _1a (t)・A ₁ (t)・sin [B ₁・wt+T _1i
(t)・I ₁ (t)・sinD ₁・wt〕 +K ₂・T _2a (t)・A ₂ (t)・sin [B ₂・wt＋T _2
i (t)・I ₂ (t)・sinD ₂・wt]...Based on the formula (3), two series of musical tone signals are obtained, and a musical tone is generated by mixing these musical tone signals. This is what I did. The electronic musical instrument according to this embodiment includes the following elements as shown in FIG. Reference numeral 1 denotes a keyboard information generation unit, which generates key information IFK containing the pressed key number and touch information containing the strength, weakness, and speed of the key press as key information related to keys operated on the keyboard. Send IFT. Reference numerals 5A and 5B denote first and second series parameter generation circuits, which output parameter outputs PA1 and PA2 regarding musical tone signal waveforms in response to the output of the tone color selection switch 6 operated by the performer. However, the parameter information generated by the generation circuits 5A and 5B is assumed to transmit information regarding timbre other than the touch information IFT of the keyboard information generation section 1 described above. 7A and 7B are first and second series musical tone signal forming units which receive key information IFK and touch information IFT from the keyboard information generating unit 1, and also receive parameter information PA1 and parameter information from the parameter generating circuits 5A and 5B.
PA2, and based on this information, 2 is expressed by the first and second terms of equation (3), respectively.
A series of musical tone signals e ₁ and e ₂ are generated, respectively. Reference numeral 8 denotes a musical tone generating section, which is a sound system such as a speaker and an amplifier, and synthesizes the outputs e ₁ and e ₂ of the first and second series musical tone signal forming sections 7A and 7B.
A musical tone corresponding to the musical tone signal e expressed by equation (3) is generated from a speaker. However, with such a configuration, the musical tone generating section 8
The musical tone generated from the keyboard information generating section 1 has a pitch corresponding to the key information IFK sent out from the keyboard information generating section 1, has a tone selected by the tone selection switch 6, and is also sent out from the keyboard information generating section 1. The musical sound waveform is formed based on equation (3), which is the basis of the frequency modulation signal. On the other hand, this musical tone is generated by the damper pedal signal PO generated by the damper pedal 9 in the musical tone signal forming section 7.
It is controlled by being given as a control signal to A and 7B. In this embodiment, each component shown in FIG. 1 has the detailed structure described below. [1] Keyboard information generation unit As shown in FIG. 2, the keyboard information generation unit 1 includes a key operation detection circuit 11 that detects the operation status of each key on the keyboard, and a key operation detection circuit 11 that detects the operation status of each key on the keyboard, and a key operation detection circuit 11 that detects the operation state of each key on the keyboard. A key coder 12 that discriminates the given key number and sends out a key code signal KC consisting of a corresponding binary code signal, and assigns the output signal of this key coder 12 to any one of an arbitrary number of pronunciation channels. A channel processor 13 that sends out key information IFK, and an initial touch control circuit 14 that determines the key press speed based on the output of this channel processor 13 and sends it out as initial touch data ITD made up of a binary code signal. and key operation detection circuit 11
The key depression strength is determined based on the output of the aftertouch data ATD, which is a binary code signal.
It also has an aftertouch control circuit 15 that sends out signals as follows. [1-1] The key operation detection circuit 11 includes a key switch group 11A consisting of, for example, two key switches K1 and K2 each having a mechanical contact structure and provided for each key of a keyboard (88 keys in this embodiment). , and a pressure detection element group 11B consisting of depression pressure detection elements DT each having a piezoelectric element configuration, for example, provided for each key. Key switch K1 and K2
For example, as shown in FIGS. 3A and 3B, these are arranged in parallel to face the rear end 11D of the key 11C, and when the key 11C is pressed down, the engager 11E provided at the rear end 11D engages the movable contact 11F. and 11H, both switches K1 and K2 are closed. Here each switch K1 and K2
As shown in FIG. 3C, stepped portions 11I and 11J having different lengths are attached to the surfaces where the movable contacts 11F and 11H contact the engaging element 11E, respectively, so that when the key 11C is operated, the engaging element 11E In response to the upward movement, the first key switch K1 first engages the long step 11I to close the contact, and then the second key switch K2 engages the short step 11J to close the contact. ing. On the other hand, a depression pressure detection element DT is provided at a lower position of the operation end 11K of the key 11C.
During the pressing operation, after the second key switch K2 closes, the lower surface of the end 11K comes into pressure contact with the detection element DT, and a detection output corresponding to the pressing pressure is generated.
It is designed to generate dt. In this way, the key operation detection circuit 11 obtains the first
and contact outputs of second key switches K1 and K2
k ₁ and k ₂ are output from the key coder 12 as 88 pairs of key operation detection outputs including the operated key number and operation speed.
The detection output dt of the press pressure detection element DT is sent to the aftertouch control circuit 15 as 88 key operation detection outputs including the press pressure. In FIGS. 3A and 3B, 11L is a felt for the upper limit stopper, 11M is a cradle for the pressure detection element DT, 11N is a guide, 11P is a fulcrum, and 11Q
is a weight. [1-2] Key coder Key coder 12 is shown in Figure 4A
As shown in FIGS. ₁ to 2C, the key switch circuit 12A includes key switches K1 and _K2 , a block detection circuit 12B and its temporary storage circuit 12C, a note detection circuit 12D, and a step control circuit 12E. The block detection circuit 12B divides the keys of the keyboard (in this embodiment, one row consists of 88 keys) into one unit of block, for example, one octave, and detects and stores the block to which the operated key belongs (into a plurality of blocks). (If the keys are operated simultaneously, it may extend to a plurality of blocks), and the block number representing this stored block is stored in the temporary storage circuit 12C as a 3-bit binary code signal.
Further, the block detection circuit 12B sends the memory state of the block to the note detection circuit 12D through the key switch being operated on the keyboard. In this embodiment, 88 keys are divided into 8 blocks, 0th block to 7th block, as shown in Table 1.

[Table] On the other hand, the note detection circuit 12D detects and stores which note (that is, the note name) of the operated key is based on the signal received from the block detection circuit 12B via the key switch of the keyboard. In some cases, multiple notes may be stored if multiple keys belonging to the same block are operated simultaneously). The note number representing the stored note is sent out as a 4-bit binary code signal. Here, when a plurality of blocks are stored in the block detection circuit 12B, reading of each block is executed sequentially with a predetermined priority, and for each block to which this read operation is performed, the note of the operation key belonging to that block is is stored in the note detection circuit 12D. Reading of stored notes in the note detection circuit 12D is similarly performed sequentially with a predetermined priority order. The block number code signal BC stored in the temporary storage circuit 12C in this way and the note number code signal NC stored in the note detection circuit 12D.
is the combined 7-bit key code signal KC
Sent as . Block detection circuit 12B and note detection circuit 1
2D has the following detailed configuration. The block detection circuit 12B has eight detection circuit bodies BL0 to BL7 of the 0th to 7th blocks corresponding to the 0th to 7th octaves, and has a signal input/output terminal _L0.
~L ₇ corresponds to each block (octave)
A pair of key switches K ₁ and K ₂ belonging to (Figure 3)
are commonly connected to each fixed contact. The block detection circuit bodies BL0 to BL7 have the same configuration except for the configuration of the readout circuit, and each includes a storage circuit 111, a priority gate circuit 112, a readout circuit 113, and a signal input/output circuit 1.
14. Now, for example, to describe the detection circuit main body BL0 of the 0th block having a signal input/output terminal _L0 , when a logic "1" signal arrives at the signal input/output terminal _L0 , the memory circuit 111 receives the logic "1" signal from the step control circuit 12E. The "1" state signal IST ₁ is received by the delay flip-flop circuit 117 through an input AND gate 115 which serves as an open control signal, and further through an OR gate 116. The flip-flop circuit 117 reads this "1" signal using the read clock _φc , and then reads it using the read clock φD that arrives. However, the "1" signal read out in this way is sent to the feedback AND gate 118.
is further fed back to the input terminal through the OR gate 116, and this is fed back to the next clock φ _c ,
The data is read and read at φ _D , and thus the flip-flop circuit 117 stores and updates the data each time φ _c and φ _D arrive. This memory is reset by reading the "0" output of the feedback AND gate 118 by the clocks φ _c and φ _D when it is closed. In this way, the block detection circuit body BL0~
When a "1" signal arrives at the memory circuit 111 of BL7, it is given to the OR gate 119 and given to the step control circuit 12E as an any block signal AB (indicating that a key belonging to any block is being operated). It will be done. Flip-flop circuit 117 of memory circuit 111
The output of AND gate 1 of the priority gate circuit 112
given to 20. The AND gate 120 is supplied with a read condition signal RCS via an inverter 121, which comes from the block detection circuit main body (BL1 in this case) which is in charge of one octave high frequency range as an open control signal. The read condition signal RCS that has arrived from the previous stage is sent together with the output of the flip-flop circuit 117 via the OR circuit 122 as the read condition signal ROS to the subsequent stage. In the case of the present explanation, the 0th block BL0 is the last stage, so the read condition signal ROS is sent to the outside. However, the readout condition signal from the previous stage to the block detection circuit body BL7 of the highest range octave.
The input from the line 123 connected to the "0" level (ground level in this case) is used as ROS, and the read condition signal RCS from the lowest range octave block detection circuit body BL0 to the subsequent stage is the memory block signal MB. (Indicating that there is memory in one of the blocks) is sent to the step control circuit 12E. In this way, when the priority gate circuit 112 has a memory in a block of an octave in a higher range,
The memory of that block can be read from the memory circuit 111 with priority, and the memory block signal MB continues to be sent out as long as there is memory in any block detection circuit main body. Memory circuit 111 passing through priority gate circuit 112
The storage output of is the AND gate 12 of the readout circuit 113.
given to 4. The "2" state signal _2ST1 coming from the step control circuit 12E is applied to the AND gate 124 as an open control signal.
When receiving the storage output from the priority gate circuit 112, it is applied to the output line 125 at the timing of the "2" state signal _2ST1 . However, the output lines 125 of each block detection circuit body BL0 to BL7 are connected to three code conversion OR gates 1.
connected to the input terminals of 26 in a predetermined combination,
As a result, when there is memory in each block detection circuit body BL0 to BL7, the memory block number is sent as a 3-bit binary code signal _BC1 to the temporary memory circuit 12C at the timing of the "2" state signal _2ST1 . The temporary storage circuit 12C is the block detection circuit 12B.
A delay flip-flop circuit 131 receives each bit of the block number code signal BC ₁ through an input OR gate 130, and a delay flip-flop circuit 131 receives each bit of the block number code signal BC ₁ in parallel. Return AND gate 132 that is maintained dynamically
and an output AND gate 133. The return AND gate 132 is “1” or “3”
“1” and “3” state signals 1 and 3 ST ₁ that arrive from the step control circuit 12E during the state
In response, the contents of the period delay flip-flop circuit 131 in the "1" and "3" states are held, and the block number code signal _BC1 sent out by the block detection circuit 12B in the "2" state is newly transmitted to the delay flip-flop circuit 131. The memory is canceled in order to be stored in the memory. Further, as will be described later, the output AND gate 133 receives a memory note signal MN that arrives from the note detection circuit 12D when a note is stored therein, and thus receives a memory note signal MN when a note number code signal NC is sent from the note detection circuit 12D. At the same time, the temporarily stored block number code signal BC is sent out in parallel as the key code signal KC. Signal input/output circuit 11 of block detection circuit 12B
Reference numeral 4 refers to a block detection circuit 12B that receives information regarding the operated keys from the key switch circuit 12A, and provides information to the note detection circuit 12D based on this information.
The charging/discharging capacitor CB1 connected to the signal input/output terminals _L0 to L7 of BL0 to _BL7 and the input/output terminals L0 to L7
A charging transistor 136 connected between L7 and a logic “1” level power supply 135, and an input/output terminal
and a discharging transistor 137 connected between L0 to L7 and ground (its logic level is "0"). The discharging transistor 137 reads the memory of the storage circuit 111 from the AND gate 124 of the reading circuit 113, which is opened by the "2" state signal _2ST1 of the step control circuit 12E, as described above, through the OR gate 138. In response to this, the capacitor CB1 is discharged and the levels of the terminals L0 to L7 are reset to "0".
Similarly, a "0" state signal is sent from the step control circuit 12E via the OR gate 138.
0ST ₁ turns on and discharges capacitor CB1. On the other hand, the charging transistor 136 receives the output of the AND circuit 120 of the priority gate circuit 112 through the inverter 139 and the AND gate 140 which receives the "2" state signal 2ST ₁ as an open control signal.
When 1 is not in the memorized state, it turns on and capacitor CB1
is charged to the logic "1" level, thus maintaining the level of the input/output terminals L0 to L7 at "1". In addition, in practice, the charging/discharging capacitor CB1 is:
The wiring capacitance of the cords connected to the input/output terminals L0 to L7 can be used. The signal input/output circuit 114 having such a configuration is
As described later, the step control circuit 12E
The note detection circuit 12D
Signals are exchanged with the signal input/output circuit 149 via the key switch circuit 12A. On the other hand, the note detection circuit 12D has the following detailed configuration. The note detection circuit 12D has 12 note detection circuit bodies NT1 to NT12 corresponding to notes (C to C#) belonging to one octave, and a pair of input/output terminals TC ₁ # and TC ₂ # to TC ₁ and TC ₂ is connected through diodes d ₁ and d ₂ to the movable contacts of a pair of key switches K ₁ and K ₂ provided for each key of a corresponding note. Note detection circuit body NT1 to NT12 is memory circuit 1
The first memory circuit 145 corresponds to the first key switch _K1 , and the second memory circuit 146 corresponds to the second key switch _K2 . and,
It includes a priority gate circuit 147, a readout circuit 148, and a signal input/output circuit 149. For example, to describe the note detection circuit body NT1 of the note "C#" which has input/output terminals TC ₁ # and TC ₂ #, the first memory circuit 145 has input/output terminals TC 1 # and TC 2 #.
When a "0" state occurs on _TC1 # (this state occurs when the key switch _K1 is closed), this is inverted to a "1" signal by the inverter 150, and then the "0" signal coming from the step control circuit 12E is 2'' state signal 2 ST ₂ is applied to the delay flip-flop circuit 15 through an input AND gate 151 as an open control signal, and further through an OR gate 152.
Receive at 3. This flip-flop circuit 153
In the same manner as described above for the memory circuit 111 of the block detection circuit 12B, the received "1" signal is read by the read clock φc, then read by the read clock φD, and then read out by the feedback AND gate 154. Furthermore, it is fed back to its input terminal through the OR gate 152, and is read in again at the next clock .phi.c, .phi.D, read out, and thus dynamically stored. This memory state is maintained as long as the read condition signal RDS of "1" is applied to the feedback AND gate 154, and when the read condition signal RDS no longer arrives (that is, when it is "0"), the gate 1
The "0" output of 54 is read by the clocks φc and φD, and is reset by reading. On the other hand, the second memory circuit 146 performs the memory operation when the input/output terminal TC ₂ # is in the "0" state (that is, when the key switch K ₂ is closed). It is configured similarly to the memory circuit 145. Note that in this embodiment, the first memory circuit 145
inverter 150 and input AND gate 15
1, and through this OR gate 165, the output of the inverter 160 of the second storage circuit 146 is input to the flip-flop circuit 153 of the first storage circuit 145. When the first key switch _K1 is not stored in the first memory circuit 145 when the key switch K1 is operated, the signal from the second key switch _K2 is used to back up this malfunction. However, in the first memory circuit 145 of the circuit bodies NT1 to NT12, the flip-flop circuit 153
The input terminal of is connected to the OR gate 166, so that if there is at least one delay flip-flop circuit 153 that dynamically stores a "1" signal through the feedback gate 154, an any note signal is generated.
Sends AN (indicating that a note is stored in one of the circuit bodies NT1 to NT12). On the other hand, the outputs of flip-flop circuits 153 and 163 of memory circuits 145 and 146 are applied to AND gates 170 and 171 of priority gate circuit 147, respectively. This AND gate 170 and 1
71 is the note detection circuit body for a note name one note higher according to the note name arrangement of one octave as an open control signal.
A read condition signal RDS coming from NT12 to NT2 is applied via an inverter 172. The read condition signal RDS that has arrived from the previous stage is used as an open control signal for the feedback AND gates 154 and 164 of the first and second storage circuits 145 and 146 as described above, and is also used as an open control signal for the feedback AND gates 154 and 164 of the first and second storage circuits 145 and 146. A read condition signal is sent to the subsequent stage via the output of the flip-flop circuit 153 and the OR circuit 173.
Sent as RDS. However, the node detection circuit for the highest note name C
The input from the line 174 connected to the "0" level (ground level in this case) is used as the read condition signal RDS from the previous stage to NT12, and thus the note detection circuit body NT12 with the highest note name C receives the stored data with the highest priority. It is designed to read the information. In addition, the note detection circuit body NT1 for the lowest note name C#
The continuous condition signal RDS from
When there is data to be read in any of the 2D circuit bodies NT1 to NT12, the temporary storage circuit 12C
The block number data stored in the block number data can be sent out. The memory outputs passing through the AND gates 170 and 171 of the priority gate circuit 147 are connected to the output line 17.
5 and 176. Note memory circuit body
One of the output lines 175 of NT1 to NT12 is connected to the input terminals of four code conversion OR gates 177 in a predetermined combination.
When the memory of NT1 to NT12 is read out, the memory note number is output as a note code signal NC of a 4-bit binary code signal to the note number output terminal TN.
Output to 1 to TN4. On the other hand, the other output line 176 of the memory circuit body NT1 to NT12 is connected to the input terminal of the OR gate 178, thereby indicating that the key switch _K2 has been closed and the timing of the delay from the key switch _K1 . Output terminal TKA2 as operating signal KA ₂
is output to. The signal input/output circuit 149 is connected to the block detection circuit 1.
It takes in information sent from the signal input/output circuit 114 of 2B via the key switch circuit 12A, and the signal input/output terminals TC ₁ # and TC ₂ # to _{TC 1} and
Charge and discharge capacitor CN connected to TC ₂ respectively
1 and CN2, and the first terminal TC ₁ # to TC ₁ and the logic “1” level power supply 179.
charging transistor 180 and a second terminal TC ₂
#~ _TC2 and a second charging transistor 182 connected between the logic "1" level power supply 181. In this example capacitors CN1 and N2
, similarly to the capacitor CB1, utilizes the wiring capacitance between the note detection circuit 12D and the key switch circuit 12A. These transistors 180 and 182 are turned on by the "1" and "3" state signals 1 and 3ST1 sent from the step control circuit 12E, and charge the capacitors CN1 and _CN2 to the logic "1" level. The above is an example of the structure of the block detection circuit 12B and the note detection circuit 12D, and these operate as follows in synchronization with the state signal of the step control circuit 12E via the key switch circuit 12A. For example, the scale notes C ₁ , C ₂ ,
Suppose that the E ₂ keys are being operated at the same time. Therefore, the key of scale note C ₁ belongs to the 0th block, and the keys of scale note C ₂ and E ₂ belong to the 1st block. The "0" state is a standby state, and the "0" state signal _0ST1 turns on the discharging transistor 137 of the signal input/output circuit 114 for all detection circuit bodies BL0 to BL7 of the block detection circuit 12B, and connects the capacitor CB1 through it. Let it discharge. Therefore, all the levels of the input/output terminals L0 to L7 become "0" level. At this time, since the key switch of scale note _C1 is closed, the terminal L0 of the block detection circuit 12B of the 0th block is connected to the key switches K1 and K2.
"C" of the note detection circuit 12D is connected to the terminals TC ₁ and TC ₂ of the note detection circuit main body NT12 through the
Similarly, the block detection circuit BL of the first block
1 terminal L1 is "C" note detection circuit main body NT1
2 and terminals TE ₁ and _{TE 2 of} the "E _" note detection circuit main body NT ₄ . Therefore, the capacitors CN1, CN2 connected to the terminals TC ₁ , TC ₂ and TE ₁ , TE ₂ are also connected to the diodes d ₁ ,
d ₂ is discharged by the transistor 137 through the key switches K1 and K2 and becomes the "0" level. When the state changes from this state to the "1" state, the step control circuit 12E sends the "1" state signal 1ST ₁ and the "1", "3" state signals 1.
3ST ₁ is sent. The "1" and "3" state signals ₁ and 3ST1 are applied to the "C#" to "C" note detection circuit bodies NT1 to NT12 of the note detection circuit 12D, and their transistors 180 and 182 are turned on. Therefore, capacitors CN1 and CN2 are charged simultaneously through this. Along with this the diodes d ₁ and d ₂
``C <sub>1</sub> '', ``C ₂ '', ``E <sub>2</sub> '' which were further manipulated through
Capacitor CB1 connected to terminals L0 and L1 of block detection circuit 12B is charged through key switches K1 and K2 of the key. However, since key switches K1 and K2 corresponding to keys that are not operated are not closed, their capacitor CB1 is not charged. Therefore, a logic "1" is applied to the input/output terminals L0 and L1 of the block to which the operated key belongs (that is, the 0th block to which the "C <sub>1 "</sub> key belongs, and the 1st block to which the "C <sub>2" and "E 2</sub> " keys belong). Input is given. Therefore, an any block signal B is sent from the block detection circuit 12B to the step control circuit 12E. On the other hand, the "1" state signal <sub>1ST1</sub> is applied to the block detection circuits BL0 to BL7 of the block detection circuit 12B, and the input gates 115 of the storage circuits 111 are opened all at once. Therefore, the 0th and 1st block detection circuit bodies BL0 and
The memory circuit 111 of BL1 enters the memory state, and the block number to which the operated key belongs (in this case, the 0th and 1st blocks) is stored in the block detection circuit 2.
It is stored in B. When the state changes from this state to the "2" state, a "2" state signal <sub>2ST1</sub> is sent out from the step control circuit 12E. This "2" state signal <sub>2ST1</sub> is applied to the block detection circuit bodies BL0 to BL7 of the block detection circuit 12B, and is applied to the output gate 12 of the readout circuit 113.
4 all at once as an open control signal. However, at this time, only the detection circuit bodies BL0 and BL1 of the 0th and 1st blocks are in the memorized state, so the detection circuit body BL1 of the 1st block, which has a higher priority,
The read condition signal RCS is applied only to the AND gate 120 of the priority gate circuit 112. Therefore, the memory circuit 11 of the detection circuit main body BL1 of the first block
The stored contents from block number 1 are transmitted through priority gate circuit 112 and readout circuit 113, and binary code signal ``100'' is sent out as block number code signal _BC1 .
This 3-bit block number code signal _BC1 is applied to the temporary storage circuit 12C and is stored through the input OR gate 130 of each of the bit storage circuits BM1 to BM3. Note that the data stored in the detection circuit main body BL1 of the first block of the block detection circuit 12B is read out, and thereby the output gate 124 of the readout circuit 113 is read out.
When the output of inverter 12 becomes “1”, this
8 to close the return gate 118. Therefore, the flip-flop circuit 117 reads "0" by the clocks φ _c and φ _D of the next cycle.
Thus, the memory circuit BL1 of the first block is reset. At this time, the read condition signal RCS to the next stage is
By becoming "0", the conditions for reading the next lowest priority block (in this case, the 0th block) are set. On the other hand, the readout circuit 1
The first block number storage output of logic "1" read from the block detection circuit BL1
is applied to the discharging transistor 137 to turn it on. Therefore, the capacitor of the first block
CB1 is discharged through transistor 137.
Not _only this, but also _the circuit body (in this case "C" and "E" Note detection circuit body NT12 and NT4) capacitor CN
1. CN2 is also discharged through the transistor 137 of the block detection circuit main body BL1. "C" and "E" note detection circuit bodies NT12 and NT4 corresponding to the pitch name of the key operated in this way are given logic "0".
Input is given. On the other hand, a second "2" state signal _2ST2 is given from the step control circuit 12E to each note detection circuit body NT1 to NT12, and
Input gates 151 of storage circuits 145 and 146 of
and 161 all at once, the memory circuits 145 and 146 of the "C" and "E" note detection circuit bodies NT12 and NT4, to which "0" input is given, enter the memory state, and the keys operated in this way are stored. Among them, the notes of the keys belonging to the first block (in this case, "C" and "E") are detected by the note detection circuit 12.
It is stored in D. However, at this time, a read condition signal of logic "0" is applied to the priority gate circuit 147 of the "C" detection circuit main body NT12, which has a higher priority among the "C" and "E" note detection circuit main bodies NT12 and NT4.
Since the RDS is applied, the memories in the first and second memory circuits 145 and 146 are read out, and therefore, the binary code signal "0111" representing the note number is transmitted through the gate 177 of the readout circuit 148 to the first memory circuit 145 and 146. Note code signal NC from memory circuit 145
A second key switch operation signal " ₁ " indicating that the second key switch K2 has been operated is sent to the output terminals TN1 to TN4 through the gate 178 of the readout circuit 148.
is sent to output terminal TKA ₂ . Note that in practice, key switches K1 and K2 are
As described above with reference to the figures, after the first key switch K1 is operated, the second key switch K2 will be operated, and the difference in operating time will correspond to the operating speed of the key. However, as will be described later, the clocks φc and _φD are adjusted so that this operating time difference is sufficiently large compared to the periods of the clocks φc and φD.
The period of φ _D is selected. Therefore, the storage and readout operations of the first and second storage circuits 145 and 146 of the note detection circuit bodies NT1 to NT12 are not actually performed at the same time, but are performed with a time difference. On the other hand, since the "C" and "E" notes have been stored in the note detection circuit bodies NT12 and NT4, the memory note signal MN sent from the note detection circuit body NT1 having the lowest rank causes the output of the temporary memory circuit 12C. Gate 133 is opened and the block number code signal BC ₁ "100" stored in it is opened.
is sent to output terminals TB1 to TB3. Therefore, output terminals TN1 to TN4 and TB1 to TB
3 contains the key that belongs to the highest key octave (in this case, the first octave) and has the highest note name (in this case, the "C ₂ " key) among the operated keys. A 7-bit key code signal "011 100" containing a number is sent out as a key code signal KC. In this way, the note detection circuit body NT1~
When one or more of the memory circuits 145 of the NT 12 performs a memory operation, an any note signal AN is sent to the step control circuit 12E, and on this condition, the state enters the "3" state following the "2" state, and the step control circuit 12E enters the "3" state. The "1" and "3" state signals 1 and 3ST ₁ are sent out again from the circuit 12E. These "1" and "3" state signals 1 and 3ST ₁ turn on the charging transistors 180 and 182 of the note detection circuit bodies NT ₁ to NT12 again, thereby charging the capacitors CN1 and CN2 again. On the other hand, by applying the "1" and "3" state signals 1 and 3ST ₁ to the feedback gate 132 of the temporary storage circuit 12C, the first clock φ _c ,
When φ _D arrives, the flip-flop circuit 131
The output of the block number code signal BC1 is fed back to the input terminal again, so that the temporary storage circuit 12C stores the same block number code signal _BC1 again. On the other hand, "C" note detection circuit body NT1
2, the first clock φ _c , φ _D resets the memory in the storage circuit 145 (because the feedback gate 154 is closed due to the logic ``0'' signal from line 174), while ``E'' In the note detection circuit NT4, the logic "1" signal is stored again (the feedback gate 154 is "C" and the "1" read condition signal from the note detection circuit main body NT12 is stored).
(because it is opened by RDS). Therefore, in the first cycle of the clocks φ _c and φ _D , the memory of the "C" note detection circuit body NT12 is reset, and this causes the read condition signal RDS to the priority gate circuit 147 of the "E" note detection circuit body NT4. When becomes "0", the "1" output of the "E" note detection circuit body NT4 is read out to the readout circuit 148 through the output gate 170.
Thus, the "E" note code "0010" is read out from the readout circuit 148. In this way, output terminals TN ₁ to TN ₄ and TB1 to
A key code signal "0010100" representing that the key belonging to the first block and having the note "E", that is, the "E ₂ " key, has been operated is sent to TB3. When all the notes stored in the note detection circuit 12D are thus read out, the clocks φ _c ,
“E” note detection circuit by the second period of φ _D
NT4 memory is reset and any note signal
AN becomes "0". At this time, the step control circuit 12E returns to the "2" state again on condition that there is a memory block signal MB from the block detection circuit 12B. That is, the "2" state signal _2ST1 is sent again from the step control circuit 12E to the readout circuit 113 of the circuit main body BL0 to BL7 of the block detection circuit 12B.
given to. At this time, the 0th block number is coded into the temporary storage circuit 12C in the same manner as in the case of the first block described above, except that the memory of the 0th block that remains unread is read out through the readout circuit 113. At the same time as reading out the signal "000", the discharging transistor 137 is turned on and the capacitor CB1 and the key switch K of the "C ₁ " key are turned on.
1. Re “C” note detection circuit body via K2
Capacitors CN1 and CN2 of NT12 are discharged to set the storage circuits 145 and 146 of the "C" note detection circuit main body NT12 to a storage state. At this time, the state shifts to "3" again, and the data stored in the memory circuits 145 and 146 are immediately read out and sent out from the readout circuit 148 as a "C" note code signal "0111", thus output terminal TN
1 to TN4 and TB1 to TB3, a key code signal ``0111000'' indicating that the key of the ``C'' note code belonging to the 0th block, that is, the key of the ``C <sub>1</sub> '' note, has been operated is sent. By the way, when this operation is completed, the feedback gate 154 is closed in the memory circuit 145 of the "C" note detection circuit body NT12 (line 1
74 is "0"), the any note signal AN is not generated from the note detection circuit 12D, and the memory block signal MB is not generated in the block detection circuit 12B either. Then it returns to the "0" state, that is, the standby state. The operations of each part of the key coder 12, such as the start of the memory operation of the block detection circuit bodies BL0 to BL7 and the output of signals from the block circuit bodies BL0 to BL7 to the note detection circuit bodies NT1 to NT12, are controlled by the master clock by the step control circuit 12E. Controlled by synchronously generated step control signals. The step control circuit 12E receives the starting pulse TC generated by the starting pulse generating circuit 12F.
The data transfer clock φ <sub>c</sub> ,
The above-mentioned step control signals 0ST <sub>1</sub> , 1ST <sub>1</sub> , 2ST <sub>1</sub> , 2ST <sub>2</sub> , 1.3ST <sub>1</sub> are generated in synchronization with <sub>φD</sub> . In this embodiment, the starting pulse generation circuit 12F
The oscillator 18 has a low frequency clock oscillator 181 having a rectangular wave generation circuit configuration, for example, and a delay flip-flop circuit 182 connected to its output terminal.
1 is given to the 2-input AND circuit 183 as one condition input, and the output of the flip-flop circuit 182 is inverted by the inverter 184 and given to the AND circuit 183 as the other condition input. oscillator 18
1 becomes the logic "1" level, and thereafter the flip-flop circuit 182 reads the logic "1" signal with the clock φ <sub>c</sub> and continues until the flip-flop circuit 182 reads the logic "1" signal with the clock φ <sub>D.</sub> Send TC. Here, the oscillation frequency of the low frequency clock oscillator 181 is determined mainly by taking into account the conditions for detecting keyboard operations, such as avoiding the influence of chattering.
It is selected to be approximately 1ms. On the other hand, the data transfer clocks φ <sub>c</sub> and φ <sub>D</sub> have sufficiently short cycles suitable for one round transfer of data for each note corresponding to the maximum number of simultaneous notes, and are arranged in the channel processor 13. 7th to be done
It is generated by a synchronizing signal generating circuit 13A as shown in FIG. The synchronization signal generation circuit 13A is a four-stage full adder 18.
5 and four delay flip-flop circuits 186 connected to each stage thereof. Each stage of the flip-flop circuit 186 is supplied with a master clock φ <sub>1</sub> (φ <sub>1</sub> in FIG. 5) having a period τ of 1 μs, which is generated by a separate master clock oscillator (not shown), as a read <sub>clock</sub> . On the other hand, a master clock φ <sub>2</sub> (FIG. 5, φ <sub>2</sub> ) delayed by 1/2 period is provided as a read clock. Therefore, the full adder 185 operates in response to the operation of the flip-flop circuit 186 every period τ of the master clocks φ <sub>1</sub> and φ <sub>2</sub> , and thus the output terminal of each stage of the flip-flop circuit 186 receives the period τ of the master clocks φ <sub>1</sub> and φ <sub>2</sub> . A binary coded hexadecimal code output (having ``1'', ``2'', ``4'', and ``8'' bits) is sent out in steps of . By appropriately combining the binary coded hexadecimal code outputs generated in this way, a timing pulse with a period of 16τ can be formed with a pulse width of one period τ of the clock pulse φ ₁ , and In the case of the embodiment, the synchronization signal generation circuit 13A generates the first, second, ninth, and sixteenth timing pulses _{1Y 16} , 2Y ₁₆ , and _{16Y 16 as} shown in _FIG . 9Y ₁₆ , 16Y ₁₆ are generated by AND circuits 188, 189, 190, 191, and the 16th and second timing pulses 16Y ₁₆ and 2Y ₁₆ are used as data transfer clocks φ _c and φ _D of the key coder 12. It is designed to be used as a The reason why a timing signal with a period of 16τ is generated here is based on the fact that the number of tones to be generated simultaneously is selected to be 16 tones. In other words, since the electronic musical instrument of this embodiment has a single-level keyboard structure with 88 keys like a piano, there is a possibility that keys for 10 fingers of both hands will be operated simultaneously, and how many keys have already been operated? Taking into consideration the possibility of a decay waveform, a total of 16 notes can be produced simultaneously. However, the master clocks φ ₁ and φ ₂ are divided into 16 periods, each period within the 16 periods is used as a time slot, and the data of each note to be produced simultaneously is assigned, and the corresponding data ( (hereinafter also referred to as the relevant data). Therefore, in FIG. 5, the first, second...16th clock of master clock _φ1
The periodic intervals T ₁ , T ₂ ...T ₁₆ are respectively the first and second...
...It will be referred to as the 16th channel. Based on this idea, the channel processor 13 processes data regarding each tone in synchronization with the master clocks φ ₁ and φ ₂ . Therefore, in cooperation with this, the step control circuit 12E is generated in synchronization with the master clocks φ ₁ and φ ₂ in the synchronization signal generation circuit 13A in order to cause the key coder 12 to perform an operation to determine which key is the operated key. The timing signals φ _c and φ _D are used. The synchronizing signals 16Y ₁₆ and 2Y ₁₆ generated in this way are used as the read and read clocks _φc of each delay flip-flop circuit in the key coder 12.
and φ _D , thus all delay flip-flop circuits are connected to the master clocks φ ₁ , φ ₂
The data is continuously read once every 16 cycles, and the read operation is repeated. The step control circuit 12E includes a step counter 203 made up of two delay flip-flop circuits 201 and 202 that receive a read clock _φc and a read clock _φD , and controls the stepping operation of the step counter 203 and outputs each state signal based on the stepping state. and a gate circuit 204 forming the gate circuit. The gate circuit 204 is the starting pulse generation circuit 12F.
It is activated by the activation pulse TC arriving from the block detection circuit 12B, and receives the any block signal AB and memory block signal MB generated by the block detection circuit 12B, and the any note signal AN generated by the note detection circuit 12D. Gives rise to four states.
In other words, the "0" state (standby state), the "1" state (detection state of the block to which the operated key belongs), and the "2" state (detection of the note of the key belonging to the detected block among the operated keys). A total of four states are generated: the "3" state (an operating state in which a key code is sent out based on the block note detection result), and the "3" state (an operating state in which a key code is sent out based on the block note detection result). As shown in Table 2, these states are determined by the output Q of flip-flop circuits 201 and 202,
This is established by the inverted output obtained through inverters 205 and 206 as follows.

【table】 The step control circuit 12E is at “0” step.
(i.e., flip-flop circuit in standby state)
The Q outputs of 201 and 202 are "0" and "0".
), the amplifier of the state signal input circuit 214
“0” state signal OST from gate 215₁but
It is being sent out. Starts when in this “0” state
When the pulse TC arrives, this gate circuit 20
AND gate 20 of state control circuit 206 of 4
7 is given. At this time, the flip-flop circuit
The outputs "1" and "1" of 201 and 202 are
Since it is given as a condition for the and gate
The input conditions for 207 are met and a “1” output is generated.
The second flip-flop circuit 202 has its input OR
is provided through gate 212. Therefore, the read and read clock φ_cand φ_DYo
In flip-flop circuits 201 and 202,
“0” and “1” are stored and “1” state state
become. At this time, the output of circuit 202 and circuit 2
The Q output of 01 is output from the state signal output circuit 214.
By being given to the gate 217, this
“1” state signal 1ST from gate 214₁sent by
Served. Therefore, as mentioned above, this "1" state signal 1
ST₁The block detection circuit 12B is activated by
Operated key switch of key switch circuit 12A
The block to which the hit belongs is detected and stored. However,
If any key of any block is operated,
-Block signal AB is step control circuit
12E and any block inspection
If the output circuit body BL0 to BL7 performs memory operation, a memo will be displayed.
Reblock signal MB is the step control circuit
Sent back to 12E. Any block signal AB is state control circuit 1
2E AND gate 211 (output of circuit 201
and the Q output of circuit 202 is already given.
) from this gate 211 to the circuit 20
“1” output is input to the 1 input OR gate 213.
It will be done. In contrast, the state control circuit 206
The activation pulse TC has already been applied to the gate 207.
Since the input or game of the circuit 202 is
A “0” output is input to port 212. Therefore, circuits 201 and 202 have readings for the next cycle.
Load and read clock φ_cand φ_Dby "1"
and “0” is stored and becomes “2” state.
Ru. Therefore, the AND gate of the state signal output circuit 214
First “2” stay signal 2ST from port 216₁but
At this time, the block detection circuit 12B
The memory block signal MB is coming from
The second from AND gate 218 with the condition
"2" state signal 2ST₂is sent. This first “2” state signal 2ST₁is a blog
is applied to the readout circuit 113 of the clock detection circuit 12B,
The highest priority stored block
The new block number is encoded and stored in the temporary storage circuit 12.
At the same time, it is read out to the
Furthermore, the notebook is detected through the key switch circuit 12A.
The signal of the note of the key being operated is sent to the output circuit 12D.
send the number. On the other hand, at this time, the second "2" state signal
No. 2ST₂are the first and second notes of the note detection circuit 12D.
Provided to and sent to storage circuits 145 and 146
Memorize the notes you took. However, note detection in the “2” state
When the note is stored in circuit 12D, Enino
The start signal AN is the step control circuit 12E.
This is sent back to the state control circuit 206.
AND gate 208 . On the other hand, andgame
Gate 210 is connected to memory block signal MB and circuit 2.
Since the Q output of 01 is given, the “1” signal is
It has occurred. Therefore, circuits 201 and 202 have
Next cycle clock φ_C,φ_Dinput by
"1" and "1" through ports 212 and 213
The signal is memorized and thus in the "3" state.
Ru. However, at this time, the note detection circuit 12D
is the highest priority of the memorized notes.
The high note number is coded through the readout circuit 148.
and sends it to output terminals TN1 to TN4. At this time, a block appears at the output terminal of the temporary storage circuit 12C.
This is the output terminal TB1 to TB.
given to 3. Therefore, terminals TN1 to TN4 to TB
The key code signal KC is sent to 1 to TB3.
It becomes. On the other hand, in the "3" state, the step control
The Q output of the circuit 202 of the roll circuit 12E is "1",
"3" state signal 1/3ST₁occurs again as
This is the signal input/output circuit of the note detection circuit 12D.
149, thus blocking the block detection circuit.
Note detection from 12B to note detection circuit 12D
Reset the signal transmission status. Along with this, “1”
"3" state signal 1/3ST₁is temporary memory circuit 1
given to 2C to update its memory. Here, the note stored in the note detection circuit 12D is
If there is only one item, the first and second memory
Memory of circuits 145 and 146 is in “3” state
Since the any note signal AN is reset to
It will no longer arrive. Therefore, the step control times
In state control circuit 206 of path 12E, the gate
The outputs of ports 208 and 209 become "0". Here, one block is detected in the block detection circuit 12B.
If only the ``3'' screen is memorized,
Memory block signal MB is “0” in state
Therefore, the AND game of the state control circuit 206 is
There is no "1" output on circuit 210, so circuit 20
A “0” signal is input to 1 and 202. Therefore, circuits 201 and 202 read the next cycle.
and read clock φ<sub>C</sub>and φ<sub>D</sub>“0” and
becomes the “0” memory state, thus the “0” state
The state returns to the standby state. On the other hand, if the block detection circuit 12B has 2 or more
blocks are memorized, one block is stored.
Memory still remains in "3" state for Tsuk
The block signal MB continues to arrive, so the status
“1” output is output to the gate 210 of the gate control circuit 206.
and this is provided to the circuit 201. Therefore, circuits 201 and 202 read the next cycle.
Clockφ<sub>C</sub>and read clock φ<sub>D</sub>"1" and
It becomes a memory state of "0", and the state signal output circuit
The “2” state signal is sent again from gate 216 of 214.
No. 2ST<sub>1</sub>Send out. Thus "2" state
Once the condition is reached, then do the following as described above.
Read and read clock φ<sub>C</sub>and φ<sub>D</sub>by "3"
Becomes a state state. Such a repetitive operation is performed by the block detection circuit 1.
Repeat until there are no more blocks stored in 2B.
However, as a result, the memorized block is lost.
and the block detection circuit 12B in the "3" state.
The memory block signal MB from
and the next period's clock φ<sub>C</sub>,φ<sub>D</sub>"0"
Return to Tate. In the above, the detected block is
As mentioned above, if the test included in one block
If there are multiple notes, the note detection circuit 12D
The readout for all detected notes is
Maintain the "3" state until the end. In other words, in the "3" state, the note
The any note signal AN from the detection circuit 12D is
The state control circuit continues to arrive naturally.
The “1” output continues to the gate 209 of the path 206.
is obtained, so the "3" state state is the next period's
Clockφ<sub>C</sub>,φ<sub>D</sub>will be maintained even when
It is from. As described above, the step control circuit 12E
operates in steps as follows. (a) When one key is operated. "0" → "1" → "2" → "3" → "0" step
Perform one cycle of the route. (b) Multiple notes for one block key
when a key is operated. "0" → "1" → "2" → "3" → "3"...
All notes like "3" → "0" state
The "3" → state is maintained until the reading is completed. (c) One key for each block
when operated. "0" → "1" → "2" → "3" → "2" →
"3"..."2" → "3" → "0" state
The reading for all blocks is finished.
Repeat the steps of “2” → “3” → “2” state until
return. (d) For multiple blocks, each has multiple nodes.
when the route is memorized. "0" → "1" → "2" → ["3-"3"...
"3"] → "2" ["3" → "33..."3"] → "2"
... "2" → ["3" → "3" ... "3"] →
Like the "0" state, ["3" → "3"...
``3''] Repeating operation to maintain the ``3'' state
and step operation of "2" → "3" → "2" state
is combined with the repetition of . The step control circuit 12E has the above configuration.
In addition to key-off detection timing signal output circuit
It has 220. Here is the key-off detection timing
Signal X is a key code signal in key coder 12
A key release operation is performed in connection with the KC generation operation.
The channel processor is used as a guide to determine whether
13. The key-off detection timing signal output circuit 220
Starting pulse coming from starting pulse generation circuit 12F
AND gates 221 and 222 that receive STTC
and flip-flop circuits 201 and 202.
Timing counter with Q output and hexadecimal counter configuration
Output TMO from the count end output terminal of 12G
In response to this, the starting pulse TC is activated in the “0” state.
When the signal arrives, a pulse-like signal is sent from the AND gate 222.
Generates "1" output and uses this as signal X at the output terminal
Sends to child TX and also via OR circuit 223
and sends a count start pulse to timing counter 12G.
Give as TMI. At this time, the counter 12G
is clock φ_Cand φ_DEach time ``1'' arrives,
During the addition operation, the output TM0 is
Set it to "0". In other words, the output TM0 is the counter 12
It remains "0" until G reaches its maximum value. The signal output circuit 220 outputs this "0" TM0
is inverted by the inverter 224 and the AND gate 22
1, thereby starting the starting pulse generation circuit 12.
OR gate when starting pulse TC arrives from F
223 to give a “1” output to the counter 12G.
By adding ``1'', the ``1'' addition operation is performed. This card
The start operation is performed by sending a start pulse to the start pulse generation circuit 12F.
It is repeated each time a russ TC occurs, thus lowering
A period of 16 cycles of the output of the frequency oscillator 181 has elapsed.
When this happens, all bits of counter 12G are output as “1”.
Since the output TM0 becomes “1”, the
Stops counting operation via the second gate 221
and the arrival of the activation pulse in the next “0” state.
We are forced to wait for the future. In addition, in the timing counter 12G, 22
6 is a four-stage full adder, and 227 is connected to each stage.
reading and reading clock φ_C,φ_Dmemory by
The operating delay flip-flop circuit, 228, is 4
The output of the flip-flop circuit 227 of the stage is input as the input condition.
When all conditions are “1”, send “1” output TM0.
This is an output AND gate. The operation of the key coder 13 having the above configuration will be summarized.
If shown as a flowchart, it would look like Figure 6.
Ru. That is, step 235 is in the "0" state.
Step control circuit 1
“0” state signal OST from 2E₁By
Capacitor CB1 of lock detection circuit 12B is discharged.
state and are generally on standby. Next, in step 236, it is determined whether TC=1 or not.
In other words, starting from the starting pulse generation circuit 12F
The presence or absence of pulse TC is checked and the occurrence is confirmed.
If not, it will still maintain the "0" state.
However, once you have confirmation that it is occurring, the next step is to
Proceed to step 237. This step 237 obtains the "1" state state.
"1", "3" state signals 1, 3
ST₁Capacitor of note detection circuit 12D by
CN1 and CN2 are charged and are currently being operated.
block through key switches K1 and K2.
The capacitor CB1 of the detection circuit 12B is charged.
Meanwhile, at the same time, the corresponding key of the block detection circuit 12B
- corresponds to the block to which switches K1 and K2 belong.
The input gate 115 to the memory circuit 111 is “1”
State signal 1ST₁opened by the capacitor
The charging state of CB1 is read into the memory circuit 111,
Thus the block to which the currently operated key belongs
The operating status is stored in the memory. This result causes the any block signal AB to be sent.
In step 238, check whether AB=1 or not.
This is done by checking. As a result AB=1
(i.e. being manipulated by one of the blocks)
(means there is a key), then the next step
Proceed to step 239, otherwise proceed to step 235
returns to the standby state of ``0'' state. Step 239 is the step to obtain the "2" state.
At the step, the step control circuit 12E
"2" state signal 2ST₁Block detection by
The successive circuit 113 of the circuit 12B is operated. deer
In particular, the readout circuit 113 reads the stored block.
Read out the one with the highest priority and its contents
block code signal BC₁Send out. Same as this
Connected to the block detection circuit body that performed a read operation at the time.
discharge the capacitor CB1. At this time
Key switches K1 and K2 are connected to this capacitor CB1.
Note detection circuit capacitor connected through
Sensors CN1 and CN2 also emit radiation through this connection loop.
Powered up. On the other hand, the first and second notes of the note detection circuit 12D
2 memory circuits 145 and 146 are step controllers.
"2" state signal 2ST from loop circuit 12E₂to
Therefore, read the discharge status of capacitors CN1 and CN2.
It's crowded. Next, in step 240, the block detection circuit
Memory block detection signal MB starts from 12B.
What is given to the push control circuit 12E?
(i.e. some block was memorized)
At the same time, in step 241, the
Any note detection signal AN from note detection circuit 12D
is given to the step control circuit 12E.
(i.e. any notes are memorized)
242), and proceed to the next step 242.
Here, if MB=1 in step 240,
In this case, there are no blocks to process, so the
Return to step 235. Step 242 is the step to obtain the "3" state.
At this time, select the note with the highest priority.
Read sequentially from Along with this, the step controller
“1” and “3” state signals 1 and 3 of the loop circuit 12E
ST₁Capacitor of note detection circuit 12D by
Charge CN1 and CN2, thus detecting the note
Blocking input to circuit 12D. and this
Memory circuit 1 of note detection circuit 12D at timing
45 and 146 perform a read operation, and the
The memory contents are read from the notebook through the readout circuit 148.
Convert it into a note code and send it. However, the operating state is determined in step 243.
checking the presence of any note signal AN.
(i.e. from step 243)
(Return to step 242). On the other hand, AN=1
When the note is no longer present, it is stored in the note detection circuit 12D.
Memory retrieval for all notes that have been
Now that the process has been completed, proceed to the next step 244.
move on. This step 244 checks whether MB=1.
If the step is affirmative, it is the end of the process.
The block data remains in the block detection circuit 12B.
This means that there is a
Go back and process the data in this remaining block.
cormorant. If a negative result is obtained for this, step
Control circuit 12E is "0" state signal 0
ST₁, and thus all operations are
After that, the process returns to the standby state in step 235. The above operation starts from the starting pulse generation circuit 12F.
It is repeated every time a starting pulse TC is generated. However, key-off detection is related to starting pulse TC.
The output timing signal X is processed according to the steps described below.
Therefore, based on the starting pulse TC,
-The following is related to the sending operation of the code signal KC.
and sent out. First, in step 245, the starting pulse generation time is determined.
The starting pulse TC generated at path 12F is counted as a counter.
Counted at 12G, overflow output
When TM0 appears, do this in step 246.
It is detected and the process proceeds to step 247. At this time, the step control circuit 12E
Sending “1” addition signal TMI to counter 12G
stop the output. In this state, the step control circuit 12E
“0” step signal 0ST₁to send out
and this is detected in step 248 and the next step is
At step 249, the trigger pulse TC was sent.
Check the timing. Once this confirmation is obtained, the following
At step 250, the step control
Sends key-off timing signal X from path 12E.
Ru. However, when the sending of this signal
Return to step 245 and set the start pulse TC counter again.
start. Thus, the key-off timing signal
The activation pulse that occurs after the sending of the code signal KC is completed.
Count the ST TC and the count number becomes "15"
When you get tired, the key code being executed at that time
It is sent after waiting for the signal KC sending operation to finish.
It turns out. [1-3] Channel processor Channel processor 13 should be sounded at the same time
Assign and record each sound data to channels 1 to 16.
These stored data are stored in the master clock φ.₁，
φ₂Figure 7 A to C
It has the following configuration. Here, the number of memory channels (this
(16 in the case of the example) is the maximum simultaneous output as described above.
The value is determined to match the number of notes, and all channels are
Channels with no stored data (hereinafter referred to as empty channels)
key to this empty channel if there is a
Read new key code data from coder 12
Load and set. The key code thus memorized
The data indicates that the corresponding key on the keyboard is pressed.
It will not be reset for a long time, and the sound will continue even after the key is released.
If you need a day key for the day key part,
It will not be reset unless the amplitude reaches a predetermined value. Channel processor 13 key code data
The memory of 1st to 16th channel data is mastered.
Takurotsukφ₁,φ₂is repeatedly circulated in series by
This is done dynamically by Thus da
The data of the 1st to 16th channels circulating to Inamitsuku
The data is monitored at one point in the circulation loop, and 16
The data of each channel is
data is read. Therefore, the content of each channel is
Master clock φ₁,φ₂A period with a length of 16 periods of
It will be read out and checked. The channel processor 13 is a key coder 12
The 7-bit key code signal KC, which comes from
- Off detection timing signal X and second key switch
A sample that captures and temporarily stores the Tsuchi operation signal KA2.
key hold circuit 13B and the captured key code signal.
Assign the number KC to one of the 16 channels.
The key code storage circuit 13C and the sample ho
The key code signal temporarily stored in the field circuit 13B
Each channel of No. KC and key code storage circuit 13C
based on the comparison results.
key code comparison control circuit that sends control condition signals.
13D and the data regarding the touch of the key operation.
The key operation discrimination circuit 13E for obtaining
Elements allow data to be captured, stored, compared, etc.
A timing controller that commands and controls the timing of
Troll circuit 13F and all 16 channels
When there is no empty channel, a new key code
When new key code data arrives, the old key code data is updated.
To replace the key code data with new key code data.
and a link circuit 13G. The sample hold circuit 13B is the key coder 12
Key code signal KC (note code signal) arriving from
Each bit N1 to N4 of No. NC and block code
consists of each bit B1 to B3 of signal BC) and key
Off detection timing signal X and second key switch
Set the motion detection signal KA2 correspondingly.
The storage element 23 via the gated gate circuit 231
Store in 2. In this embodiment, the gate circuit 231 is a field effect
Synchronous signal generation circuit 13A made up of transistors
(Figure 7C) Timing signal of the first channel
1Y₁₆(Figure 5 1Y₁₆) was held all at once by
and copy the input logic “1” or “0” level.
storage element 232 in a capacitor configuration. Thus, the data stored in storage element 232 is
Next cycle timing signal 1Y₁₆is coming
is retained in the storage element 232 until
If the same data has arrived from the key coder 12, it will be recorded.
Leave the memory of memory element 232 as it is, and
If the content of the key code that arrived changes, this
Memory of bit memory elements whose contents change according to
It is designed to change the state. However, for each bit of the key code signal KC,
The memory contents of the memory element 232 are stored in parallel with the key code.
Input data temporary storage circuit 23 of the code storage circuit 13C
given to 3. The temporary storage circuit 233 is a synchronization signal
Timing signal of the 9th channel of the generation circuit 13A
No. 9Y₁₆(Fig. 5 9Y₁₆), the reading operation is performed by
The timing signal of the first channel that arrives after that
1Y₁₆(Figure 5 1Y₁₆) due to read operation delay
It consists of flip-flops. In this way, the temporary memory circuit 233 stores the first
Timing signal 1Y₁₆sampling ho
The retention state of the data read into the field circuit 13B is
After stabilizing, timing signal 9Y₁₆By this
Read stable data and start the next 2nd cycle
Timing signal 1Y₁₆Read it with . Therefore this
Second cycle timing signal 1Y₁₆by
Reverse logic level to sampling hold circuit 13B
Even if the code is memorized, the 3rd cycle
Timing signal 1Y₁₆of one cycle until obtaining
At least the memory state should not be changed during this period.
ing. However, it is stored in the temporary memory circuit 233.
The received data is timing signal 1Y₁₆for one period of
and gate of the input gate circuit 234 as necessary.
memory via gate 235 and or gate 236.
Of the 1st to 16th channels of the circuit body 237
Stored in empty channel. The memory circuit body 237 stores each key code signal KC.
7 16 stage shifts, each corresponding to a bit
It consists of registers RG1 to RG7, and each stage has
and the first master clock φ₁By the front stage
The contents of the page are read and the second master clock φ₂
The contents read by
Ru. Therefore, the contents of seven registers RG1 to RG7
is master clock φ₁,φ₂1 step at the same time
Shift one page at a time. However, the 16th stage
The second output is the circulating AND of the input gate circuit 234.
via gate 238 and or gate 236
is fed back to the input end of the stage, and therefore each stage
Dynamically memorize without losing memory. There
at any time for registers RG1 to RG7.
specific stages (i.e., stages 1 to 1)
16 stages) contents for one channel, 7 bits
will represent the key code KC. For example,
1 channel timing signal 1Y₁₆upon the arrival of
The first stage of registers RG1 to RG7 in
The content of represents the key code KC for 1 note and 7 bits.
I will do it. Therefore, the memory circuit main body 237 is
Memorizes the maximum polyphony of 16 notes of key codes KC. 16th stage of shift registers RG1 to RG7
The output of the eye is derived from the output terminals WN1 to WB3, and
The data of channels 1 to 16 will be transferred to the 16th stage.
Key code output terminal WN1 every time the screen passes
~ Read to WB3. Thus, the output terminal WN1
~The memory data read out to WB3 will not be played simultaneously.
Code the key code KC of the power note using time division multiplexing.
It is sent as a coded simultaneous key code signal KC.
Served. On the other hand, note code among registers RG1 to RG7
The output of registers RG1 to RG4 that stores the
1st key switch key through or gate 239
Send to output terminal WTK1 as ON detection signal TK1.
Served. Also, “1” appears in this or gate 239.
When power is obtained, this is sent to busy signal A1 (16th stage).
There is memory data on the channel that passed through the page.
In other words, it is not an empty channel.
(representation). The data in the temporary memory circuit 233 is transferred to the memory circuit main body 2.
Which channel of 37 should be assigned and stored?
is the AND gate 235 of the input gate circuit 234
And the feedback AND gate 238 is connected to the timing controller.
Set signal S of control circuit 13F, reset
It is executed by controlling the opening and closing by signals.
Ru. However, the timing control circuit 13F
is the key code signal arriving from the key coder 12
The contents of KC and each channel of the memory circuit body 237
Based on the contents of the key code KC stored in the
The set signal S or
Send or not send a reset signal
Operate. Data from key coder 12 and memory circuit body 2
Comparison with 37 stored data is key code comparison control
This is done in circuit 13D. This comparison control circuit
13D matches the key code comparison circuit 240.
channel storage circuit 241. The key code comparison circuit 240 is a sample hold
Key code signal KC held in circuit 13B
Each bit N1 to B3 of is used as one input signal, and
The outputs of the corresponding registers RG1 to RG7 are
It has an exclusive OR circuit 242 that takes as an input signal,
The outputs of these OR circuits 242 are connected to the matching detection output node.
Give to Agate 243. Here, the exclusive OR circuit 242 is a key code signal.
All bits of KC are in registers RG1 to RG7.
When the memory contents of one of the channels match
(However, as described later, only when both logic is "1"
), sends a logic ``0'' output, and thus
NOR gate 243 outputs logic “1” match detection
EQ₁is input into the matching channel storage circuit 241.
Ru. The coincidence channel storage circuit 241 is configured using the above-mentioned register.
Similarly to data RG1 to RG7, the master clock φ₁，
φ₂16-stage shift register driven by
It is composed of a star. However, the 16th stage
The loop that feeds back the second output to the first stage is
Therefore, the data once input is mastered.
Lockφ₁,φ₂16 cycles of time (this is the timing
signal 1Y₁₆~16Y₁₆)
It will overflow and be used after the elapsed time. However, the sampling hold circuit 13B
Timing signal 1Y₁₆key for that one period by
While the output signal from coder 12 is memorized,
Then, registers RG1 to RG7 are timing signals.
1Y₁₆Data of all 16 channels during one cycle of
Because it goes through one cycle, it ends up being a matching channel memory circuit.
241 is the same as the newly arrived key code data
There is a channel that stores key code data.
If so, this is the shift operation of registers RG1 to RG7.
It is to be memorized by shifting in synchronization with
Ru. In this way, the key code comparison circuit 240
The same content as the code signal KC received when it arrived.
data has already been stored in the memory circuit main body 237.
The purpose is to detect whether or not the In this case the key
- Match detection when code signal KC does not arrive
Output EQ₁This is prohibited so that it is not sent. vinegar
That is, the key code detection circuit 244 detects the key code.
Becomes “0” when the code signal KC has not arrived.
Obtain the key code detection output DEQ and invert it.
NOR gate 24 for match detection output via data 246
3, and thus the key code signal KC arrives.
When there is no output, the output of Noah Gate 243 is always “0”
It is designed to do this. Here, the key code detection circuit 244
Of the outputs from the hold circuit 13B, the notebook
OR gate 245 receiving bits N1 to N4
, and the key code signal KC is sampled and held.
Confirmation of logic “1” when held in circuit 13B
Sends the recognition output DEQ. Match detection output EQ₁is the key code memory circuit body 2
Used to prohibit reading data to 37.
The read prohibition signal REG is generated.
The signal is applied to the stop circuit 247. Read prohibition circuit 247
are the coincidence storage circuit 248 and the read end signal circuit 24.
It becomes 9. The coincidence memory circuit 248 receives the timing signal 1Y.₁₆of
Coincidence detection output EQ of "1" during one cycle₁is obtained
When the
Data from the memory circuit 233 to the memory circuit main body 237
This is provided for the purpose of prohibiting the reading of data. mosquito
What you need to do is to check the new key code data that has arrived.
The content is one of the channels of the memory circuit main body 237.
If it is stored in , this new code will be loaded.
This is because there is no need to do so. The coincidence storage circuit 248 is switched to the output terminal.
The output consists of a transistor 250 and a capacitor 251.
Delay flip-flop connected to force holding circuit 252
A storage element 253 of a double circuit configuration is provided for detecting a match.
force EQ₁Input AND gate 254 and OR gate
255 and sends it to the master clock φ.₁，
φ₂Read and read. “1” read at the output end
The output is passed through the feedback AND gate 256, and further
is fed back to the input terminal via the OR gate 255,
It will be remembered dynamically. The switching transistor 250 is the first channel.
Timing signal 1Y corresponding to channel₁₆By the way
The memory element at this time is opened only for a pulse width of
Depending on the memory state of 253, a logic is applied to the capacitor 251.
The management level "1" or "0" is maintained. On the other hand, the same
Same timing signal 1Y₁₆Inverter 25 by
7, the return gate 256 is closed, and this
The memory of the memory element 253 is reset by this. Thus one timing signal 1Y₁₆has arrived
after the storage element 253 is reset.
Timing signal 1Y₁₆Until the arrival of
Regarding the 1st to 16th channels of the memory circuit main body 237
channel as a result of the comparison.
If the match detection output EQ1 is obtained, the storage element 25
3 is set, the second tie
Mining signal 1Y₁₆The capacitor 251 is
The battery will be charged to the "1" level. and this state
then the third timing signal 1Y₁₆has arrived
It will be held until it comes. This hold level signal outputs an output OR gate 258.
Timing controller as read inhibit signal REG via
It is applied to the troll circuit 13F. Note that the input gate 254 of the coincidence storage circuit 248
is the key-off memory circuit 293, which will be described later.
The output detection signal D1 is applied via the inverter 259.
The key-off memory circuit 293 is keyed off.
When a channel is memorized, the corresponding channel is read out.
When the output D1 becomes “1”, the input gate
The port 254 is closed. On the other hand, the read end signal circuit 249 is the temporary storage circuit 2.
Reading data from 33 to memory circuit main body 237
Immediately close the input gate circuit 235 after
for the purpose of preventing malfunctions in the future.
It is provided. In other words, the read end signal circuit 24
9 is the storage element 2 of the delay flip-flop circuit configuration.
60, the timing control circuit 13F
When the set signal S is sent from
through the end gate 261 and further through the or gate 26
2, the master clock φ₁,φ₂Yotsu
to read and read. “1” read out at the output end
The power is passed through the return AND gate 263, and then
Input end of storage element 260 via agate 262
was returned to the world, and thus remembered by the dynamic
Ru. Such a storage state is determined by AND gate 261 and
263 via an inverter 264.
No. 16Y₁₆(The last tab corresponding to the 16th channel
Clear when the timing signal (which is the timing signal) is given.
be done. In this way, it was stored in the storage element 260.
“1” output is prohibited from reading via OR gate 258
Timing control circuit 1 as signal REG
Given to 3F. From the sample hold circuit 13B as above
Key code data to key code storage circuit main body 237
Data input operation or memory data rewriting operation
is the setting of the timing control circuit 13F.
This is carried out by the signal S and the reset signal. The timing control circuit 13F has three controls.
It has a control mode. The first control mode is key code
The new memory circuit 13C has an empty channel.
This key code is sent when new key code data arrives.
The content is to assign code data to an empty channel.
do. Below this control mode is the new key on control
It's called a mode. The second control mode is the key code storage circuit 13C.
is full (in other words, there are no empty channels)
When new key code data arrives in
Key code data of keys that have already been released is memorized.
The stored data for the channel being
The sound generated based on the sound is about to disappear
When new storage data for the channel arrives
The content is to be replaced with the key code data
do. This control mode is described below as a truncated control mode.
It is called a code. The third control mode is already activated when the key is released.
Key code data for the sounds involved in the process
For channels that remember
When the amplitude of the waveform part of A becomes below a predetermined value,
The content is to reset Yannel's memory state.
do. Reset this control mode below to control mode
That's what it means. To obtain the control signal for the new key-on control mode.
Therefore, the timing control circuit 13F is
Has AND circuit 271 for key-on control mode
Ru. This AND circuit 271 receives the first input condition signal.
as output for key code storage circuit 13C.
Inputs the busy signal A1 sent from the port 239.
a second input condition signal received via converter 272;
as the read prohibition signal REG of the read prohibition circuit 247
is received via the inverter 273, and the third input condition is
The key code of the key code detection circuit 244 is used as a signal.
Receives the code arrival confirmation output DEQ. Thus the and times for new key on control mode
Road 271 is a new key code signal KC.
When held by pull-hold circuit 13B
(The output of the OR circuit 245 becomes "1"), reading prohibited
The read inhibit signal REG is sent from the stop circuit 247.
(i.e. key code notation).
One circulation of the memory code data in the memory circuit 13C
During the operation, a match is obtained from the key code comparison circuit 240.
), key code memory circuit
Busy signal A1 is output from output gate 239 of 13C.
At the timing when it does not occur (empty channel is memorized)
We have shifted to the final stage of road main body 237.
), it sends out an output of "1". this news
“1” of AND circuit 271 for key-on control mode
The output is through the OR gate 247 for outputting the set signal.
Input AND gate of key code storage circuit 13C
235 as an open control signal, and
Further, via the set signal output OR gate 275,
And gate for feedback via inverter 276
238 as a close control signal. Thus, input AND gate 235 opens and returns.
The return AND gate 238 is closed and the slave
It is located at the final stage of the memory circuit main body 237.
The content of the channel you are using is displayed in the return
gate 238 and temporary storage circuit 233
All the memory contents are transferred to the first stage of the memory circuit body 237.
Load onto the stage. However, in this way, once the set signal is output
A set signal S is sent from the gate 274 and stored.
Inputting new data to the first stage of the circuit body 237
When reading is completed, the reading end signal circuit 249 is set.
, and therefore the data to the memory circuit main body 237 is
When the data reading is completed, the read inhibit signal REG is activated.
The new key on control amplifier is generated by
The output of the code circuit 271 becomes “0”, which causes
AND gate for input of key code storage circuit 13C
235 is closed and the return AND gate 238 is closed.
Open and prepare for the arrival of the next channel. Thus
The memory circuit main body 237 stores the newly arrived key code.
The data is assigned to an empty channel and stored.
Ru. Next, the timing control circuit 13F
In order to obtain the timing signal in the control mode,
AND circuit 277 for truncate control mode
have This AND circuit 277 meets the first input condition.
Sent as a signal from the truncate circuit 13G
The second input receives the truncate signal MTCH
The read inhibit signal of the read inhibit circuit 247 is used as a condition signal.
REG is received via the inverter 273, and the third
key code detection circuit 244 as an input condition signal.
Receives key code arrival confirmation output DEQ. Here, the truncate circuit 13G is written as a key code.
The storage capacity of the storage circuit 13C (i.e. the number of channels)
16) The above number of key code signals KC have arrived.
When the newly arrived key code signal KC is
Memorizes the key code data of the sound that is almost disappearing.
Change to the current channel and memorize it, then hide it.
Reliably memorizes newly arrived key code data
It is designed to make it possible. Truncate circuit 13G is a minimum value storage comparison circuit
280 and from the envelope generator described below.
Master clock φ₁,φ₂sequentially on a time-sharing basis in synchronization with
Envelope messages for each incoming channel
The values E of the number ΣKA are compared sequentially, and the value of the smaller value is selected.
Store envelope signal ΣKA as minimum value Q
The newly arriving envelope signal ΣKA
When the value E of is smaller than the minimum memory value Q (i.e.
when E<Q), minimum value detection signal Z of logic “1”
is sent out via the output AND gate 281. This AND gate 281 has a key operation discrimination circuit.
The key-off detection signal D1 generated at 13E is opened.
is given as a control signal, and thus the released key
The data of the channel to which the key code of
Memory circuit main body 2 of the key code memory circuit 13C
At the timing when it is read from 37, the envelope
When the curve value E is smaller than the minimum value Q, the minimum value detection signal
No. Z is sent out. This minimum value detection signal Z is sent to the minimum value storage comparison circuit 2.
80 is given to the fetch command terminal FETCH, and this
The circuit 280 receives the currently arriving envelope signal.
The contents of No. ΣKA are stored and updated as the minimum value Q, and
keys stored in channels 1 to 16.
– the smallest envelope of the notes corresponding to the chord
The value is always remembered. The minimum value detection signal Z of “1” is the minimum envelope
The value is stored in the value channel storage circuit 282. this
The memory circuit 282 is the same as the memory circuit main body 237 described above.
Similar to shift registers RG1 to RG7, the master
Clockφ₁,φ₂Read and read operations
It consists of a 16-stage shift register.
Then, the “1” output of the final stage is used as the output andgame.
The truncate signal MTCH and
and send it. This output AND gate 283 has an open control signal.
Noage receives the output of the 1st to 15th stages as
output of port 284 is provided, thus
The content of 15 stages is “0” (i.e. 1st to 15th
Channel key code memorized on stage
The envelope of the sound corresponding to the note is not at its minimum value.
), in other words, the 16th stage
Truncate signal when only memory of ji is “1”
MTCH is output through AND gate 283.
For AND circuit 277 for rank control mode
give it. Therefore, AND circuit 2 for truncate control mode
77 indicates that the new key code data is sample home.
Reading is prohibited when held by the hold circuit 13B.
The read inhibit signal REG is sent from the circuit 247.
Truncate signal, provided that it is not
Outputs “1” at the timing when MTCH arrives
This is sent through the OR gate 274 for setting.
and game for inputting key code storage circuit 13C.
235 to open it and the reset option.
Through the agate 275, and further through the inverter 276
This is given to the feedback AND gate 238 via
Close. Therefore, the truncate signal MTCH is generated.
Channel contents (currently stored in the 16th stage)
) is the next master clock φ₁,φ₂Yo
The smallest envelope key ever stored.
- Stored in the temporary storage circuit 233 from the code data
will be replaced with the new key code data.
and stored in the first stage. Used as an output condition for the minimum value storage comparison circuit 280
The key-off detection signal D1 is used to determine key operation.
Generated in circuit 13E. The key operation determination circuit 13E is configured to detect the first and second keys.
switch key-on memory circuits 291 and 292;
It has a key-off memory circuit 293. these records
Memory circuits 291, 292 and 293 are the memory circuits described above.
Similarly to the circuit body 237, the master clock φ₁,φ₂
16-stage shift lever that operates by
The memory contents of each channel are
Through return and gates 294, 295, 296
and thus preserve memory dynamically.
It is designed so that The first key switch key-on memory circuit 291 is
Key code arrived at sample hold circuit 13B
Press the key to memorize the channel to which the data is assigned.
It is provided for the purpose of holding while being operated.
Ru. However, key code memory when a key is pressed
As a response operation of circuit 13C, a new key code is
The content that matches the content of the code data has already been memorized.
In the first case where there is a channel with
There is a second case where there is no channel, and the first case
Update the memory contents of the channel with the matching contents.
In contrast, in the second case, the empty channel is not updated.
Store new data in the memory (or if it is full,
Minimum envelope with truncate control mode
channel data). In either case, are the keys being operated?
So press the corresponding channel
Must memorize the “1” signal indicating that it is inside.
Must be. Therefore, the first key switch key-on memory circuit 2
91 is Timing control circuit 13F key code
Data channel assignment to memory circuit 13C
The key-on data is synchronized with the corresponding channel.
memorize it at the location. That is, the memory circuit 291 firstly controls timing.
OR for set signal output of control circuit 13F
Input set signal S of gate 274 to OR gate 2
Receive via 97. Thus the newly arrived De
If data is to be stored in an empty channel, the channel
new data to old data in channel or truncate mode.
If data is replaced, logic is added to that channel.
A "1" signal is stored. The memory circuit 291 also has a second timing controller.
First key switch memory of troll circuit 13F
Input the output of the AND circuit 298 to the OR gate 29
Receive via 7. However, this AND circuit 29
8 is the OR gate 24 of the key code detection circuit 244
5 output DEQ and matching channel storage circuit 24
1 match memory output EQ and new key code decoding.
Channels with memory contents that match the data are memorized.
When returned to the first stage of the circuit body 237
In synchronization with this, a logic "1" signal is sent to the memory circuit 291.
Read and memorize. Here, the first key switch key-on memory circuit 29
1 feedback AND gate 294 has a timing controller.
AND circuit 29 for clearing control circuit 13F
The output of 9 is given via the inverter 300.
Ru. This clear AND circuit 299 has a key off
A detection timing signal
When the number X becomes "1", all of the memory circuit 291
Try to clear the memory of the channel.
It is. In this way, the memory circuit 291 receives the signal X when it arrives.
Keyco assigned to channels 1 to 16
check whether the key of the card is still pressed or not.
It will be checked intermittently. The second key switch key-on memory circuit 292 is
1st to 16th channels of key code storage circuit 13C
If the key code data is stored in the
The second key switch of the key corresponding to the key code
The ON operating state of K2 (FIG. 3) is memorized. deer
The records of the first to sixteenth channels of the memory circuit 292 are
The memory contents are master clock φ₁,φ₂One in 16 cycles of
The data read from the output terminal at this time is
as the second key switch on operation signal TK2.
Send from output terminal WTK2. The input of the storage signal to the storage circuit 292 is based on timing.
2nd key switch of control circuit 13F
- Input the output of the ON memory AND circuit 301 or
This is done by inputting through gate 302.
This AND circuit 301 comes from the key coder 12.
The second key switch operation detection signal KA2 and the second key switch operation detection signal KA2
The input condition is the output EQ of the matching channel storage circuit 241.
As a matter of fact, the sample and hold circuit 13B receives
key code data and key code memory circuit body
Memories of any of the 237 channels
When the data matches, the second key switch operates.
Sends "1" output when detection signal KA2 arrives
Ru. Therefore, the memory circuit 292 is a key code memory circuit.
Incoming data from channels 1 to 16 of 13C
The channel that stores the same data as
When you returned to the first stage of the road main body 237,
At that timing, the "1" signal is memorized, and thus
The second key switch K2 turns on and then turns off.
``1'' button for this operation key until
Memorize the number dynamically. Note that the memory circuit 29
The timing controller is installed in the feedback AND gate 295 of 2.
If the reset signal of the control circuit 13F is given
It will be done. However, as mentioned above, the sample hold cycle
The key code data arriving at path 13B is
formed by the operation of key switch K1.
On the other hand, the detection signal KA2 is from the second key switch K.
2. hence the key code
New key code data is stored in the memory circuit 13C.
Regarding this memory channel by being
“1” output was sent to output terminal WTK1
is the point at which the first key switch K1 turns on.
In contrast, the output of the storage circuit 292
The fact that “1” output is sent to terminal WTK2 means that
Indicates the moment when key switch K2 of No. 2 is turned on.
are doing. Therefore, the signal TK is applied to the output terminal WTK1.
From the moment when 1 is sent, a signal is sent to output terminal WTK2.
The time between the times when No. TK2 was sent corresponds to
Corresponds to the speed at which the key is pressed
It will be the size that it will be. Thus, the speed of key operation is
Channel the data to be processed using signals TK1 and TK2.
This means that the data can be sent from the file processor 13. The key-off memory circuit 293 is a key code memory circuit.
Key code stored in each channel of 13C
The key corresponding to the code is released and the key code is the same as that key code.
The key code is not output from the key coder 12.
When the key is turned off (that is, when the key is turned off)
i) Memorize that channel. The key-off memory circuit 293 is the first key switch described above.
Timing based on the output of the Tsuchi memory circuit 291
The controller formed in the control circuit 13F
Memory operation is performed by the troll signal. In other words,
Timing control circuit 13F has key-off memory
It has a control AND circuit 305, and its first input
As a signal, the first key switch key-on memory circuit 2
91 output TA1 is received via the inverter 306.
and the key code storage circuit 1 as the second input signal.
3C busy signal A1 is received, and the third input signal and
and the step control of the key coder 12 mentioned above.
Key-off detection timing signal X of the key-off circuit 12E
receive. Therefore, the AND circuit 305 for key-off memory control is
When key-off detection timing signal X arrives
In this case, the first key switch memory circuit 291
A channel for which a “1” signal is not stored is input.
When it is fed back to the end (at this time, the memory output TA1 is
0), indicating that the busy signal A1 has arrived.
Sends a “1” signal on the condition that
The input OR gate 308 to the OFF storage circuit 293
be memorized via . In this way, the key-off memory circuit 293
Every time the timing signal X arrives, the memory circuit main body 2
About 37 channels that are not empty channels
The key corresponding to the key code has been released.
You will have to check and remember whether it is true or not. Note that the memory in the key-off memory circuit 293 is based on timing.
The reset signal R is sent from the control circuit 13F.
Each time it is sent out, it is
and is given to the feedback AND gate 296.
Cleared by Record of each channel of key code storage circuit 13C
Memories are separated from the sound of the key code, which is the content.
A tie occurs when the decay waveform part attenuates completely after key operation.
AND for clearing the timing control circuit 13F
Cleared by the output of circuit 309. The clear AND circuit 309 has the first condition
As a signal, in musical tone signal forming sections 7A and 7B
The generated decay end signal 2DF is given,
In addition, a key-off memory circuit 29 is used as a second condition signal.
3 key-off detection signal D1 is given, and its logic
The “1” output is passed through the reset gate 275.
Furthermore, the key code is stored via the inverter 276.
Close the return AND gate 238 on path 13C. However, the DAYK end signal 2DF is the key code.
Currently exists in the 16th stage of memory circuit 13C
Regarding the sound of the key code stored in the channel.
This chip detects the end of day-K.
It is no longer possible to return data about Jannel.
and eventually be cleared for that channel.
It becomes. Thus, this channel is the so-called sky
Waiting for the next data allocation as a channel
becomes. In the above manner, the channel processor 13
is a plurality of keys sequentially sent from the key coder 12.
- Chord data, if necessary for simultaneous pronunciation.
~When assigned and memorized to any of the 16th channels
The content of each channel (i.e. simultaneous pronunciation)
(key codes for multiple sounds) are multiplexed in a time-sharing manner.
Output terminals WN1 to WB3 as converted information signals
Output from. However, the contents of this output information signal are shown in Figure 2.
The key information about the key code is IFK.
Ru. The first information is key code information KC,
From the memory circuit body 237 of the code memory circuit 13C
Obtained note code NOTE and block code
It becomes OCT. Also, the second information is the key switch operation.
With the operation information, the output OR of the key code storage circuit 13C
First key switch K1 obtained from gate 239
The key-on detection signal TK1 and the second key
The first value obtained from the switch key-on memory circuit 292
Key-on detection signal for 2-key switch K2
It comes with TK2. The third information indicates the key-off status.
With the key-off information, the key-off memory circuit 293
It consists of the key-off detection signal TDO obtained from the key-off detection signal TDO. These key information are as shown in Figure 1.
and second series parameter generation circuits 5A and 5B.
In addition to being sent as a parameter generation signal, the key
Information regarding key press operations, so-called touch information
In order to form the IFT, the initial control
control circuit 14 and aftertouch control circuit
15 (Figure 2). (1-4) Initial control circuit The initial control circuit 14 controls key press operations.
Determine the depressing speed that is decreasing during the attack, and
Variable T related to amplitude in equation (2) mentioned above_oi
(t) and T_oaTo generate the control constant of (t)
It is provided for the purpose of generating a condition signal, and the timekeeping logic
It has a circuit 14A and a conversion circuit 14B (second
figure). The timing logic circuit 14A detects when a key is pressed.
After the first key switch K1 is turned on, the second
The time it takes for key switch K2 to turn on,
Simultaneously stored in channel processor 13
Measures and stores the time corresponding to the channel of each generated sound.
As shown in Figure 8, the timekeeping clock is
The clock oscillator 311, the adder 312, and the operating time
and a calculation storage circuit 313. The operating time calculation memory circuit 313 has a 16-stage system.
6-bit 16-stage with 6 rows of shift registers
It has a shift register configuration, and the master clock
φ₁,φ₂All bits of the shift register are unified by
They are designed to shift in unison. here
The number of stages of the shift register was set to 16 stages.
are the first to the first channels of the channel processor 13 mentioned above.
It is determined corresponding to 16 channels, thus the channel
The channel processor 13 processes the 1st to 16th channels.
Each time key information IFK is sent, it is
Calculate the key press speed for the corresponding channel key.
It is designed to be memorized. In other words, the input side of the operating time calculation storage circuit 313
is provided with a 6-bit adder 312, each of which
The outputs of the bits pass through the input AND gates 314 respectively.
It is applied to each bit register of the memory circuit 313 through
available. Adder 312 operates a half adder for each bit.
Clock oscillator 3 for time measurement, provided as an addition element
“1” addition input 1AD given from 11 and
By adding the output of the 16th stage of the storage circuit 313,
to be read into the first stage of the memory circuit 313.
is being done. However, there is no input in the path of "1" addition input 1AD.
An AND gate 315 is provided to control its opening and closing operation.
Controlled by the output of the AND circuit 316 for starting calculations
do. In other words, the AND circuit 316 is a channel loop.
It arrives from the processor 13 in the form of a time division multiplexed signal.
1st key switch for channels 1 to 16
The key-on detection signal TK1 is used as the first condition signal.
and receive a similar second signal as a second condition signal.
Invert key switch key-on detection signal TK2
317. Therefore, the amplifier for starting calculation is
The code circuit 316 outputs the first signal for each channel of information.
Key switch K1 turns on and key-on is detected.
When signal TK1 becomes “1” (at this time, the second key
-Switch K2 is not turned on yet, so please turn it on.
– ON detection signal TK2 is “0”), logic
The output of "1" is used as an open control signal for AND gate 3
15 and then the second key switch K2 turns on.
key-on detection signal TK2 becomes “1”.
The AND gate 315 is controlled to open until the
Ru. Therefore, when adding "1" to the time measurement clock oscillator 311,
The calculation signal 1AD is given to the adder 312. On the other hand, at this time, the adder 312 and operation time calculation record
AND gate 314 provided between storage circuits 313
The key-on detection signal TK1 is used as the open control signal.
Therefore, the adder 312 corresponds to the 1st to 16th channels.
Is the channel key information channel processor 13?
The storage circuit synchronizes with this data every time it is transferred.
Add “1” to the memory contents of 313 and memorize it again
The operation of storing the information in the path 313 is repeated. This result record
The storage circuit 313 has the first key switch K1 turned on.
After turning on the second key switch K2 turns on.
The time from the first to the first in the memory circuit 313
Expressed as the number of 16-channel circular motion cycles.
The calculation will be memorized. The calculation result (key-on signal TK2 has arrived)
(the result at the time becomes the measurement result) is the memory circuit 313
Binary evolution from the 16th stage of each bit register of
To output terminals U1 to U32 as code signal IND
Sent out. By the way, the second key switch K2 turns on.
Then, the key-on detection signal TK2 changes from “0” to
By changing to "1", the AND gate 316 is
closed, so the “1” addition signal 1AD is the adder 31
2 will no longer be given. Therefore, the adder 312
No addition is made to the data arriving from the storage circuit 313.
is sent to the output terminal as it is, and thus the memory circuit
The data in 313 is passed through the adder 312 and then to the adder 312.
dynamically stored via the command gate 314.
This stored data continues to the output terminals U1 to U32.
It will be sent out. This operation is performed after the keys are released and the keys are pressed one after another.
On detection signals TK2 and TK1 go from “1” to “0”
This continues until the signal TK1 returns to "0".
When the gate 314 closes, the memory circuit 3
The memory of all 13 bits becomes “0” and the
Therefore, the output of output terminals U1 to U32 becomes "0".
It will end with this. In this embodiment, the output of the memory circuit 313 is
is applied to the NAND circuit 318, thus storing the memory circuit
The contents of all 313 bits became "1"
When we get a “0” output, we apply this to the AND gate 316
is given as a closed signal, and thus recorded.
Memory circuit 313 slows beyond the range that can be measured.
If the key is pressed again, the maximum timekeeping output will be reached.
It is designed to be retained after that time.
Ru. In this way, the operation time calculation memory circuit 313 sends out
The time measurement output is sent to the code conversion circuit (ROM) 14.
This code is given to B, which makes it easier to process later.
Initial touch data ITD
and then sent out. (1-5) Aftertouch control circuit Aftertouch control circuit 15 is key press operation
The pressing strength is determined when
The variables Tni(t) and T_oa(t)
Generates a condition signal to generate the control constant of
The multiplexer 15A and its
A/D converter 15B receives the output of
Figure 2). As shown in FIG. 9, the multiplexer 15A is
Channel processor 13 key code KC (no
Consists of block code NOTE and block code OCT
and this is provided for all keys.
Line output g to the corresponding one of the 88 output lines
1 to g88 (the logic level of that output line is “1”)
a decoder that converts to
321, and its line output g1 to g88 can be controlled by key operation.
In the operation detection circuit 11, each key is
Pressure pressure detectors DT1 to DT88 provided
Gate G receiving outputs dt1 to dt88 of (Figure 9)
Give it as an open control signal to 1 to G88.
It is. However, the key code KC is 16 characters as mentioned above.
Contains time-division multiplexed data for multiple channels.
Therefore, the decoder 321 inputs each channel of the key code KC.
Each time channel data arrives, gates G1 to G
Switch the gate of the corresponding key out of 88 in sequence.
and thus each channel's arrival
Key press pressure detection output corresponding to dt1 to dt88
are sampled sequentially and sent to the output terminal VDT.
will be done. This output signal is an analog value, but this
It is converted into a digital signal by the A/D converter 15B in the second stage.
After that, it is sent as after-touch data ATD.
It will be done. In this way, the aftertouch control circuit
Aftertouch control device formed in step 15
The data ATD is the initial control circuit described above.
Initial control data formed at path 14
Touch information output from keyboard information generator 1 along with data ITD.
The power is sent out as IFT. [2] First and second series parameter generation circuit First and second series parameter generation circuit 5A and
5B is a constant required when calculating equation (3)
The signals are time-division multiplexed in the keyboard information generating section 1.
The key codes of the 1st to 16th channels generated by the expression
This occurs sequentially each time a KC arrives, and the
Key code KC and tone selection as shown in Figure 10
Controlled by both tone selection signal VSS of switch 6.
The first constant generation circuit 325 of the controlled ROM configuration
and 326, and the tone selection signal of the tone selection switch 6.
The second ROM configuration is controlled only by the VSS.
It consists of constant generation circuits 327 and 328. First series (or second series) parameter generation circuit
5A (or 5B) first constant generation circuit 325 or
326 is the overall sound of the first series (or second series)
The total volume constant K that determines the amount₁or K₂occurs. Second, the timbre change that determines the temporal change in timbre in equation (3) is
Number I₁(t) (or I₂(t))
A constant, that is, an initial sound that determines the tone at the beginning of the sound.
color constant IL₁(or IL₂) to determine the temporal change in timbre.
Tone change constant DR_I1(or DR_I2) and D.K.
Tone change stop level constant that determines the end level of
SL_I1(or SL_I2) and occur. Third, the amplitude for determining the envelope of equation (3)
level or envelope variable A₁(t) or A₂
The constant necessary to calculate (t), that is,
Attack rate constant AR that determines attack speed_A1or
AR_A2and the first deke that determines the first deke speed.
i rate constant 1DR_A1or 1DR_A2and the second day rate
The second decay rate constant 2DR that determines the degree_A1or
2DR_A2and the decay rate constant that determines the decay rate after key release.
Number DR_A1or DR_A2and from the first decay speed to the second
Decay transition that determines the level to move to Decay speed
Level constant 1DL_A1Or 1DL_A2and occurs. Also, the first series (or second series) parameter generation
Second constant generation circuit 327 of circuit 5A or 5B or
328 is the pitch constant that determines the frequency of the generated sound.
B₁Or B₂secondly, partials (harmonics and
Partial constants that determine the composition of components (including nonharmonic tones)
D₁or D₂occurs. Third, determine the volume according to key touch operations
Constant T for volume selection_1a(t) or T_2acalculate (t)
The constants necessary to
The initial constant βi (or δi) that responds to
The after constant βa (or δa) that responds to the touch is
Occur. Fourth, determine the tone depending on the key touch operation.
Tone selection constant T/i(t) or T_2iCalculate (t)
The constants needed to do this, i.e. the initial
Initial constant α that responds to_iOr γi and after
After constant α that responds to touch_aor γ_aand generate
Ru. [3] Tone selection switch circuit The timbre selection switch circuit 6 selects the tone to be added to the generated musical tone.
generates a timbre selection signal VSS for the timbre;
This is the first and second series parameter generation circuit 5A.
and 5B, the configuration shown in FIG.
can be applied. In other words, there are selectable tones, such as piano,
- psichord, vibrafon... Compatible with xylophone
Then, normally closed contact b and normally open contact a and their corresponding
Tone selection switch CH1 consisting of movable contact c,
CH2, CH3...CHn are provided. deer
These switches CH1, CH2, CH3...
CH_oThe movable contact c and the normally closed contact b are connected in series.
That switch CH_oThe side edge is at logic “1” level.
Connected to the power supply, each switch is connected to the normally open contact a of each switch.
Tone selection output VSS1, VSS2, VSS3...
VSS_oIt is designed to send out. Thus, switches CH1, CH2, CH3...
CH_oSelected output VSS1, VSS2, VSS...VSS_o
has the reverse order of priority, and multiple
The highest priority is also given when a switch selection operation is performed.
Only one tone selection output with a high ranking will be sent.
It is being done. [4] First and second series musical tone signal forming section First and second series musical tone signal forming sections 7A and 7B
are the calculations of the first and second terms of equation (3), respectively.
, key information IFK and touch of keyboard information generating section 1
Information IFT and first and second series parameter generation times
constant output of paths 5A and 5B and damper pedal 9.
and the output (FIG. 1). First and second series musical tone signal forming sections 7A and 7B
have exactly the same configuration. Therefore, in this specification
Detailed structure of the first series musical tone signal forming section 7A
Describe the composition. The first series musical tone signal forming section 7A is shown in FIG.
As shown in B, perform the calculation of the amplitude term part of equation (3).
The amplitude term calculation circuit 331 and the carrier wave term part of equation (3)
a carrier term calculation circuit 332 that executes the calculation of
A modulating wave term operator that performs the calculation of the modulating wave term part of equation (3).
It has a calculation circuit 333. (4-1) Carrier term calculation circuit The carrier wave term calculation circuit 332 is a channel processor.
It comes from the key code storage circuit 13C of Tsusa 13.
Of the key code KC, select the note code NOTE.
This is received by the frequency converter 334 of ROM configuration.
is the frequency of the reference note (note of the reference octave)
Convert to the binary equivalent of the number. The output of this conversion is
is provided to shifter 336 through adder 335.
Ru. This shifter 336 comes from converter 334
Enter the value corresponding to the reference note name note in the key code KC.
OCT assigned to the included block code OCT
Shuffle upward or downward by the amount corresponding to the cube number.
and thus the pressed key is placed at the output end.
A frequency output consisting of a binary value proportional to the pitch frequency of
Send out force FS. On the other hand, the adder 335 has a block code OCT.
The output of the tuning curve simulating constant generation circuit 337
Power is given. This constant generation circuit 337 is the same
Even if it is a note name, a high octave note is a low octave note.
It is necessary to tune to a slightly higher frequency than that of the cube.
Designed to satisfy this need.
Assigned to the incoming block code OCT
The tuning output corresponding to the octave number
It is sent as a decimal value and sent to the adder 335.
by adding it to the frequency output of converter 334.
and obtain a tuning effect. The output of shifter 336 is sent to accumulator 338.
Given. This accumulator 338 is a shifter.
336 output as master clock φ₁,φ₂given
Repeatedly add each time the
Now sends an output pulse when a low occurs.
has been done. However, the output of shifter 336 is as described above.
is proportional to the pitch frequency of the operated key.
Since the size is large, the addition of the accumulator 338 is
The rate of increase in the calculation content increases as the pitch frequency increases.
As a result, the output terminal of the accumulator 338 receives a high frequency sound.
An output ωt with a frequency proportional to the wave number is transmitted.
It becomes. In this way, the number of laps sent out by the accumulator 338 is
The wave number output ωt is sent to the multiplication circuit 339 (Fig. 12B).
given, where the first series parameter generation circuit 5
Pitch constant coming from the second constant generating circuit 327 of A
Number B₁The output B of this multiplier circuit 339 is multiplied by
1・ωt is the calculation output of the carrier term part of equation (3).
Sent out. However, this calculation output B1・ωt is obtained by key press operation.
It will have the pitch frequency of the key. (4-2) Modulation wave term calculation circuit The modulation wave crest calculation circuit 333 obtains the modulation wave term of equation (3).
It has a sin function generation circuit 341 with a ROM configuration,
Frequency output ωt of the carrier term calculation circuit 332 described above
The first series parameter is generated in the multiplication circuit 342.
It comes from the second constant generation circuit 327 of the raw circuit 5A.
partial constant D₁Multiplying with sine function generation circuit 34
1 and thus the modulating wave frequency at the output end.
Sine wave output sin D with D1・ωt₁・Send ωt,
This sine wave output sin D₁・ωt to the multiplication circuit 343
given constant T_1i(t)・I₁(t)・sinD₁・ωt is modulated wave
It is sent out as the calculation output of the term calculation circuit 333. Here, the constant T input to the multiplication circuit 343_1i
(t)・I₁(t) is a timbre function as shown in Figure 13.
It is formed based on the output of generation circuit 344. This timbre function generation circuit 344 is according to the present invention.
It is one of the function waveform generators, and it produces basic tones.
Something that generates the timbre waveform that determines the time change of
In this example, the base is
Generates the output of the actual tone waveform. In other words, the waveform output
The force VW is the second key switch operation detection signal TK2.
At the time of arrival (time t₁₁) becomes the maximum value MAX, and then
Decrease linearly or curved (e.g. exponentially)
Lower, level SL_Iretains that value after it reaches
It's been like that. In addition to this, the waveform output VW is
Descent part W₁₁point in time t₁₂When the key is released with
From then on, the value at that time is maintained. Naokaka
In the waveform output VW, the falling period is M11.
Let the period be M12. Such a waveform is formed by the configuration shown in FIG.
Ru. In other words, the timbre function generation circuit 344 generates a linear descending wave.
A linear calculation circuit 345 for forming a shape and a curve
a curve calculation circuit 346 for forming a falling waveform;
The linear arithmetic circuit 345 performs the subtraction operation as a basic operation.
The curve calculation circuit 346 performs the addition operation as a basic operation.
It is a work of art. The linear calculation circuit 345 is the channel processor 1
16 channels of key code KC coming from 3
16-stage shift register corresponding to 6-bit
It has a memory circuit 347 provided in parallel for
Master each stage of these six shift registers.
Lockφ₁,φ₂Read and read operations by
By doing so, the 1st to 16th channels of key code KC
The memory circuit 347 is synchronized with the shift operation of the channel.
Shift the contents and output the 16th stage output
Send as tone reference signal VOC to terminals Y1 to Y32.
put out However, the memory circuit 347 stores all the bits.
An input OR gate 348 is provided for
Set signal XX of logic “1” to all bits through
The first output of the memory circuit 347 is
All bits in the channel that exists in the stage
Read the data of “1” into. all these bits
The channel that memorized the “1” signal is the 16th stage
This is the time t in FIG.₁₁
As the maximum value MAX of the timbre reference signal VOC at
It is sent to terminals Y1 to Y32. The set signal XX is sent to the set signal forming circuit 349.
and comes from the channel processor 13.
Based on the second key switch key-on detection signal TK2
It is formed by In other words, two detection signals TK2 are input.
is given to the power AND circuit 350 as one condition signal.
and a subtraction signal control circuit 351 to be described later.
The subtraction signal M1/M2 is passed through the inverter 352.
and is given as the other condition signal. subtract here
As described later, the signal M1/M2 has a waveform output VW.
Logic when in descending section M11 (Fig. 14)
The section M12 is less than “1”
(that is, when the waveform output VW is in a certain range)
The logic becomes "0". Then press the second key switch key.
Subtraction before on-detection signal TK2 arrives
Since the signal M1/M2 is "0", the AND circuit 35
Channel where detection signal TK2 becomes “1” at 0
arrives, the output of the AND circuit 350 becomes "1".
This is sent as set signals XX, YY.
It will be done. Therefore, as mentioned above, all of the memory circuits 347
A “1” signal is set for the bit, but
Once the “1” output is sent from the AND circuit 350,
When the signal is output, the subtraction signal M1/M2 is generated as described later.
From the AND circuit 350 by becoming "1"
It becomes impossible to send a "1" output. On the input side of the memory circuit 347 is a calculation means 6.
An addition circuit 353 having a stage full adder configuration is provided,
It is recorded as the first addition input of each stage of the addition circuit 353.
When each bit output of the storage circuit 347 is given,
As the second addition input of each stage of the addition circuit 353,
“1” input ADD with period controlled by₁But and game
All stages are given at once from gate 354, thus adding
In the arithmetic circuit 353, each channel of the memory circuit 347
Subtract the value "1" from the contents of the channel. This subtraction calculation
The power is transmitted to the memory circuit 347 via the OR gate 348.
Read in the first stage. Here, given from the AND gate 354
"1" input ADD₁The rising width of the memory circuit 347
The master clock φ used to shift₁，
φ₂is preselected to a length of 16 cycles and follows
Which channels from channels 1 to 16 are added?
Subtraction operation is performed uniformly even if it is read out to the circuit 353.
It is made possible to do so. In this way, the calculation contents of the memory circuit 347 are as follows:
And every time it is read from the 16th stage,
“1” input ADD from gate 345₁is coming
With the condition that "1" is subtracted, and conversely
If it has not arrived, no subtraction will be made and it will remain as is.
The data is read into the memory circuit 347. Therefore, memory circuit 3
The subtraction speed of the contents of 47 is AND gate 354?
“1” input ADD given by₁frequency of arrival, exchange
In other words, it depends on the cycle. The output of the AND gate 354 is the square wave oscillator 35
5, and its repetition period is programmed.
The change was controlled by the marble divider 356.
After that, it is sent out through AND gate 354. However, the programmable divider 356 has a
1st constant generation time of 1 series parameter generation circuit 5A
timbre change constant DR generated in path 325_I1
is given, and the oscillator 3 is set to a magnitude corresponding to that value.
Change the output cycle of 55. But this tone
Change constant DR_I1is selected by tone selection switch 6.
to the selected tone and the key indicated by the key code KC.
Therefore, in the end, the linear calculation time is
The subtraction speed of path 345, and therefore the reference tone waveform VW.
Tone with descending slope selected and key operated
It will be determined depending on the location. In other words, the rectangle
Shape wave oscillator 355 and programmable diver
Ida 356 is based on the output of constant generation circuit 325.
an operator that controls the calculation timing of the adder circuit 353.
It constitutes a computational control means, and from another point of view it is a constant
Generation circuit 325, square wave oscillator 355, program
Mable divider 356 is key code information Kc
Therefore, it constitutes one operational control means.
Ru. On the other hand, the AND gate 354 receives its open control signal.
Then, the output M1/M2 of the subtraction signal control circuit 351 is
Given. This subtraction signal control circuit 351 is as described above.
A 16-stage circuit similar to that used in the memory circuit 347 of
It has a shift register 358 and receives the above-mentioned set signal.
From the formation circuit 349 through the input OR gate 359
Set signal for specifying a subtraction channel with logic “1”
When issue YY arrived, this was actually the first stage.
It is stored in the channel that exists in the eyes. However,
The channel that stores this "1" signal is the 16th channel.
When reaching the stage, subtract this command signal M1/
M2 to the AND gate 354, so that the
The time during which the output of the binder 356 is generated (master
The period corresponding to 16 clock cycles), the corresponding “1” signal
of the channel whose number was read from register 358.
Only during the interval (an interval of one master clock cycle)
AND gate 354 is opened, and at this time, memory circuit 3
Chiyanne being read out on the 16th stage of 47
"1" is subtracted from the contents of the file.
There is. This AND gate 354 also calculates the function waveform value when
As a calculation control means for the calculation means that performs divided calculations.
It works. Shift register 35 of subtraction signal control circuit 351
8 “1” signal is stored in the feedback AND gate 36
0 and further circulates through or gate 359
be done. Therefore, the subtraction command signal M1/
M2 was generated and the "1" signal was memorized.
The channel data subtraction operation is repeated and this
This causes the corresponding channel to be output to the output terminal of the linear calculation circuit 345.
(in other words, the sound of the key being pressed is
a wave that descends in a straight line from the applied channel)
You can get the shaped output VOC. Storage of “1” signal of subtraction signal control circuit 351
To clear, close the return AND gate 360
There are two cases: The first is the timbre reference waveform VW (Figure 14).
falling waveform part W₁₁is the planned level SL_Idown to
Therefore, the output of the linear calculation circuit 345
power is applied to the comparator circuit 361 as one comparison input B.
available. On the other hand, the comparison circuit 361 has the other side.
The first series parameter generation circuit is used as the comparison input A of
Tone change stops from 5A first constant generation circuit 325
level constant SL_I1is given and satisfies the condition A>B
(In other words, when the falling waveform part W₁₁is selected
Level SL determined by the tone_I1(when it becomes lower)
Send clear signal TDF. This clear signal
TDF is the input or gate of the subtraction signal control circuit 351.
via the port 362 and further via the inverter 363.
is given to the AND gate 360 as a close control signal.
, thus actually register 358's first stage
Clear the contents of the channel that exists in the eye to "0"
do. Therefore, from now on, the subtraction signal M
1/M2 is no longer sent, so "1" is subtracted
By closing the input AND gate 354, the
No subtraction operation is performed on the contents of the storage circuit 347.
As a result, the terminals Y1 to Y of the linear calculation circuit 345
A roll of 32 will maintain a constant value (14th
Constant waveform part W in the figure₁₂). In addition, in the case of the second clear, the tone reference waveform VW
(Fig. 14), the falling waveform part W₁₁in the middle of
point t₁₂When the key is released in
Read from the key-off memory circuit 293 of the processor 13
The key-off detection signal TDO is output to AND gate 3.
64, and an or gate 362 and an inverter.
Close control is applied to the AND gate 360 via the motor 363.
is given as a signal and thus actually register 35
Contents of channels existing in the first stage of 8
Clear to "0". Therefore, in this case as well, we do a straight line in the same way as in the above case.
The outputs of terminals Y1 to Y32 of the arithmetic circuit 345 are constant.
(constant waveform part in Figure 14)
W₁₃). That is, shift register 3
58 indicates the current formation interval (occurrence state) of the function waveform.
Functions as a storage device that stores data that represents
ORGATE 359, ANDGATE 360, comparison time
road 361, or gate 362, inverter 363
etc. updates the state data of each function waveform.
functions as a control means. However, if it is inserted in the path of the key-off detection signal TDO,
The closed control signal and the AND gate 364
Then, the damper pedal coming from damper pedal 9
Signal PO (logic “0” during operation) is connected to the inverter.
365, thus key-off detection
Damper pedal 9 was depressed when signal TDO arrived.
In this case, as described above, the subtraction signal control circuit 351
Immediately clear the memory of the channel,
Therefore, the linear calculation circuit 354 immediately interrupts the subtraction operation.
constant waveform part W of output waveform VW₁₃(Figure 14)
will be formed. The effect of the damper pedal 9 is as follows.
If the entry into Dal 9 is canceled, the
As a result, the output wave of the linear calculation circuit 345
For model VW, the waveform section starts from the moment damper pedal 9 is released.
W₁₂It will go down to. On the other hand, the curve calculation circuit 346 operates as described above.
As shown in FIG. 14, the linear calculation circuit 345 forms
Generates musical tones based on the basic timbre waveform VW.
In order to improve the points that make listening difficult when
It is set up for the purpose of That is, the basic calculation is performed only by the linear calculation circuit 345.
When forming the timbre waveform VW, use the waveform shown in Figure 14.
As is clear from the straight descending part W₁₁Followed by
Constant waveform part W₁₂Or W₁₃will occur,
The transition is always at a certain angle with sudden changes.
This sudden change is one of the reasons why it is difficult to hear.
There is. So, for example, this is close to an exponential change.
If you modify it so that it changes, it will reduce the difficulty of listening.
Wear. In order to achieve this purpose, the curve calculation of this embodiment is
The circuit 346 is the memory circuit 3 of the linear calculation circuit 345.
Except for changing the number of bits to 3 bits in 47.
A memory circuit 367 having a similar configuration and a linear performance
The number of stages in the addition circuit 353 of the calculation circuit 345 is 3.
The carry is sent from the highest bit.
Additions with the same configuration except that
and a calculation circuit 368. However, each of the 16th stages of the memory circuit 367
The bit output is connected to the corresponding stage of adder circuit 368.
The input AND gate 369 provided in each
"1" addition input ADD arriving from₁and the
The addition result is stored in the first stage of the storage circuit 367.
will be returned directly. Input address for the first to third stages of the adder circuit 368
The memory gate 369 of the linear arithmetic circuit 345
Among the outputs obtained from the circuit 347, the top 3 bits
Inverts the bit output, that is, the 4th to 6th bit outputs.
370 as a close control signal. Therefore, the storage circuit 347 of the linear calculation circuit 345
The contents are set to all bits by set signal XX.
From the state where the “1” signal is stored, the signal is decreased by “1”.
In the process of calculation, the 4th bit from the bottom
When the content of this bit becomes “0” (the content of this bit
is "1" alternately every 8 subtraction operations
or becomes “0”), the first bit of the adder circuit 368
"1" addition input ADD for₁give and hide
Add the contents of the memory circuit 367 by "001"
go. Also, the contents of the fifth bit of the memory circuit 347 are
When it becomes “0” (the contents of this bit are 16 times
Each time a subtraction operation is performed, "1" or
becomes “0”), the second bit of the adder circuit 368
and gives a "1" addition input, thus memory circuit 3
Add the contents of 67 by "010". Furthermore, the contents of the 6th bit of the memory circuit 347 are
When it becomes “0” (the contents of this bit are 32 times
Each time a subtraction operation is performed, "1" or
becomes “0”), the third bit of the adder circuit 368
Provides a "1" addition input, thus storing circuit 367
Add the contents in increments of 100. As a result of this addition operation, the third bit of the addition circuit 368
When a carry occurs in the
The "1" addition input ADD to path 345₂given as
It will be done. Note that it is given via the AND gate 369.
As a “1” addition input, it corresponds to the linear calculation circuit 345.
and the logic provided via AND gate 354
A "1" input is used. The above-mentioned curve calculation circuit 346 is the straight line calculation circuit 34.
5, it operates as follows. The memory circuit 347 of the linear calculation circuit 345
After being set to "11111111", it becomes "111000"
During the eight subtraction operations up to
The contents of the 4th to 6th bits of the output are “111”
The linear calculation circuit 345 performs the original linear subtraction operation.
execute the work. After this 8th subtraction operation, the 16th subtraction operation is performed.
Until the calculation operation is performed, the output of the memory circuit 347 is
The 6th to 4th bits are “110”, so the curve performance
The addition circuit 368 of the arithmetic circuit 346 is a memory circuit 367
Add "001" ("1" in decimal number) to the contents of
Calculate at a cycle that corresponds to the rising speed of the addition result.
Rei ADD₂Output. However, this carrier
ADD₂The timing of the output is determined by the linear calculation circuit 345.
The adder circuit 353 performs a subtraction operation of “1”.
Since this matches the timing, the adder circuit 353
subtraction input and addition circuit 3 of curve calculation circuit 346
Carry ADD from 68₂(i.e. addition input)
You will receive both at the same time. Therefore, carry
ADD₂Each time the is sent out, the linear calculation circuit 345
There will be no subtraction operation. After this 16th subtraction operation, the 24th operation
Until the operation is performed, the sixth output of the memory circuit 347 is
~Since the 4th bit is “101”, the curve calculation time is
The adder circuit 368 of the path 346 is included in the memory circuit 367.
Add "101" ("2" in decimal number) to the volume.
Carry at a cycle according to the rising speed of this addition result.
ADD₂Output. That is, the above-mentioned 8th time ~
Carry ADD twice as fast as in the 16th case₂of
I will send it out. Therefore, the linear calculation circuit 345
will thin out the subtraction operation at this frequency, and this
The falling speed of the output VOC of the linear calculation circuit 345 is
descend. In the same manner, the memory circuit of the linear calculation circuit 345 is
The 4th to 6th bits of the output of the line 347 are "100",
As “011” and so on, the curve calculation circuit 346
The addition value to the addition circuit 368 is "011", "100"...
…(in decimal notation “3”, “4”…)
I'm getting louder and I'm getting more and more ADD₂output frequency
twice the degree, 2²times...exponentially
I'm getting tired of it. Accordingly, the linear calculation circuit 34
The thinning frequency for the subtraction operation of 5 is also exponential.
becomes larger, thus the subtraction speed of the storage circuit 347,
In other words, the falling speed of the output waveform VW is exponential.
This will result in a decline in By providing the curve calculation circuit 346 in this way,
Therefore, the falling waveform part VW of the reference tone signal VOC is constant.
Waveform part W₁₂Or W₁₃There is a roundness in the sudden transition part when transitioning to
This also reduces the difficulty of listening.
Wear. In this way, the straight line of the timbre function generation circuit 344
Reference tone signal formed by arithmetic circuit 345
VOC is fed to the multiplier circuit 371 (Figure 12B).
, the first constant of the first series parameter generation circuit 5A
Constant IL coming from generation circuit 325₁is multiplied by
Variable I in equation (3)₁Obtain the output of (t). This variable output
I₁(t) is then output as a variable T by the multiplication circuit 372._1i
(t) and the variable T in equation (3)_1i(t)・I₁(t)
get. Here the variable output T_1i(t) is the keyboard information generating section 1
initial touch control circuit 14 and
The input coming from the lid touch control circuit 15
Initial attach signal ITD and after touch signal
Formed on the basis of ATD. i.e. initia
The touch signal ITD is applied to the multiplier circuit 373 (Fig. 12).
In A), the first series parameter generation circuit 5A
The initial constant α arriving from_iWhen multiplied by
Then, the aftertouch signal ATD is sent to the multiplication circuit 374.
comes from the first series parameter generation circuit 5A at
After constant α_aand the result of these multiplications is
are added in the adder 375 and the variable T_1i(t)
is applied to the multiplication circuit 372 described above. The variable T obtained in this way_1i(t) is after
The touch signal ATD is applied to the key while the performer is pressing the key.
It changes according to the change in the pressing force applied.
Therefore, it becomes a temporal variable. Output T of multiplier circuit 372_1i(t)・I₁(t) is multiplication
In the circuit 343, the output of the sin function generating circuit 341 is
force sin D₁・It is multiplied by ωt, and the multiplication result is expressed as equation (3).
The modulation wave term T_1i(t)・I₁(t)・sin D₁・Represents ωt
It is sent out as the output of the modulation term calculation circuit 333.
Ru. (4-3) Amplitude term calculation circuit The amplitude term calculation circuit 331 calculates the amplitude term K of equation (3).₁・T_1a
(t)・A₁(t) is provided to obtain Fig. 15.
As shown in FIG.
is one It has a volume function generation circuit 381. This volume function generation circuit 381 determines the volume of the generated sound.
Basic amplitude changes over time, including the envelope
The envelope wave shown in Figure 16 determines the
Generates an output AOC with type ENV. i.e.
The envelope waveform output ENV is normally
When the second key switch K2 is closed due to
2nd key switch from Jannel processor 13
Time t when the on detection signal TK2 arrives_{twenty one}from a predetermined steep
The slope rises from the lowest value MIN to the highest value MAX.
Tack waveform section ENV₁And this waveform ENV₁Followed by
The first decay waveform section descends at a relatively steep slope.
ENV₂And this waveform part ENV₂followed by a relatively slow slope.
The second stage slopes down to the minimum level MIN.
Good waveform part ENV₃It becomes. However, the second decay waveform part ENV₃In the middle of
If the pump pedal 9 is operated, at the time of the operation
point t_{twenty four}descends steeply from to the minimum level MIN
dump slope section ENV_Fouris formed. The volume function generating circuit 381 is an engine shown in FIG.
The following configuration is used to obtain the envelope waveform output AOC. That is, the timbre function described above with respect to FIG.
Linear calculation circuit 345 of generation circuit 344, curve calculation
circuit 346, programmable divider 356, ratio
A linear calculation circuit 382 substantially similar to the comparison circuit 361;
Curve calculation circuit 383, programmable divider 3
84, includes a comparison circuit 385, and a linear calculation circuit 38
The period of the subtraction operation in 2 is the output of the oscillator 386.
The output voltage of the programmable divider 384 that receives
By changing the period of the loop, the hidden
The basic structure is to create a falling and falling waveform part.
In this respect, it is the same as the timbre function generation circuit 344 described above.
It's like that. However, the output pulse ADD of the divider 384₃of
The period is each waveform part ENV₁~ENV_FourThe slope changes in response to
Gate signal generated in further control circuit 387
By M1 to M4, the first series parameter generation time
A constant signal coming from path 5A is sent to divider 384.
Set by giving it as a period setting signal to
be done. First, attack waveform part ENV₁In order to generate
First gate signal M₁The opening of the game is controlled by
1st series parameter generation circuit 5 through GT1
Attack rate constant AR coming from A_A1the device
divider 384, thereby outputting the output of divider 384.
force pulse ADD₃Let the period of be a constant AR_A1large equivalent to
In this way, the addition of the linear calculation circuit 382 is
calculation operation frequency, in other words, its output waveform ENV
The type of tone selected for ascending slope (e.g. piano,
harpsichord, etc.) and the position of the operated keys.
Set accordingly. Also, the first decay waveform part ENV₂caused
, the second gate signal M₂Open controlled by
gate gt₂Through the first series parameter generation circuit
The first decay rate constant 1DR coming from 5A_A1of
divider 384, thus similar to above.
The first decay waveform part ENV of the output waveform ENV₂of
The descending slope is controlled by the selected tone type and
Set according to the position of the key. Furthermore, in the same manner, the second decay waveform part ENV₃of
To generate the second decay rate constant 2DR_A1of
Third gate signal M₃The opening of the game is controlled by
GT₃to divider 384 through
depending on the selected tone and the operated key position.
Then the second decay waveform part ENV₃The slope of the first day
K waveform part ENV₂If set to a value greater than the slope of
Ru. On the other hand, the dump waveform part ENV_Fourwhere it occurs
In this case, the gate GT is set by the fourth gate signal M4._Four
and through this the decay rate constant DR_A1Deva
second decay waveform part ENV₃Yo
The dump waveform part ENV has a larger slope._Fourof
Set. Gate signal M1 for gates GT1 to GT4
~M4 is the second key from the slope change control circuit 387.
- Sequentially after arrival of switch key-on detection signal TK2
generated. The slope change control circuit 387 has 16 stages of shifting.
Memory circuit 388 with three bit registers
Then, "1" is added to the output of the memory circuit 388 and recorded.
an addition circuit 389 for re-memorizing in the storage circuit 388;
have The memory circuit 388 is the linear calculation circuit 3 described above.
82 memory circuit 390 and curve calculation circuit 383.
Similarly to the memory circuit 393, the master clock φ₁，
φ₂By performing a shift operation by
Dynamic step data for each 16 channels
Remember. Thus, the output KT of the memory circuit 388 is 3 bits.
A binary signal is sent to the decoder 396.
is converted into four line outputs M1 to M4.
However, the output KT of the memory circuit 388 is "000".
When the decoder 396 sends out the gate signal M1,
Similarly, when it is "001", the gate signal M2 is sent out,
When "010", gate signal M3 is sent, and when "011"
When the gate signal M4 is sent out, the slope is changed.
The control circuit 387 indicates that the content of the memory circuit 388 is "000".
``1'' is added from the state to ``011''
According to
Send. However, the difference between the adder circuit 389 and the memory circuit 388 is
In between, the second key switch detection signal TK2 is opened.
An AND gate 397 is provided as a control signal,
As a result, when the detection signal TK2 is “0”, the chip
All bits of the memory contents of Jannel's memory circuit 388
“0” and when the detection signal TK2 becomes “1”
Addition circuit 3 for the memory contents of storage circuit 388
Start the addition operation of 89 from the state of "000"
It is done like this. However, the output of the gate signal M1 of the decoder 396
Insert the second key switch detection signal TK2 into the power path.
An AND gate 398 is provided as an open control signal.
As a result, when the detection signal TK2 arrives, the
First, the gate signal M1 is sent out. This gate signal M1 is given to gate GT1.
Therefore, the divider 384 is a constant AR_A1corresponds to
“1” signal ADD with period₃and gate 399
Send via. here and gate 399
is the output of the memory circuit 390 of the linear calculation circuit 382
AND circuit 400 for minimum value detection provided at the end
The inhibition signal 2DF′ from these is transmitted through the inverter 401
receive. However, the AND circuit 400 has the first
All of the outputs of the storage circuit 390 as condition signals of
The output of the NOR circuit 402 which receives the bit output of
and the third and third conditions as the second condition signal.
OR circuit 403 receiving 4 gate signals M3 and M4
The output of is given. Therefore, ANDGATE 400
is the gate signal when there is no memory in the memory circuit 390.
When issue M3 or M4 is occurring (i.e.
2day K waveform part ENV₃Or dump waveform part ENV_Four
) works. Ando game there
gate 399 is prohibited when gate signal M1 is generated.
Since the device that passed through the AND gate 399
Ida 384 output ADD₃is the bottom of the adder circuit 391
input to the lowest bit. On the other hand, the bits other than the least significant bit of the adder circuit 391
An AND gate 404 is provided for the input terminal of the gate.
This is inverter 4 by gate signal M1.
Prohibition control is performed via 05. Therefore the gate signal
When M1 occurs, the adder circuit 391
Adding the “1” signal that arrives at the bit
Therefore, the output AOC of the memory circuit 390 is
Waveform ENV is constant AR_A1erected with an inclination equivalent to
Upward, thus the attack waveform part ENV₁is formed
Ru. In this state, the contents of the memory circuit 390 are all
is maintained until the bit becomes logical ``1''.
Ru. However, all bits become logical "1"
This is detected by the AND circuit 406 for maximum value detection.
The logic “1” output is sent to the slope change control circuit 38.
7 is given as a step input signal AF to the step circuit 407.
available. The step circuit 407 adds the input signal AF to the adder circuit 38
9 through its input OR gate 408 and recorded.
Add “001” to the memory contents of the storage circuit 388 and
Then, the second gate signal M2 is output from the decoder 396.
to occur. This second gate signal M2 is applied to gate GT2.
Therefore, divider 384 has a constant 1DR<sub>A1</sub>phase
"1" signal ADD of the corresponding period<sub>3</sub>gate 399
Send via. However, in this case, the linear calculation circuit
382 to the input gate 404 to the adder circuit 391.
The prohibited operations for this have been lifted. Therefore, the addition times
“1” signal ADD to all bits of path 391<sub>3</sub>but
As a result, the adder circuit 391 becomes a memory circuit.
We decided to subtract 1 from the contents of 390.
Therefore, the output waveform ENV of the memory circuit 390 is constant.
Number 1DR<sub>A1</sub>It descends at an inclination equivalent to
1st Decay waveform part ENV<sub>2</sub>is formed. At this time, the output AOC of the memory circuit 390 is
At path 385, the first series parameter generation circuit 5
Decay transition level constant 1DL coming from A<sub>A1</sub>and
The output AOC is compared to this constant 1DL<sub>A1</sub>lower than
When the detection output 1DF is
(controlled open by gate signal M2)
put out This detection output 1DF is input to the step circuit 407.
A step signal is sent to the adder circuit 389 via the power gate 408.
Entered as a number. Therefore, the step circuit 389 is
Add “001” to the memory contents of the storage circuit 388 and
Then, the third gate signal M3 is output from the decoder 396.
to occur. This third gate signal M3 is applied to gate GT3.
Therefore, divider 384 has a constant 2DR<sub>A1</sub>phase
"1" signal ADD of the corresponding period<sub>3</sub>gate 399
Send via. At this time, the linear calculation circuit 382
“1” for all bits of adder circuit 391
signal is given, so the adder circuit 391
We decided to subtract the contents of 390 by ``1''.
Therefore, the output waveform ENV of the memory circuit 390 is
constant 2DR_A1a slope equivalent to (usually constant 1DR_A1phase
(less than the slope of the slope) and hide the
2nd Decay waveform part ENV₃is formed. In this way, the output waveform of the linear calculation circuit 382
ENV is the decay transition level constant whose value is
1DL_A1The slope will be eased at this point. In principle, this state (damper pedal 9 is operated
) If the contents of the linear calculation circuit 382 are
By becoming “0”, the value of the output waveform ENV is the minimum
It is maintained until the value M1N (Fig. 16) is reached. However, the contents of the memory circuit 390 become "0".
, logic “1” is input to the AND circuit 400 for minimum value detection.
Detection output 2DF¹occurs, and this is the end of the day.
The AND circuit 410 for generating a completion signal (FIG. 12B)
Given. In this state, if the key is released, the second key switch
The switch-on detection signal TK2 becomes logic “0” and the slave
Addition circuit 389 of slope change control circuit 387 and
AND gate 3 disposed between
97 closes, the contents of the memory circuit 388
is cleared. Also, the output gate of gate signal M1
gate 398 is closed, thus controlling circuit 387.
Return to standby state. The above operation will occur if the damper pedal 9 is not operated.
In this case, the second decay waveform part ENV₃of
During the process, the damper pedal 9 is operated (see Fig. 16).
time t_{twenty four}) and the damper wave as follows:
Shape ENV_Fouris formed. In other words, the step circuit on the input side of the adder circuit 389
407 is an AND circuit 411 for forming a dump waveform portion.
is provided, and a third gate is provided as the first condition signal.
The second condition signal M3 is given as the second condition signal.
The damper pedal signal PO is passed through the inverter 412.
key-off detection as the third condition signal.
A signal TDO is given. Thus the second day
Waveform section ENV₃During the period when
When the key is operated, the damper pedal 9 is also operated.
When the logic “1” is output from the AND circuit 411,
This is sent via the input OR gate 408.
It is input to the adder circuit 389 as a progress signal. At this time, the adder circuit 389 is one of the memory circuits 388.
, and thus the decoder 396
A fourth gate signal M4 is generated. This fourth gate signal M4 is applied to gate GT4.
Therefore, divider 384 has a constant DR_A1phase
"1" signal ADD of the corresponding period₃gate 399
Send via. At this time, the linear calculation circuit 382
“1” for all bits of adder circuit 391
signal is given, so the adder circuit 391
We decided to subtract the contents of 390 by ``1''.
Therefore, the output waveform ENV of the memory circuit 390 is
Constant DR_A1(usually the second Decay wave)
Shape ENV₃(sufficiently larger than the slope of)
drops to the minimum level M1N and thus the dump wave
Shape ENV_Fouris formed. Therefore, the adder circuit 391 and the memory circuit 3
90 is a calculation means in each invention.
and storage means, and in the first invention
The arithmetic control means includes the divider 384 and the oscillator 3.
86, but the arithmetic control means in the second invention is a game
GT1 to GT4, divider 384 and
The gate 404 is controlled by the comparator circuit 385 and the controller.
Arithmetic circuit 389, AND gate 397, step circuit 4
07, the second storage means is the storage circuit 388.
The arithmetic control means in the invention of No. 3 is the constant generation circuit 3.
25 and 326, divider 384, oscillator 38
6 are equivalent to each other. As described above, the memory times of the linear arithmetic circuit 382 are
The waveform output AOC obtained at path 390 is the output terminal
of the volume function generation circuit 381 via Z1 to Z32.
Amplitude level or envelope variable output A₁(t)
and the multiplier circuit 415 (FIG. 12B)
The variable T for volume selection in_1a(t) multiplied by
The multiplication result is sent to the next multiplication circuit 416 as the first
Comprehensive sound coming from series parameter generation circuit 5A
is multiplied by the quantity constant K1, thus the amplitude term K in equation (3)
1・T_1a(t)・A₁(t) is obtained. Here, the variable T for volume selection_1a(t) is keyboard information
Initial touch control circuit 1 of generator 1
4 and the aftertouch control circuit 15.
Incoming initial touch signal ITD and after touch signal
is formed based on the signal ATD (Fig. 12).
A). In other words, the initial touch signal ITD is multiplied by
In the circuit 417, the first series parameter generation circuit
Initial constant β coming from 5A_iis multiplied by
At the same time, the aftertouch signal ATD is transmitted to the multiplier circuit 41.
8, from the first series parameter generation circuit 5A.
Arrival after constant β_aand these multiplications
The results are added in an adder 419 to the variable T_1a
(t) to the multiplication circuit 415 described above. The variable T obtained in this way_1a(t) is af
The touch signal ATD corresponds to the key while the performer is pressing the key.
Changes according to changes in the pressing force applied by
This makes it a temporal variable. (4-4) Output circuit The output circuit 421 (FIG. 12B) outputs the above-mentioned modulated wave.
Output T of term operation circuit 333_1i(t)・I₁(t)・sin
D₁・ωt and the output B of the carrier term calculation circuit 332
1・ωt and the output K1・of the amplitude term calculation circuit 331
T_1a(t)・t₁Based on (t), the output of the first term of equation (3) is
First, the carrier wave term calculation circuit 33
2 and the output of the modulation wave term calculation circuit 333 are added together.
After addition in calculator 422, sin function of ROM configuration
In the generator 423, the output sin {B1・ωt+T_1i
(t)・I₁(t)・sin D₁・ωt} is generated. The output of this sin function generator 423 is then multiplied by
In the path 424, the output of the amplitude term calculation circuit 331 and
The output that is multiplied and thus realizes the first term in equation (3)
K1・T_1a(t)・A₁(t)・sin{B1・ωt＋T_1i
(t)・I₁(t)・sin D₁・ωt} is obtained. By the way, this first term output is the first series musical tone signal.
Key information IFK and touch information arriving at the forming section 7A
IFT is a time division multiplexed digital signal.
Similarly, time division multiplexed digital signals
It is obtained as a result of processing as a
The digital signal is analyzed by the D/A converter 425.
It is converted to a log signal and finally sent to the time division multiplexing system.
The signal of the first term is sent to the musical tone generator 8 as an analog signal.
sound signal e₁Sent as . The same applies to the second series musical tone signal forming section 7B.
The time-division multiplexed analog signal is sent to the musical tone generator.
The musical tone signal e of the second term to 8₂Sent as . On the other hand, the amplitude term calculation of the first series musical tone signal forming section 7A
Minimum value detection output formed in circuit 331
2DF' is similarly generated by the second series musical tone signal forming section 7.
The minimum value detection formed in the amplitude term calculation circuit of B
Along with the output 2DF′, there is also an alarm for generating the decay end signal.
is given as an input condition to the control circuit 410, and both systems
The envelope waveform output ENV for both columns is the minimum value M1
When it becomes N, the Decay ends from the AND circuit 410.
Generates completion signal 2DF. This signal 2DF is a channel
Timing control circuit of processor 13
As a clear signal generation condition signal for 13F
Given. Therefore, the timing control circuit 13F
-Send clear signal to code storage circuit 13C
As a result, the first stage of the memory circuit main body 237
Clear the memory of the channel that actually exists on the stage.
a. Therefore, it will be stored in the channel from now on.
The sound corresponding to the key code KC that was entered will stop producing.
This channel becomes an empty channel. Furthermore, the amplitude term of the first series musical tone signal forming section 7A is
Output K1・T of calculation circuit 331_1a(t)・A₁(t) is
Similar output K2 of the second series musical tone signal forming section 7B
T_2a(t)・A₂(t) in addition circuit 430.
The addition result is the envelope signal.
The channel processor 13 mentioned above is used as ΣKA.
The signal is applied to the minimum value storage comparison circuit 280. However, the envelope signal ΣKA is simultaneously pronounced.
What actually happened on the 1st to 16th channels?
It represents the envelope of the musical tone that follows the
The minimum value of the envelope is memorized for each channel.
smaller than the minimum value stored in comparison circuit 280
This is stored in the minimum value storage circuit 280 when the
Stored as a value. [5] Musical tone generator The musical tone generator 8 is a sound generator consisting of an amplifier, speakers, etc.
The first and second series
When arriving from the series musical tone signal forming units 7A and 7B
Division multiplex analog signal e₁and e₂The first ~ included in
The musical tone signal of the 16th channel is emitted one after another as musical tones.
Let it grow (Figure 1). However, the musical tones of the 1st to 16th channels are sequentially mapped.
It is generated in synchronization with the stack clock, but its period is
Because it is short, the human ear can actually hear the sound of all channels.
to give the same effect as if they were pronounced at the same time.
Become. The above is an example configuration of an electronic musical instrument including this invention.
However, in the above configuration, the overall operation can be controlled by key commands.
As described above for the reader 12 (Fig. 4 A to C).
The scale note of the 0th block “C”₁” key and the first block.
Rock scale note “C”₂”, “E₂” key is operated.
As an example, when a key is operated,
First, the first key switch K1 closes, and then the key is pressed.
The second key switch K is activated after a period of time corresponding to the speed has elapsed.
2 closes. However, the key coder 12 first uses the first key switch.
As Tsuchi K1 is closed, the master clock
φ₁,φ₂(with a period of 1 μs) and its 16 cycles
Clock φ with period length_C,φ_DDepending on each part
operate the delay flip-flop circuits of
By this, the 0th and 1st blocks are detected as blocks.
In addition to storing it in the circuit 12B, the
Block number (in this example, 7th, 6th...
The data is sent sequentially starting from block 0). Also this sending
Notes included in the block
12D, and the one with the highest priority is
root number (in this example, note names C, B...
C# order). Thus the key
From coder 12, all keys currently pressed
Key code signal KC (block code signal)
No. BC and note code signal NC are combined)
will be sent out sequentially. Thus, the channel processor 13 (FIG. 7A)
The key code signal KC that sequentially arrives at ~C) is
Master clock φ is connected to pull-hold circuit 13B.₁，
φ₂is held for a time of 16 cycles, and this 16
During the cycle interval, the key code storage circuit 13C
Notes on the 16 channels of the memory circuit body 237
Ratio of stored data to sample-held data
The comparison completes the cycle, thus resulting in three empty channels,
Each incoming key code signal KC is memorized.
Ru. In this way, the separate chips of the memory circuit body 237 are
Each key code KC stored in Yannel is set as the content.
The data stored will continue to be retained even if the key is subsequently released.
and the first and second series musical tone signal forming section 7A and
Decay end signal at 7B (Figure 12 A and B)
When 2DF occurs (i.e. when the sound disappears),
Timing control circuit 13F (Figure 7A)
The output of the AND gate 309 for clearing
Realized. Therefore, the key code storage circuit 13C
is usually the key code of the currently pressed key.
KC and key released but still Decay waveform part
The key code KC of the key generating the sound is recorded.
It will be remembered. On the other hand, the key code data is stored in the memory circuit main body 237.
Once memorized, this will be used as the first key switch information.
first key switch key-on memory circuit 291
(FIG. 7B) is stored in the corresponding channel. From the above key operations, the key code memory circuit body 2
37 and first key switch key-on memory circuit 29
The operation up to memorization of 1 is based on the startup pattern of the key coder 12.
The starting pulse TC is generated from pulse generation circuit 12F.
The result is a channel process.
The content of the key code signal KC that arrived at Tsusa 13 is
Stored in the key code storage circuit main body 237
If it matches any of the data, the arrival data will be returned again.
Let the data disappear without memorizing it.
Ru. Eventually, when the second key switch K2 closes, the
1 key switch K1 as described above.
The operation is performed in the key coder 12 and is currently
Regarding keys with key switch K2 closed
High priority block number and high priority
Detection is performed sequentially starting with the note number with the highest number.
The detection result is stored in the second memory of the note detection circuit 12D.
146 (FIG. 4B). This detection signal KA2 is sent to the channel processor 1.
3 timing control circuit 13F (Fig. 7
A) through its second key switch memory control
2nd key switch via AND circuit 301
-on memory circuit 292 (FIG. 7B)
Remembered by Jannel. Furthermore, channel processing
2nd key switch detection signal arrived at sensor 13
Load KA2 into which channel of memory circuit 292
Each channel of the memory circuit main body 237
By comparing the contents of the incoming data with the contents of the incoming data,
The matched channel is stored in the matched channel storage circuit 2.
This is done by making a determination via 41. In this way, the operation of the first key switch K1 is
Accordingly, the memory data stored in the memory circuit main body 237
1st key switch key-on detection obtained based on data
Signal TK1 and 2nd key switch key-on memory time
Obtained based on the memory data stored in the path 292
The second key switch key-on detection signal TK2 is
Western touch control circuit 14 (Fig. 2)
is given by a large area corresponding to the interval between their arrival points.
Generate initial touch data ITD
Ru. On the other hand, the second key switch K2 is activated by key operation.
Pressure pressure detector located under the key after closing
(Piezoelectric element) For DT1 to DT88 (Fig. 9)
When you press a key, it responds to changes in pressing pressure.
The detection outputs dt1 to dt88 obtained accordingly are after
applied to the control circuit 15 (Fig. 2).
and thus the key code of the key being pressed.
Size of aftertouch operation for each KC
Generate after-touch data ATD according to. Initial touch data thus generated
ITD and aftertouch data ATD is touch information
As IFT, key code KC as key information and
Both the first and second series musical tone signal forming sections 7A and 7
given to B. These forming portions 7A and 7B are
The first to
16th channel data (i.e. time division multiplexed)
For formula data), key information IFK and touch
Information IFT contents and tone selection switch 6 selection
Based on the first and second series parameter generation circuit 5
Determined by the parameters generated in A and 5B.
The output of the complete waveform is sequentially output to the master clock φ₁,φ₂
It is transmitted with a period of 16 periods. Thus it is easy
From the sound generation unit 8, the signals for the 1st to 16th channels are transmitted.
When multiple sounds obtained by equation (3) are pronounced simultaneously,
A musical tone with a similar effect is generated, and the musical tone is
Key information for channel keys corresponds to IFK
A sound that has a high pitch and is compatible with Tatsuchi Information IFT.
Structure of a synthesized sound with color changes and volume changes
It will have a long history. Note that the calculation operations of the musical tone signal forming sections 7A and 7B are as follows.
2nd key switch key on for each channel
On the condition that the detection signal TK2 has arrived.
It is executed (Figures 13 and 15), so it
emit unnecessary musical tones for previously arriving data.
Not alive. Stop pressing the key that corresponds to the musical tone being generated.
When you release the key, this musical tone enters the decay mode.
Then, the corresponding channel of channel processor 13
Regarding the first key switch key-on memory circuit 29
1 (Figure 7B) is the key-off detection timing.
By being cleared by signal
Key-off detection is performed by the timing signal
- is stored in the OFF storage circuit 293. In contrast to this
If the damper pedal 9 is not operated, the day-care will end.
The musical tone signal is slowly generated until the completion signal 2DF is generated.
Attenuate. Therefore, the first series and second series musical tone signal forming section 7
A and 7B indicate that the damper pedal 9 has been operated.
This causes the musical tone signal to suddenly attenuate. The above key code storage circuit 13C (Fig. 7B)
The assignment memory operation of key code data KC to
- There is an empty channel in the code storage circuit 13C.
However, if there is no empty channel, the
is stored in the link circuit 13G (Fig. 7C).
is currently generating the minimum amplitude musical tone signal.
Key code that is currently receiving channel data
Rewrite with code data. Therefore, the new key information
be utilized while satisfying the optimal conditions at that time.
That will happen. Correspondence between the above embodiments and each claim
It can be written as follows. Functional waveform generator according to claim 1
In other words, the timbre function generation circuit 344 (13th
) or volume function generation circuit 381 (Figure 15)
are from the memory circuit 347 or 390, respectively.
storage means, addition circuit 353 or 391.
calculation means, ROM 325 or 326
Number generation means, square wave oscillator 355 and program
Mable divider 356 or channel divider
An arithmetic control unit consisting of a data generator 384 and an oscillator 386
It has steps. Furthermore, the function waveform generator according to claim 2
timbre function generation circuit 344 (the timbre function generation circuit 344)
13) or the volume function generating circuit 384 (Fig. 15)
) are the storage circuits 347 and 390, respectively.
The first storage means, addition circuit 353 or 3
91, a register 358 or a
A second storage means consisting of a storage circuit 388, a set signal
No. formation circuit 349, OR gate 359, andgame
gate 360, comparison circuit 361, OR gate 36
2. Combination or ratio of inverter 363, etc.
Comparison circuit 385, step circuit 389, AND gate 3
97, step circuit 407, etc.
Control means, AND gate 354, or gate
GT1~4, channel divider 384, input gate
It is equipped with arithmetic control means consisting of a gate 404, etc.
Ru. Furthermore, the function waveform according to claim 3
Generator, ie, timbre function generation circuit 344
(Figure 13) or volume function generation circuit 384 (Figure 13)
15) are memory circuits 347 and 39, respectively.
Storage means consisting of 0, addition circuit 353 or 39
Arithmetic means consisting of 1, ROM325, 326, rectangle
Shape wave oscillator 355, programmable divider 35
6 combination, or ROM325, 326, game
GT1~4, channel divider 384,
Equipped with arithmetic control means consisting of a combination of vibrators 386
It is growing. As explained above, the function waveform according to this invention
Generator (in the embodiment, the timbre function generation circuit 344 or
or the volume function generation circuit 381)
In this case, using calculation means and temporary storage means,
Generate function waveforms through digital calculations
Because we are doing this, we cannot use large capacity functions like before.
There is no need to provide waveform memory, so configuration is simple.
It becomes simpler and lower cost. Furthermore, according to the first invention, the constant
Since the waveform change characteristics of several waveforms are controlled, the constant
Easily generate various function waveforms by changing
I can live. Further, according to the second invention, the function waveform
Data representing the current formation interval (occurrence interval) of
Since we have a storage means to store this data,
The calculation operation of the calculation means (calculation
aspects) can be controlled independently, and therefore complex
Functional waveforms with similar shapes can also be easily generated. Also, the
According to the invention of No. 3, the calculation operation of the calculation means is manipulated.
Since the control corresponds to the key that is
Function waveform (envelope) corresponding to the pitch of the key
waveform) and use this function waveform.
If you control the timbre and volume of musical sounds, you can create natural instrument sounds.
You can get similar musical tones.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example of an electronic musical instrument using the function waveform generator according to the present invention, FIG. 2 is a system diagram showing its keyboard information generating section, and FIGS. 3A and B
and C are plan views, side views, and partially enlarged perspective views showing the operating mechanism of a key switch to which the key operation detection circuit of FIG. 2 can be applied, and FIGS. Connection diagram shown in separate drawings,
5 is a signal waveform diagram showing the master clock and related timing signals, FIG. 6 is a flowchart explaining the operation of the key coder in FIG. 4, and FIG. 7 A, B, and C are channels in FIG. 2. Connection diagram showing the processor divided into three drawings, No. 8
9 is a connection diagram showing the initial touch control circuit in FIG. 2, FIG. 9 is a connection diagram showing the after touch control circuit in FIG. 2, FIG. 10 is a block diagram showing the parameter generation circuit in FIG. 1, and FIG.
The figure is a connection diagram showing the timbre selection switch in Fig. 1, Fig. 12 A and B is a connection diagram showing the musical tone signal forming section in Fig. 1 divided into two drawings, and Fig. 13 is its timbre function generation circuit. FIG. 14 is a waveform diagram showing the reference timbre waveform, FIG. 15 is a connection diagram showing the volume function generating circuit of FIG. 12, and FIG. 16 is a waveform diagram showing its output waveform. DESCRIPTION OF SYMBOLS 1... Keyboard information generation section, 5A, 5B... First series, second series parameter generation circuit, 6... Tone selection switch, 7A, 7B... First series, second series musical tone signal forming section, 8... ...Musical sound generator, 9...Damper pedal, 11...Key operation detection circuit, 11A...
...key switch group, 11B...pressure detection element group,
12...Key coder, 12A...Key switch circuit, 12B...Block detection circuit, 12C...Temporary memory circuit, 12D...Note detection circuit, 12E
... Step control circuit, 12F ... Start pulse generation circuit, 13 ... Channel processor, 13A ... Synchronization signal generation circuit, 13B ... Sample hold circuit, 13C ... Key code storage circuit, 13D ... Key code comparison control circuit, 13
E...Key operation discrimination circuit, 13F...Timing control circuit, 13G...Truncate circuit, 14...Initial touch control circuit, 14A...Timekeeping logic circuit, 14B...Conversion circuit, 15...Aftertouch control circuit ,1
5A...Multiplexer, 15B...A/D converter, 325, 326...ROM, 331...Amplitude term calculation circuit, 332...Carrier term calculation circuit, 33
3... Modulation wave term calculation circuit, 344... Tone color function generation circuit, 355... Oscillator, 356... Programmable divider, 358... Shift register, 3
81... Volume function generation circuit, 384... Programmable divider, 386... Oscillator, 388...
Memory circuit, 389... Addition circuit, GT1 to GT4
……Gate.

Claims (1)

[Claims] 1. Function waveform generators 344, 381 for electronic musical instruments that simultaneously form and generate a plurality of musical tone control function waveforms for controlling the volume and timbre of musical tones over time.
storage means 347, 390 having a plurality of storage locations corresponding to the plurality of function waveforms, storing function waveform values of each function waveform, and sequentially outputting each of the stored function waveform values; A new function waveform value of each function waveform is calculated by time-sharingly performing a predetermined calculation on each function waveform value sequentially output from the storage means, and the storage contents regarding each function waveform in the storage means are calculation means 353 and 391 for temporally changing the function waveform values stored in the storage means by respectively rewriting them with new function waveform values calculated by the calculation; Constant generating means 325, 3 for setting the rate of change in the waveform changing portion numerically and generating constant data representing the numerical value.
26, and calculation control means 3 for controlling the calculation timing of the predetermined calculation in the calculation means by outputting a signal with a period corresponding to the numerical value represented by the constant data.
55, 356, 384, and 386. 2 Function waveform generators 344, 381 for electronic musical instruments that simultaneously form and generate multiple musical tone control function waveforms for controlling the volume and timbre of musical tones over time
In the first storage means 347; 390, which has a plurality of storage locations corresponding to the plurality of function waveforms, stores function waveform values of each function waveform, and sequentially outputs the stored function waveform values. and calculating new function waveform values for each of the function waveforms by time-divisionally performing predetermined calculations on each of the function waveform values sequentially output from the first storage means, and storing the function waveform values in the first storage means. calculation means 353 for temporally changing the function waveform values stored in the first storage means by respectively rewriting the stored contents of the function waveforms of the means with new function waveform values calculated by the calculation; 391, second storage means 358, 388 having a plurality of storage locations corresponding to the plurality of function waveforms and storing data representing the current formation section (state) of each function waveform; control means 349 for updating and controlling each data in the storage means 2 based on the generation command signal TK2 of each function waveform and each function waveform value;
359,360,361-363,385,38
9,397,407, and arithmetic control means 354 for controlling the arithmetic operation regarding each function waveform in the arithmetic means according to each data of the second storage means; GT1 to
A function waveform generator for an electronic musical instrument comprising GT4, 384, and 404. 3 Function waveform generator 344, 3 for an electronic musical instrument that generates a musical tone control function waveform in response to key operations on a keyboard to control the volume and timbre of musical tones over time.
81, storage means 347 and 390 for storing function waveform values of the function waveform; and calculating a new function waveform value of the function waveform by performing a predetermined operation on the function waveform value of the storage means; calculation means 353, 391 for temporally changing the function waveform value of the storage means by rewriting the storage contents of the storage means with a new function waveform value calculated by the calculation; receiving key information (KC) indicating a position, controlling the calculation operation of the predetermined calculation in the calculation means according to the key information, and changing the function waveform value over time in accordance with the operated key; Calculation control means 325, 32
6,355,356,325,326,GT1～
A function waveform generator for an electronic musical instrument comprising GT4, 384, and 386.