JPS604264A - Insulated gate type fet - Google Patents
Insulated gate type fetInfo
- Publication number
- JPS604264A JPS604264A JP11201583A JP11201583A JPS604264A JP S604264 A JPS604264 A JP S604264A JP 11201583 A JP11201583 A JP 11201583A JP 11201583 A JP11201583 A JP 11201583A JP S604264 A JPS604264 A JP S604264A
- Authority
- JP
- Japan
- Prior art keywords
- side wall
- etching
- channel
- region
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 5
- 230000008595 infiltration Effects 0.000 abstract 1
- 238000001764 infiltration Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 241000605281 Anaplasma phagocytophilum Species 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
木兄り」は、絶縁ゲート型電界効果トシンジスタ（以下
ＭＯ８］・’ＥＴという）にかかり、とくにゲート長が
１μｍ％度以下の短チャンネルＭＯＢ Ｆ）、Ｔの構造
に関する。[Detailed Description of the Invention] The present invention relates to insulated gate field effect transistors (hereinafter referred to as MO8) and 'ET', and particularly relates to the structure of short channel MOBs (F) and T with a gate length of 1 μm or less. .
ＭＯＳ ＦＥ’ｌ”ので１ぺ細化は、高年私密度および
高速化のために必要不可欠でおる。特にチャンネル長を
短かくすることは、高速化にとって効果的である。短チ
ャンネルにするためには、パンチスルーを防止するため
にソース・ドレイン接合深さを浅くする必要がある。し
かし、浅い接合は層抵抗が高くなシ、ソース・ドレイン
寄生抵抗が増加するため、動作速度が遅くなる。従って
、浅い接合を実現すると同時に、寄生抵抗を小さくする
工夫が必要である。Since MOS FE'l'' is made smaller, it is indispensable for high density and high speed. In particular, shortening the channel length is effective for high speed. In order to prevent punch-through, it is necessary to reduce the depth of the source/drain junction.However, a shallow junction has a high layer resistance and increases the source/drain parasitic resistance, which slows down the operation speed. Therefore, it is necessary to create a shallow junction and at the same time reduce the parasitic resistance.
従来よシ、このだめの方法としてサイドウオールを用い
る素子構造が提案されている。Conventionally, element structures using sidewalls have been proposed as a method to avoid this problem.
この従来技術によるサイド・ウオール法を第１図（ａ）
、 （ｂ）に示す。１はシリコン基板、２はゲート酸
化膜、３は多結晶シリコンであシ、通常のシリコン・ゲ
ートＭＯＳトランジスターの構造をしている。多結晶シ
リコンのバターニング後ｓ Ｉ Ｘ １０ｔｓｃＩ！Ｌ
′″２程度のドーズ量でドーパントをイメン注入し、浅
い接合４を形成する。次に、厚さ０．５〜１μｍ程度の
酸化膜５を気相成長する。′次に、基板全面をリアクテ
ィブ・イオン・エツチング（ＲＩＥ） 法で酸化膜をエ
ツチングすると、多結晶シリコンの側面にサイド・ウオ
ール６が形成される。このサイド・ウオールをイオン注
入のマスクに用いて、５ｘ１０”ｃｍ−ｚ程度のイオン
注入を行い、深い接合７を形成する。This conventional side wall method is shown in Figure 1(a).
, shown in (b). 1 is a silicon substrate, 2 is a gate oxide film, and 3 is polycrystalline silicon, and has the structure of a normal silicon gate MOS transistor. After buttering polycrystalline silicon, s I X 10tscI! L
A dopant is implanted at a dose of approximately 2 to form a shallow junction 4. Next, an oxide film 5 with a thickness of approximately 0.5 to 1 μm is grown in a vapor phase. When the oxide film is etched using the active ion etching (RIE) method, a side wall 6 is formed on the side surface of the polycrystalline silicon.This side wall is used as a mask for ion implantation, and the oxide film is etched by about 5 x 10" cm-z. ion implantation is performed to form a deep junction 7.
この方法で実現されるＭＯＳ ＦＥＴのソース・ドレイ
ン領域は、層抵抗は高いが浅い接合と、層抵抗が低い深
い接合とが組み合わされている。この構造では、チャン
ネル長は浅い接合で決定される。The source/drain regions of the MOS FET realized by this method are a combination of a shallow junction with high layer resistance and a deep junction with low layer resistance. In this structure, the channel length is determined by the shallow junction.
深い接合は、寄生抵抗を下げるために効果がある。Deep junctions are effective in reducing parasitic resistance.
この従来技術によるサイド・ウオール構造の欠点は、サ
イド・ウオール６の厚みが少ないことにある。このため
、深い接合領域がチャンネル領域に近づきすぎるため、
パンチ・スルーが起こシ易く、短チャンネル化に限界が
あった。A disadvantage of this prior art side wall structure is that the side wall 6 has a small thickness. This causes the deep junction region to be too close to the channel region.
Punch-through was easy to occur, and there was a limit to the shortening of the channel.
本発明の目的はかかる従来技術の欠点を除去した有効な
ＭＯ８Ｂ”ＥＴを提供することである。The object of the present invention is to provide an effective MO8B''ET that eliminates the drawbacks of the prior art.
本発明の特徴は、ゲート電極の側面に傾斜がつけられた
絶縁膜を具え、前記ゲート電極と前記絶縁膜とを合せた
断面形状がほぼ台形であり、前記・ゲート電極によシ自
動的に位置決めされた浅い拡散層と、前記絶縁膜により
自動的に位置決めされた深い拡散層とを具えたＭＯＳ
ＦＥＴの構造にある。The present invention is characterized in that the side surface of the gate electrode is provided with an insulating film with a slope, and the combined cross-sectional shape of the gate electrode and the insulating film is approximately trapezoidal. A MOS comprising a positioned shallow diffusion layer and a deep diffusion layer automatically positioned by the insulating film.
It's in the structure of the FET.
このような本発明による新サイド・ウオール構造を用い
ると、十分に厚くかつ傾斜がつけられたサイド・ウオー
ルが形成できるため、深い接合領域とチャンネル領域が
近づきすぎることがなく、容易に短チャンネルが達成で
きる。By using the new side wall structure according to the present invention, a sufficiently thick and sloped side wall can be formed, so that the deep junction region and the channel region do not come too close together, making it easy to form a short channel. It can be achieved.
第２図に、本発明の実施例を示す。本発明のサイド・ウ
オールを形成するまでの工程は、従来技術第１図（ａ）
と同一である。新しい点は、サイド・ウオールのための
几ＩＥにおいて、第３図に示す様に、エッチャントの進
入方向１ｏに対して、基板を角度θだけ傾け、中心軸１
２を中心に回転させながらエツチングするととにある。FIG. 2 shows an embodiment of the invention. The process up to forming the side wall of the present invention is similar to that of the prior art shown in Fig. 1(a).
is the same as The new point is that in the side wall IE, as shown in Fig. 3, the substrate is tilted by an angle θ with respect to the etchant entrance direction 1o, and the central axis 1
If you do the etching while rotating around 2, it will be there.
この方法によシ、影になる部分にテーパーが付けられて
エツチングされるため、第２図に示されるように、ツ・
イド・ウオール８の厚みが増す。その結果、深い接合領
域９がチャンネル領域から離れるから、パンチ・スルー
が起こシにくくなる。また、多結晶シリコンの段部がな
だらかになシ、微細なアルミ配線が容易になる。With this method, the shaded area is tapered and etched, resulting in
The thickness of the id wall 8 increases. As a result, since the deep junction region 9 is separated from the channel region, punch-through is less likely to occur. In addition, the steps of the polycrystalline silicon are smooth, making it easier to form fine aluminum wiring.
本発明のサイド・ウオール構造によって実現されるＭＯ
ＳＦＥＴは、従来のものに比べてチャンネル長を短かく
することが可能である。又、同じチャンネル長にした場
合には、深い接合ｔ１域の接合深さをより深くできるた
め、アルミ配線とのコンタクト形成が容易になシ、よシ
微細なコンタクト構造が可能に々る。このことは、トラ
ンジスター寸法の縮小および高集積化にとってきわめて
有利である。また、多結晶シリコンの側面に、テーパー
のついたサイド・ウオールが形成されるため、この部分
の段差がなたらかになシ、微細な金り配線が可能になる
という利点がある。MO achieved by the side wall structure of the present invention
SFETs can have a shorter channel length than conventional ones. Further, when the channel lengths are the same, the junction depth in the deep junction t1 region can be made deeper, which facilitates the formation of contact with the aluminum wiring and enables a finer contact structure. This is extremely advantageous for reducing transistor size and increasing integration. Furthermore, since a tapered side wall is formed on the side surface of the polycrystalline silicon, there is an advantage that the step in this part is not rounded and fine gold wiring can be formed.
第１図（ａ）および（ｂ）は従来技術による製造方法を
説明するだめの素子断面図、第２図および第３図は本発
明の詳細な説明するだめの素子断面図およびエツチング
方法の説明図である。
尚、図において、１・・・・・・シリコン基板、２・・
・・・・ゲート酸化膜、計・・・・・多結晶シリコン、
４・・・・・・浅い接合、５・・・・・・酸化膜、６，
８・・・・・・サイド・ウオール、７，９・・・・・・
深い接合、１０・・・・・・エツチングガスの進入路、
１１・・・・・・基板、１２・・・・・・中心ホＨであ
る。
代理人 弁理士 内 原 晋FIGS. 1(a) and (b) are cross-sectional views of a device to explain a manufacturing method according to the prior art, and FIGS. 2 and 3 are cross-sectional views of a device to explain the present invention in detail and an explanation of an etching method. It is a diagram. In the figure, 1... silicon substrate, 2...
...gate oxide film, total ...polycrystalline silicon,
4... Shallow junction, 5... Oxide film, 6,
8...Side wall, 7,9...
Deep bonding, 10... Etching gas entrance path,
11...Substrate, 12...Center H. Agent Patent Attorney Susumu Uchihara
Claims (1)
記ゲート電極と前記絶縁膜とを合せた断面形状がほぼ台
形であシ、前記ゲート電極によシ自動的に位置決めされ
た浅い拡散層と、前記絶縁膜によシ自動的に位置決めさ
れた深い拡散層とを具えることを特徴とする絶縁ゲート
型電界効果トランジスタ。A shallow diffusion layer is provided with an insulating film having a sloped side surface of the gate electrode, the combined cross-sectional shape of the gate electrode and the insulating film is approximately trapezoidal, and the shallow diffusion layer is automatically positioned by the gate electrode. and a deep diffusion layer automatically positioned by the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201583A JPS604264A (en) | 1983-06-22 | 1983-06-22 | Insulated gate type fet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11201583A JPS604264A (en) | 1983-06-22 | 1983-06-22 | Insulated gate type fet |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS604264A true JPS604264A (en) | 1985-01-10 |
Family
ID=14575837
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11201583A Pending JPS604264A (en) | 1983-06-22 | 1983-06-22 | Insulated gate type fet |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS604264A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
| US4868137A (en) * | 1987-12-29 | 1989-09-19 | Nec Corporation | Method of making insulated-gate field effect transistor |
-
1983
- 1983-06-22 JP JP11201583A patent/JPS604264A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
| US4868137A (en) * | 1987-12-29 | 1989-09-19 | Nec Corporation | Method of making insulated-gate field effect transistor |
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