JPS6042500B2 - Multi data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system that can quickly identify the mines and tasks of the central processing unit that was operating at the time when the system is stopped due to the occurrence of a failure.

Conventionally, when multiple central processing units are connected and the system stops for some reason while it is operating, records are kept as to which central processing unit processed which task or when the system stopped. It was extremely difficult to determine the cause of the failure.

Therefore, the operator selects a central processing unit that is known to have had no failures, and debugs it sequentially from the beginning to see how it goes or tries other program processing. This method has the disadvantage that it takes a long time to discover a task early, investigate its cause, and restart processing. SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks, and to provide a multi-data processing system that is capable of quickly ascertaining the correspondence between the tasks processed immediately before the system is stopped and the mines in the central processing unit. It is in. Embodiments of the present invention shown in the drawings will be described below.

FIG. 1 is a schematic diagram of a multi-data processing system, and FIG. 2 is a detailed diagram of task control blocks. In FIG. 1, central processing units CPU-A and CPU-B are so-called multi-connected. When each timer TM-A) TM-B is provided in each central processing unit to process a certain task at a certain running level, the duration is set at the beginning of processing the task and is displayed while it is in operation while being subtracted. . Main storage M
M is connected to each central processing unit CPU via a bus control circuit BSC. Channel CH is also shown in the same manner. R
G-A) RG-B is a register that indicates the running level when the central processing unit processes a task, and has relatively CMPI and CMP2 for processing an interrupt. Immediately before the central processing unit CPU-A starts processing a predetermined task TS-A, a task control block TCB corresponding to the task as shown in FIG. 2 is provided in the main memory device MM, and predetermined items are stored therein. . That is, the mine C of the central processing unit to be processed
PU-A) Task name TS-A) Driving level at the start of processing ITL) When the driving level changes during processing, CTL to store the current level, time credit TCR to store the timer display time, etc. in that order. Set them up side by side.
Initially, the machine number CP excluding the CTL that stores the current level
Predetermined items such as the UAL task name are stored and processing is started. During the process, the operation proceeds while the running level of the central processing unit is stored in the above-mentioned CTL column. If an interrupt with a high running level is made, the task control block TCB is used to save information on the task currently being processed.
The remaining time of the current running level is read from the timer TM and stored in the time credit TCR column. When re-engaging with the current process, the central processing unit reads time information from the time credit TCR column and sets it in the timer TM before re-engaging with the process. When the processing of the task is completed, the used task control block TCB
The information in each column is deleted and the process moves on to the next task. In the next task processing, a task control block is similarly prepared and the CPU machine number is stored in the same manner as described above.
Furthermore, if the system goes down due to some kind of failure during processing, at least the machine number and task name of the central processing unit will be immediately known, as long as the information stored in the task control block TCB is not lost. Corrective measures can be taken immediately, such as checking to see if the problem is caused by hardware or software.

In this way, according to the present invention, when a system failure occurs, it can be immediately detected by associating the central processing unit that is in process with the task, so that countermeasures can be taken immediately, so that the system does not go down. This reduces the amount of time spent on the system and improves reliability.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a multi-data processing system, and FIG. 2 is a detailed diagram of task control blocks used in the present invention. CPU-A. CPU-B...Central processing unit, T
M-A, TM-B...Timer, MM...
・Main memory, CH... Channel, TCB...
...Task control program.

Claims (1)

[Claims] 1 A multi-data processing system that has a plurality of processing devices and memories, in which a processing device is assigned to a predetermined task when the task occurs, and the assigned processing device executes the task; Means for storing task control information in a memory that associates identification information for identifying a task with identification information for instructing a processing device executing the task; and erasing the task control information after completion of execution of the task. 1. A multi-data processing system, comprising: a means for performing a task, and recording a processing device that is executing the task in an identifiable manner.