JPS6041235A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6041235A JPS6041235A JP58149023A JP14902383A JPS6041235A JP S6041235 A JPS6041235 A JP S6041235A JP 58149023 A JP58149023 A JP 58149023A JP 14902383 A JP14902383 A JP 14902383A JP S6041235 A JPS6041235 A JP S6041235A
- Authority
- JP
- Japan
- Prior art keywords
- bump
- photoresist
- semiconductor device
- plating
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高密度で且つ強度の高い外部接続端子を有する
半導体装置の製造方法に関するものである0
半導体装置の外部接続端子としては、金やアルミニウム
のワイヤボンディング用に使われる、いわゆる、ポンデ
ィングパッドと呼ばれるものや、バンブと呼ばれる金属
凸起を端子部分に形成しこの凸起部分と外部の回路の金
属配線と接合するものが一般に使われている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having external connection terminals with high density and high strength. Commonly used terminals include so-called bonding pads, which have metal protrusions called bumps formed on the terminals, and which connect the protrusions to the metal wiring of external circuits.
本発明はこの後者にあたる金属凸起(以下バンブと略記
する)の形成にか−るものである。The present invention relates to the formation of metal protrusions (hereinafter abbreviated as bumps) corresponding to the latter.
半導体装置は、性能の向上及び原価低減の面から微細化
高密度化が要求されている。Semiconductor devices are required to be made smaller and more dense in order to improve performance and reduce costs.
この様な要求に供いバンブもより小さく形成する必要が
生じて来ている。In response to such demands, it has become necessary to make the bumps smaller.
本発明はか\る目的を効果的に実現する方法に関するも
のである。The present invention relates to a method for effectively achieving the above object.
従来バンブは半導体装置の能動領域の加工が完成した後
に感光樹脂をマスクにした一回の選択メッキでこれを形
成していた。Conventionally, bumps were formed by one-time selective plating using a photosensitive resin as a mask after the processing of the active area of a semiconductor device was completed.
第3図は従来の方法で形成したバンブの断面図を示した
。第3図より明らかな様にバンブ4はメッキにより高さ
■までメッキで形成される。FIG. 3 shows a cross-sectional view of a bump formed by a conventional method. As is clear from FIG. 3, the bumps 4 are formed by plating to a height of {circle around (2)}.
この場合、フォトレジスト開口細巾Bに比ベバンプ外形
巾Aは、A>B−1−2Hの関係が成立する様にほぼ等
方的に成長する。In this case, the bump external width A compared to the photoresist opening width B grows almost isotropically so that the relationship A>B-1-2H holds.
バンブの高さHは半導体装置を外部回路と接続する場合
の接着性、応力の吸収等の理由である−定の値以上が必
要である。従ってバンブの外形中Aをより微細にする為
にはBを小さくする事となり、バンブ自体の強度が低下
する欠点があった0本発明によって形成1〜だバンブの
断面図を第1図、第2図に示した。The height H of the bump needs to be at least a certain value for reasons such as adhesion and stress absorption when connecting the semiconductor device to an external circuit. Therefore, in order to make A in the external shape of the bump more fine, B must be made smaller, which has the disadvantage of reducing the strength of the bump itself. It is shown in Figure 2.
本発明では、バンブの高さHを得る為に、複数回の選択
メッキを行う事で、バンブ強度の低下を防止しつ\バン
プの微細化を計るものである0以下本発明の形成方法を
第1図を用いて順序を追って詳細に説明する。In the present invention, in order to obtain the height H of the bump, selective plating is performed multiple times to prevent a decrease in the bump strength and to make the bump finer. This will be explained in detail step by step with reference to FIG.
まず、従来方法と同様にフォトレジストを能動領域の形
成が終了した半導体基板1に塗布し、公知のフォトエ稈
を用いて開口部Bをあける0しかる後にメッキにより4
−1を形成する。この後再びフォトレジストの塗布を行
い4−1 (7)上部を部分的に開口させ、再びメッキ
をして4−2を形成する。First, as in the conventional method, a photoresist is applied to the semiconductor substrate 1 on which the active region has been formed, and an opening B is made using a known photoresist.
-1 is formed. After that, photoresist is applied again to form 4-1 (7) The upper part is partially opened and plated again to form 4-2.
この様に二度の選択メッキを行い高さHのバンブを形成
すれば、バンブの外形中Aと高さH及びメッキの開口部
の巾Bの関係は、人々B+Hとなり、Aが微細化されて
も、Bを大きくする事ができる。If a bump of height H is formed by performing selective plating twice in this way, the relationship between the bump's outer shape A, height H, and width B of the plating opening becomes B + H, and A is miniaturized. However, B can be made larger.
Bを大きくすればバンブの強度が得られる為に強度の大
きい微細バンブを形成する事ができる。If B is increased, the strength of the bumps can be increased, so that fine bumps with high strength can be formed.
第2図には祈択メッキを3回行って形成したバンブの断
面図を示した。FIG. 2 shows a cross-sectional view of a bump formed by performing selective plating three times.
以上の説明で明らかな様に本発明の方法によれば最初の
バンブ4−1とその」−に形成するバンブ4−2との金
属を変える事も可能であり、又メッキの開口部も変化さ
せてメッキする事もできる。As is clear from the above explanation, according to the method of the present invention, it is possible to change the metal of the first bump 4-1 and the bump 4-2 formed therein, and the plating opening can also be changed. It can also be plated.
本説明ではメッキを2回及び3回でバンブを形成する製
造方法について記述したが、一般に複数回のメッキが行
える事はもちろんである0In this explanation, we have described a manufacturing method in which bumps are formed by plating two or three times, but it is of course possible to perform plating multiple times in general.
第1図及び第2図は本発明によるバンブの断面図、第3
図は従来方法によって形成されたバンブの断面図である
。
1・・・半導体基板
2・・・半導体基板の表面層
6・・・半導体装置の電極
4・・・バンブ
4−1〜4−3・・・バンブの部分を示す。
以 上
出願人 株式会社諏訪精工舎
代理人 弁理士 最上 務
第3図1 and 2 are cross-sectional views of the bump according to the present invention;
The figure is a cross-sectional view of a bump formed by a conventional method. 1... Semiconductor substrate 2... Surface layer 6 of semiconductor substrate... Electrode 4 of semiconductor device... Bumps 4-1 to 4-3... Bump portions are shown. Applicant Suwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami Figure 3
Claims (1)
いて該凸起部を形成するに当りフォトレジストを用いた
選択メッキ工程を複数回行う事を特徴とする半導体装置
の製造方法。1. A method of manufacturing a semiconductor device, which comprises performing a selective plating process using a photoresist multiple times to form a metal protrusion in a semiconductor device having a metal protrusion as an external connection terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58149023A JPS6041235A (en) | 1983-08-15 | 1983-08-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58149023A JPS6041235A (en) | 1983-08-15 | 1983-08-15 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6041235A true JPS6041235A (en) | 1985-03-04 |
Family
ID=15465976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58149023A Pending JPS6041235A (en) | 1983-08-15 | 1983-08-15 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041235A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6481344A (en) * | 1987-09-24 | 1989-03-27 | Toshiba Corp | Bump and formation thereof |
JPS6481345A (en) * | 1987-09-24 | 1989-03-27 | Toshiba Corp | Formation of bump and apparatus therefor |
US5136363A (en) * | 1987-10-21 | 1992-08-04 | Kabushiki Kaisha Toshiba | Semiconductor device with bump electrode |
US7060241B2 (en) | 2001-03-26 | 2006-06-13 | Eikos, Inc. | Coatings comprising carbon nanotubes and methods for forming same |
-
1983
- 1983-08-15 JP JP58149023A patent/JPS6041235A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6481344A (en) * | 1987-09-24 | 1989-03-27 | Toshiba Corp | Bump and formation thereof |
JPS6481345A (en) * | 1987-09-24 | 1989-03-27 | Toshiba Corp | Formation of bump and apparatus therefor |
US5136363A (en) * | 1987-10-21 | 1992-08-04 | Kabushiki Kaisha Toshiba | Semiconductor device with bump electrode |
US7060241B2 (en) | 2001-03-26 | 2006-06-13 | Eikos, Inc. | Coatings comprising carbon nanotubes and methods for forming same |
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