JPS6040071B2 - Method for detecting faulty bits in digital image processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for detecting faulty bits in a digital image processing device.

Unfortunately, the only way to detect faults in this type of equipment is to use an oscilloscope to detect each fault one by one, which is very time consuming.

The present invention distinguishes between faults in the control system and the main line system by looking at faults/gutters from the digital image processing apparatus, and detects fault bits in the digital image processing apparatus that can easily and quickly find fault bits in the main line system. The present invention provides a detection method.

The present invention will be explained in detail below using the drawings.

Digital image processing devices process analog signals by converting them into digital signals of several bits, but as shown in Figure 1, these digital signals are processed bit by bit in parallel, for example, in an A/D converter. In such a case, by using a test signal consisting only of specific bit levels, it is possible to easily determine which bit system is at fault based on the fault pattern that occurs digitally. For example, for a device that divides into 4 bits, a4:1000, a3: which indicates density or color tone,
0100,a2:0010,a. :0001 A portion made up of four levels is created in the test signal. If a fault occurs in a 3-bit system that changes "1" to "0", the value of the third bit in areas other than the a3 level is originally "0", as shown in the upper part of Figure 2a. Therefore, it is not affected by this failure, but since there is information of "1" in the third bit in the a3 level area, this becomes "0", causing a level change to (0000) as shown in the lower part of the figure. . In Figure 2b, the 3-bit system goes from “0” to “1”
This is a diagram showing the case of a failure that changes to
It changes from 00 to “1100”, and the a2 area becomes “0”.
010” to “0110”, and the a and area also change to “00”.
The value changes from 0r to "0101", but since the 3-bit format of the a3 area is "1", it does not change. This causes a level change as shown in the lower part of the figure. By using a test signal having a portion in which only each bit level has been completed in this manner, a faulty bit system can be easily found by knowing in which region a level change is occurring. A display example according to an embodiment of the present invention is shown in FIG.

Castle A, Castle B, Castle C, and D that divide the television screen into four equal parts
The castle levels are 0001, 0010, 0100 respectively.
, 1000, and when a failure occurs, a level change occurs only in a specific area among these four areas, so the failure bit system can be seen from changes in density or color tone. A case will be described in which the test signal used in the present invention is used for testing a television standard format converter as shown in FIG. 4a.

In this device, an input signal is converted into a 4-bit signal by an A/D converter 1, and written into a memory 2 in synchronization with the input synchronization timing. This memory 2 is read out in synchronization with the synchronization timing of the output, and the distortion of the image due to conversion is corrected by the internal D/A circuit 3.
The converter 4 converts it into an analog output signal. Control unit 5
controls each of the above circuits. FIG. 4b shows a configuration example of a control circuit that is a main part of the control section 5.

The horizontal synchronizing signal separated from the input signal by the synchronizing signal separator 5-- is used as a reset pulse for the counter 5-2. The horizontal synchronization signal is set to 57 by the frequency multiplier 5-3.
2. 9.9MHZ sampling pulse Ps
is made. The counter 5-2 is a sampling pulse Ps
The starting point is when the horizontal synchronizing signal is generated, and from this point on, the predetermined number of sampling pulses Ps is counted and generates Hst. Figure 5
4 shows an example of a test signal generator when the present invention is applied to the device of FIG. 4a.

In this case, the test signal generator is used in place of the A/D converter 1. This circuit considers the case where there are 50 fixed sampling points per scan line of the TV signal, and each region is 125 sampling widths as shown in FIG. 125 counter 1-1 generates one pulse every 12 sampling pulses,
As a result, the shift registers 1-2, which have been set to "100" in advance, are shifted, and a level area made up of only each bit is generated.

The Hst pulse is a sampling start signal for each line, and this signal returns the state of the shift register 1-2 to its initial state. That is, in FIG. 5, first, the shift registers 1-2 are set to "100". The 125 counter 1-1 counts the sampling pulse Ps (FIG. 61) from the Hst signal (FIG. 60), When the pulses are counted, one pulse is output and the shift register 12 is set to "010".

Furthermore, the shift register 1-2 is set to "001" by the next output of the 125 counter 1-1.
1". Next, 125 counter 1-1 is set to H.
It is set to "1000" by the st signal, and the above operation is repeatedly executed. The above explanation uses a signal that includes one "1" bit among the "0" bits, but it is also possible to use a signal that includes one "0" bit among the "1" bits. You can also get the same effect.

As explained in detail above, images are information that affects human vision, and whether or not these digital devices are a problem can often be determined by looking at their output images. By using the test signals of the present invention and displaying them as in the present invention, even operators who do not have sufficient knowledge of digital equipment such as TSCs, frame synchronizers, noise reducers, etc. can detect changes in density or color tone in disturbance patterns of output images. Faulty parts can be easily found and maintained. It can also be applied to transmission path tests when general image signals are digitally transmitted.
Furthermore, since the failure situation can be patterned and judged by looking at it, there is an advantage that it is possible to easily discover a plurality of failures in a specific manner and over a wide range.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the device targeted by the present invention, FIGS. 2a and 2b are diagrams for explaining the mode of level change that occurs when a failure occurs, and FIG. 3 is a table of the present invention. A diagram showing an example, FIG. 4a is a block diagram showing the configuration of a TV standard format conversion device as a target device of the present invention, FIG.
b is a block diagram showing a configuration example of a control circuit used in the example of FIG. 4a, FIG. 5 is a block diagram showing a configuration example of a test signal generator used in the present invention, and FIG. 6 is a block diagram showing an example configuration of a test signal generator used in the present invention. It is a time chart for explaining. Box I Figure 3 Figure 5 Figure 6 Figure 2(a) Figure 2(b) Figure 4

Claims (1)

[Claims] 1. In order to search for a fault in a digital image processing device, specific bits that have the same number of bits as the digital signal handled by the digital image processing device and are in a different state from other bits are sequentially selected from high-order digits to low-order digits. A plurality of test signals of a number equal to the number of bits obtained by addressing one bit are sequentially input to the digital image processing device, and each corresponds to the plurality of test signals on the display surface of the digital image processing device. A method for detecting a faulty bit in a digital image processing apparatus, characterized in that a faulty bit in the digital signal is detected by utilizing the fact that each level of a plurality of areas changes according to a fault in the specific bit.