JPH02186444A - Fault detecting system for digital signal processor - Google Patents

Abstract

PURPOSE:To easily estimate a fault generating bit by supplying a digital signal for test to a digital signal processor, passing the output through a cyclic shift circuit, after that, converting the digital signal to an analog signal, and displaying the signal. CONSTITUTION:A frame memory to which a test pattern is written in advance, is built in a test pattern generator 1 and the video signal of 8-bit accuracy is successively read synchronously with a synchronizing signal to be supplied from an external part. The read digital video signal is inputted to a digital signal processor 3. The digital signal processor 3 outputs the inputted digital video signal as it is through a bus which is a checking object in the processor. The outputted video signal is passed through a cyclic multi-digit shifter 2, after that, converted to the analog signal by a digital/analog converter 4 and displayed on a TV monitor 5.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a fault detection method effective for adjusting and detecting faults in digital signal processing devices, and particularly in digital video signal processing devices.

(Prior art) Like a digital video signal, the clock frequency is 1.
In manufacturing a device that handles high-speed signals of 0 MHz or higher, adjustments such as phase alignment between data and clock and bus impedance matching are required in order to eliminate data transfer errors. -Generally, these operations are performed using measurement equipment such as an oscilloscope to observe the signal waveform and make adjustments to obtain the optimal waveform. However,
If a transfer error occurs due to a defective IC or crosstalk, it is difficult to find the location of the failure just by observing individual digital signal waveforms. In such cases, it is often more efficient to display the output digital video signal on a TV monitor and directly monitor the output screen. Therefore, when adjusting a video signal processing device, first, the video signal output to the TV monitor is observed to estimate the fault location, and then measurement equipment such as an oscilloscope is used to make detailed adjustments and circuit corrections. It is being

In general, failures in digital signal processing equipment include static failures in which signals are fixed at high or low levels due to broken wiring on printed circuit boards, and operational failures such as crosstalk and shorts between signal lines. There are dynamic faults that are detected. If the former static fault occurs on the image data bus, the gradation of the image signal will drop, and this will be observed as a false contour on the TV monitor screen, making it possible to detect the fault. However, when a fault occurs in the bit of LSBfl,l], it is difficult to detect a false contour just by observing the monitor screen. Furthermore, it is not possible to specify which bit has a fault. On the other hand, in the case of a dynamic failure such as the latter, errors that occur in the image data are random, so they are observed as impulsive noise on the monitor screen.

However, even in this case, it is difficult to detect when the faulty bit is on the LSB side, and it is also impossible to specify which bit is faulty.

(Problems to be Solved by the Invention) As described above, since fault detection using a TV monitor becomes difficult depending on the bit position where the fault occurs, there is a risk that the occurrence of the fault may be overlooked. Furthermore, even if a fault can be detected, the position of the bit where the fault has occurred cannot be specified, so there is a problem in that it takes time to find a correction location. Therefore, an object of the present invention is to make it possible to detect a fault in a signal processing device using a TV monitor or the like, regardless of the bit position where the fault occurs, thereby improving the efficiency of adjusting and correcting the device. There is.

(Means for Solving the Problem) To this end, the present invention provides a test pattern generating means for supplying a test digital signal to a digital signal processing device, a cyclic shift circuit for cyclically shifting the output of the digital signal processing device, and a cyclic shift circuit for cyclically shifting the output of the digital signal processing device. , provides a failure detection method comprising a digital-to-analog converter for converting the output of the cyclic shift circuit into an analog signal, and means for displaying the output of the digital-to-analog converter.

(Function) As mentioned above, the problem with detecting a fault using a TV monitor is that when a fault occurs on the LSB side of a digital signal, it is difficult to detect visually.

In other words, if a fault always appears in the MSH, the brightness value of the error pixel will show a change close to brightness reversal, making detection easier. Therefore, in the present invention, bit manipulation is performed when displaying on a monitor screen, and designated bits of the output of the signal processing device are converted into digital-to-analog conversion as MSB.

Further, the test pattern generator can stably and repeatedly generate a specific digital test pattern, thereby making visual failure detection easier.

(Embodiment) FIG. 1 shows an embodiment of a real-time video processing device according to the present invention. In the figure, 1 is a digital test pattern generator, 2 is a cyclic multi-digit shifter, 3 is a digital signal processing device for adjustment, 4 is a digital-to-analog converter,
5 is a TV monitor.

The test pattern generator 1 has a built-in frame memory in which a test pattern is stored in advance, and sequentially reads out an 8-bit precision video signal in synchronization with a synchronization signal supplied from an external source (not shown). The read digital video signal is input to the digital signal processing device 3. The digital signal processing device 3 directly outputs the digital video signal input via the bus to be verified within the device. After the output video signal passes through the multi-digit shifter 2,
The signal is converted into an analog signal by the digital-to-analog converter 4 and displayed on the TV monitor 5.

The cyclic multi-digit shifter operates based on the logic table shown in FIG. In FIG. 2, three control signals s2. s1.
When so is all low level (= "ooo"), 8-bit output data Y = (y7y6y5y4
ya y2y1yo) is 8-bit input data A =
(a7 a5 a5 a4 a3 a2 a 1aO
) has the same bit order. Therefore, the MSB of the output signal
The MSB (a7) of the input signal is output as is at (y7). Furthermore, when s2+s1+"0 are all at high level (="111"), the LSB (a
o) is output as the output MSB (y7). In this way, the 3-bit control signal S2 (s2.sl, s□)
Depending on the value of , arbitrary bits of a7 to aQ of the input signal are output as the MSB of the output. A cyclic multi-digit shifter with such a function is described in the 1985 edition of Bipolar Microprocessor Logic and Interface, a data book by Advanced Micro Devices, Inc., 9-32.
It can be configured using Am25S10 described in Sections 9-37. The 8-bit cyclic shifter is Am25S1.
The logic operation that can be configured using four 0s and shown in Figure 2 is as follows.
It is realized using the same circuit configuration as described as an application example in Section 9.35 of the same data book.

Next, an example of the structure of image data generated from the test pattern generator 1 will be described. Since the output video signal is bit-manipulated by the multi-digit shifter 2 and then output to the TV monitor 5, it is convenient that the image after the cyclic shift is a bang that can be easily inferred. Here, as shown in Figure 3,
10101010'"("AA"' in hexadecimal) and '01
An image signal consisting of only two types of pixel values: 010101"("55" in hexadecimal) is given as a large kabatan. At this time, when the cyclic shift amount is an even number, the signal generated from the test pattern generator 1 is If the image data is input to the multi-digit shifter 2 without deterioration, the luminance value of the background part and the luminance value of the graphic area do not change, so the image data after cyclic shift is the same as the input. As long as there is no failure, the output of the multi-digit shifter 2 will be the same as the output of the test pattern generator 1.On the other hand, when the cyclic shift amount is an odd number,
"10101010'" becomes '01010101', "
'01010101' is converted to '10101010', so if no fault has occurred, the test pattern generated by test pattern generator 1 is a signal in which the luminance values of the background area and figure area are exactly swapped. It is obtained as the output of the multi-digit shifter 2. However, regardless of whether the shift amount is an even number or an odd number, the difference in luminance value between the background area and the graphic area is the same.

Here, if a certain bit of the output video signal is fixed at high level or low level due to a failure in the signal processing device 3, the difference between the background area and the graphic area depends on the cyclic shift amount of the multi-digit shifter 2. Fluctuations occur in the difference in brightness values.

In particular, when the fault occurrence bit is selected as the MSB of the output of multi-digit shifter 2, the MSB of the luminance of the background area and graphic area
Since B is the same, the difference in brightness values between the two becomes extremely small. Therefore, it may be assumed that a fault has occurred in the bit selected as the MSB at this time.

Furthermore, even for dynamic disturbances such as crosstalk, it is possible to estimate the faulty bit because impulsive noise is most frequently observed when the focal point where the fault occurs is selected as the MSB. becomes.

In this way, by selecting the shift amount of the multi-digit shifter 2 while observing the output TV monitor screen, it becomes easy to estimate the faulty bit. Furthermore, if the digital test pattern of the test pattern generator 1 is configured to be rewritable, it becomes possible to update the test pattern based on the results of estimating the location of the fault, which is necessary for identifying the detected fault location and elucidating the cause. You can get detailed information.

(Effects of the Invention) According to the present invention, it is possible to easily detect a fault regardless of the bit position where the fault has occurred, and to improve the detection efficiency. Furthermore, by observing the output image while changing the shift amount setting, it becomes easy to identify the faulty bit position.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIGS. 2 and 3 are diagrams for explaining the operation of the embodiment. In the figure, l is a test pattern generator, 2 is a multi-digit shift circuit, and 3 is a test pattern generator.
is a digital signal processing device; 4 is a digital-to-analog converter; and 5 is a TV monitor.

Claims (1)

[Claims] This method detects a failure by monitoring the multivalued digital output of a digital signal processing device, the method comprising: a test pattern generating means for supplying a test digital signal to the digital signal processing device; A fault detection system comprising: a cyclic shift circuit that performs cyclic shifting; a digital-analog converter that converts the output of the cyclic shift circuit into an analog signal; and means for displaying the output of the digital-analog converter.