JPS6039959A - Data block transmission system - Google Patents

Abstract

PURPOSE:To improve the transmission efficiency by transmitting three consecutive data while adding a 1-byte BS code to the head of the data in the system having a 1-byte block size code to the head of the data. CONSTITUTION:The 1st block size code BS7 of an input signal is detected by a BS code detector 15 and when three data being <=4 bytes are consecutive, a comparator 24 generates a pulse to clear a counter 23 and gives the pulse to memories 19, 28 and a BS coder 26. The BS code forming device 26 forms the 2nd block code 30 representing a special block and transmits the code to an output device 29. The input/output device 29 transmits data while adding the 2nd BS code 30 transmitted at the head of the data 2, 4 and 6.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention provides that each time the information type of data differs, a 7°1 byte indicating the number of bytes of the data and that it is a block is added to the beginning of the data. (b) Prior art and problems related to a data block transmission system that can improve transmission efficiency in relation to a data block transmission system with a block size code of 1. Figure 1 is a transmission code format diagram of a conventional data block transmission system. FIG. 2 is a format diagram of the first block size code of FIG.

1.3.5.7 in the figure. 'J, 11 is the first proxize code area, 2, 4, 6, 8, 10.12 is data, 13 is an area indicating a block, and 14 is a byte number area indicating the number of bytes of data.

The information types of data 2 and 4, the information types of data 4 and 6, the information types of data 6 and 8, and the information types of data 8 and 10 in Figure 1 The information types of data 10 and 12 are different. . The types of data include, for example, simple information, information necessary within the system such as traffic flow, shift traffic, etc., and terminal break signals.

In the conventional data block transmission method, as shown in FIG. A code indicating that it is a block and a code indicating the number of bytes of data are written in the clock size code area and transmitted. For example, if the number of bytes of data 2υ) is 4, the first clock size code area 1 will contain the data as shown in FIG.

The 2-bit value is 0 in area 13, which indicates the value of 1 note.
0 in the 6-bit byte number area 141C4 or 0001.
Write 00. However, in this method, the data is 1
Even if it is a byte, the first clock size code area is provided at the beginning of the byte, which has the disadvantage of poor transmission efficiency.

tc+ OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, an object of the present invention is to provide a data block transmission method that can improve transmission efficiency.

(dl) Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a first norosocnization code; J8-bit configuration, of which 2 bits indicate block size, and can express 4 types of data. The area indicating the number of bytes is 6 bits, and if this is divided into three parts of 2 bits each, the number of bytes up to 4 bytes can be expressed in each division. In this case, the destination of these three consecutive pieces of data @l
This 1-byte second block size code includes a predetermined code indicating that the block is a special block and a code indicating the number of bytes of each of the three consecutive data blocks. The data transmitting side is characterized by a means for scraping the data so as to prevent the transmission from occurring.

(0) Examples of the invention The following is an example of the present invention. This will be explained according to the diagram.

Fig. 3 is a block diagram of a circuit for creating a transmission code format of the Cheetab n Tsuk transmission power type according to the embodiment of the present invention, and Fig. 4 is a transmission code format diagram of the data block transmission system of the embodiment of the misfire I'll. , FIG. 5 shows the format of the second block size code (hereinafter referred to as [-BS code) in FIG.

15 is a BS code detector, 16.23f'i cow 717,
17 and 24 are comparators, 18 are delay circuits, 19 and 28 are memories, 20 and 22 are node circuits, and 21 is a not circuit.

251 tffl a circuit, 26 a BS code generator, 29 an output device, knee 301: J second BS code area, 31 an area indicating a special block, 32, 33, and 34 the number of bytes of each data. This is the area shown.

2.4.6.8.10 of the code format shown in Figure 1.
are respectively 1 byte, 3 bytes, 1 byte, and 4 bytes.

The following explanation is based on the 5-byte format. Also No. 10)
BS code area j, 'edited, 5.7.9.11 (:1
Since the number of bytes (prosocization) of the next data is written in each, the first BS code will be called hereinafter.

Matsu J3', :, j: The door detector 151 detects the first BS code 1 and emits two pulses to clear the counter I6. From then on, the counter 16 outputs every byte of the input signal. The counting of the number of 5M5-CIs continues until the BS code detector 15 detects the first BS code 3, emits a pulse, and clears the h counter 16. This counting result 4 (
20 bytes of data) are sent to the comparator 17 and memory 19. The comparator 17 compares the counting result 4 with the pulse 4 which is slightly delayed by the delay circuit 18 when the BS code 3 of the audience is detected, and calculates the output level by the output level. (The comparator 17 uses the counting result as a level when there is no output level below 4, and a level from 5 or above from l, 1 to O level.) By becoming a level, the first BS code 3 is detected. The pulse passes through the AND circuit 20 and is sent to the counter 23, and the counter 23 counts this pulse +.

The counting result 1 is always output, and the value of u-3 is compared with the comparator 24. (The comparator 24 is sent <<) and the counting result is 3.
ζWhen this happens, a pulse is outputted to the memory 19. When the first BS4: i- number 3 is detected (Tsuku pulse 7) (when it comes, it is sent C and the counted result 4 is sent =, 1) 1. - The 10th DBS code 1 of the universal signal is deleted by the BS code deleter 27 and data 2 is inserted into the memory 1/28i. The same operation as above is performed when the BS code detector 15 detects the first 133 code 7.
Continue until it detects and emits a pulse. When the first BS code 7 is detected and a pulse is emitted, the count result of the counter 23 is 3 and 7. , 28. is sent to the BS code generator 26. When this pulse arrives, it is stored in the memory J9 (・1 take 2.4.
The IBS code-5 generator 26 generates a second BS code as shown in FIG. That is, it must be a special block.B6, for example, 01 is written in area 31 indicating 2, and areas 32 and 3 are written with the number of bytes of data.
3゜34 was sent/Ko2l-Itta2. -1.6
! Write υ number of bytes 4°3.1. This, /′-ri′]
) As for the number of bytes/0 representation, for example, 1 byte is 00,2
by) '<' OL, 10.4 pies for 3 bytes (・
As in 11 < 1-7. , the second BS code produced in this way as shown in FIG. 5 is sent to the output device 29. On the other hand, data 2.4.6 is stored in the memory 28 when the above pulse arrives.
is stored, and this data 2.4.6 is sent to the output device 29.
1. The output device 29 outputs the second BS code (30) sent at the beginning of the data 2.4.6 as a transmission format shown in FIG. .

Next, when the BS code detector 15 detects the first BS code 9 and emits a pulse, the counting result 4 (number of bytes of data 8) of the counter 6 is written to the memory 19 by the same operation as described above. It is included.

Further, the count value of the counter 23 is l. Also memo 92
When the missing BS code detector 15 detects the first BS code 11 and emits a pulse, the counting result of the counter 6 is 5 (data 10). Since the output of the comparator 17 becomes O level, the output of the NOT circuit 21 becomes a level, and the above pulse passes through the AT circuit 22 and clears the counter 23/. The number of bytes of data 8, 1o is 4.5 stored in the memory 19 at this point, and this number of bytes 4, 5 is sent to the BS code generator 26. BS code generator At 26, the same first BS code 7.9 as before is created and sent to the output device 29.On the other hand, when the above pulse arrives at the memory 28,
Data 8, 1o are stored, and this data 8, 10
is sent to the output device 29. In the output device 29, each data 8, 10
The first BS code 7.9 is added to the beginning of the message and output in the transmission format shown in FIG.

As mentioned above, when there are 3 consecutive pieces of data of 4 bytes or less, a 1-byte second
Since the BS code is encoded and transmitted, the BS code area is reduced compared to the conventional case, and the transmission efficiency can be improved.

That is, when m pieces of data of 4 bytes or less are consecutive, 2 x J n BS code areas are reduced. However, J
n=(m/3) and is the largest integer that does not exceed m/3.

(f) Effects of the Invention As explained in detail above, according to the present invention, only one BS code is required for three pieces of consecutive 4-bar data or less, so the BSn number area is reduced and the transmission time is reduced. It has the effect of improving efficiency.

[Brief explanation of the drawing]

FIG. 1 is a transmission code format diagram of the conventional data block transmission method, FIG. 2 is a format diagram of the first block size code in FIG. 1, and FIG. 3 is a diagram of the data block transmission method of the embodiment of the present invention. A block diagram of a circuit for creating a transmission code format, FIG. 4 is a transmission code format diagram of a data block transmission method according to an embodiment of the present invention, and FIG. 5 is a second proxize code format diagram of FIG. 4. . In the figure, 1.3.5.7.9.11 is the first block size code area, 2, 4.6, 8, 10.12 is data, and 13
．． ;(1 is the area indicating that it is a block,], 4,
32, 33.34 is the Hyde number area of data, 15iJ block size sign detector, 16.23 is non-counter, 1
7.24 is a comparator, 18 is a delay circuit,] 9, 28i;
t memory, 2o. 22 is an AND circuit, Hrt not circuit, 25 is an OR circuit, 26 is a prosecution tq=creator, 29 is an output device,
30 indicates the second block 1 noise mark flash area. Agent: Patent Attorney Hiroshi Matsuoka [7,,;+ 4 Figure 5

Claims (1)

[Claims] In a data block transmission method where each data type has a first block size code indicating the number of bytes of the data and the block, m pieces of consecutive data of n bytes or less are placed at the beginning of the data. In this case, a second block size code is provided at the beginning of the m consecutive data, and the second block size code includes a code indicating that it is a special block and the number of bytes of each of the m consecutive data. 1. A data block transmission system characterized in that a data transmitting side is provided with means for providing a code indicating the .