JPS5563153A - Error detection system for digital communication equipment - Google Patents

Abstract

PURPOSE: To secure the detection for the 1/3 errors occurring in an equi-probability way be counting the pulse number of the pulse row supplied to the transmitter within a fixed section and then adding the different parity bits in the case of the multiples of 3 and otherwise respectively.

CONSTITUTION: For transmitter 10' of the digital communication equipment of the differential phase modulation system, pulse row 9 of N-bit is converted into the N+ 1-bit row through 1-bit addition circuit 11, and the pulse number of pulse row (a) is counted by ternary counter 17. Counter 17 delivers the parity P bits of 1 and 0 incase the pulse number is then multiple of 3 and in other cases respectively to be inserted into the last one bit of the N+1-bit pulse row at P-bit insertion circuit 13. This pulse row is then converted into two series to be transmitted after 4-phase modulation 16, and then demodulated 21 at transmitter 20' to be converted into the pulse row of N+1-bit. And the first N-bit pulse row is counted by ternary counter 27, and the output P' of gate 28 turns to 1 and 0 when the pulse number is the multiple of 3 and otherwise respectively to be compared with the last bit P of the output signal. Thus the error is detected.

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