JPH04111636A - Error correction system - Google Patents

Abstract

PURPOSE:To reduce number of coders and decoders and to decrease the circuit scale by converting a data signal whose code speed is (f) into a data signal whose code speed is f.n/m and converting the data signal whose code speed is f.n/m into a data signal whose code speed is (f). CONSTITUTION:A data signal 12 coded by an error correction coder 101 at a sender side is converted into data signals 131-13m whose code speed is f/m by a 1st conversion circuit 102 and a modulator 103 modulates them as a modulation signal 14. On the other hand, a reception signal at a receiver side is demodulated by a demodulator 104 and each of data signals 151-15m whose code speed is f/m is converted into a data signal 16 whose code speed is (f) by a 2nd conversion circuit 105. The data signal 16 whose code speed is converted into the speed (f) is given to a decoder 106, from which the data subject to error correction decoding is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error correction system in a digital microwave communication system using a 2mQAM or 2mPSK communication system.

[Prior Art] FIG. 2 shows an example of an error correction system in a conventional digital microwave communication system. On the transmitting side, the first conversion circuit 201 converts the input data signal 21 with a code rate f (bits/second, the same applies hereinafter) into m-column signals with a code rate f/m, and converts the input data signal 21 into m-column signals with a code rate f/m, and converts the input data signal 21 into m-column signals with a code rate f/m. Output. Also, m error correction encoders 202I to 2o2. are the input data 22° to 22. ．． ．． A redundant bit for error correction is added to the encoded data signal 23. ~23. Output. Modulator 203 modulates the input signal and sends out a modulated signal.

On the receiving side, demodulator 204 receives the modulated signal and outputs the demodulated signal. m error correction decoders 205I-2
05. is the input signal 25. Error correction is performed for 25 degrees, and decoded data signals 26 to 26 degrees are output. The second conversion circuit 206 receives m columns of input signals 26 .
.about.26i is converted into one column of data signal 27 at code rate f.

[Problem B to be Solved by the Invention] In the conventional error correction method described above, the transmitting side converts the signals into m sequences, and then performs error correction encoding on each signal, and the receiving side converts each signal into m sequences of signals. Since error correction decoding is performed on m error correction encoders 202 .
~202. Therefore, m decoders 2051 to 205# are required, resulting in a problem that the circuit scale increases.

An object of the present invention is to provide an error correction method that reduces the number of error correction encoders and decoders to reduce the circuit scale.

[Means for Solving the Problems] The error correction method of the present invention provides a signal having a coding rate f (bits/second, hereinafter the same) of n columns (n is a natural number of 1 or more and less than m) on the transmitting side. n error correction encoders using block codes that output A first conversion circuit for converting into data and means for modulating and transmitting the output signal of the first conversion circuit are provided.

Further, on the receiving side, means for receiving and demodulating the signal;
A second conversion circuit that converts the demodulated m-column signals into n-column data at a speed f, and an error correction decoder that decodes the output signal of the second conversion circuit are provided.

In the most advantageous embodiment of the invention, n is configured to be 1.

[Effect]

According to the present invention, the number of encoders and decoders can be comprised of n, which is less than m, thereby reducing the number of these components and reducing the circuit scale.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the error correction method of the present invention. In the figure, T indicates the transmitting side and R indicates the receiving side. The transmitting side T has n error correction encoders 101 (n is a natural number greater than or equal to 1 and less than m, here n-1), and this encoder 101 adds redundant bits for error correction to the input data signal 11. and outputs an encoded data signal 12 at a code rate f (bits/second, hereinafter the same). Further, the encoder 10
1 is connected to the first conversion circuit 102, which converts the input signal 12 with the code rate f to the code rate f-n/m (n in this example).
= 1, so it is converted into a signal of f/m), and m-column encoded data signals 13. ~13, is output. Furthermore, it has a modulator 103, which modulates each input signal and sends out a modulated signal.

The receiving side R has a demodulator 104, and the demodulator 1
04 demodulates the received modulated signal and outputs a demodulated signal. A second conversion circuit 105 is connected to the demodulator 104, and this second conversion circuit 105 has a code speed of f/m.
input signals 15+ to 15 are converted into data signals having a code rate f. Furthermore, it has n (here, one) error correction decoders 106, which perform error correction on the input signal 16 and output a decoded data signal 17.

According to this configuration, on the transmitting side, the error correction encoder 101
The data signal 12 encoded by the first conversion circuit 102 converts the data signal 13 . ~13
5 and sent out as a modulated signal 14 by the modulator 103.

On the other hand, on the receiving side, the received signal is demodulated by the demodulator 104, and each data signal 15+ to 15 at the code rate f/m is
．． is converted by the second conversion circuit 105 into a data signal 16 having a code rate f. The data signal 16 converted to the code rate f is subjected to error correction decoding by the error decoder 106 to obtain data.

In addition, although the example in which n=1 is shown in the above embodiment, it can be realized in the same way when n is 2 or more. In this case, encoder 1
In addition to arranging n decoders 106 in parallel, the first conversion circuit 102 converts a data signal with a code rate f into a data signal with a code rate f·n/m,
It goes without saying that the second conversion circuit 105 converts a data signal with a code rate f-n/m into a data signal with a code rate f.

Therefore, with this configuration, error correction similar to that of the conventional system shown in FIG. 2 can be achieved by using only one encoder and one decoder, and the number of component parts can be reduced to reduce the circuit scale. Even when n is 2 or more, it never becomes more than m, so it goes without saying that the circuit scale can be reduced.

〔Effect of the invention〕

As explained above, the present invention allows an error correction system to be configured with n encoders and decoders, which is less than m, so it is possible to reduce the number of these encoders and decoders, and the circuit size can be reduced. It has the effect of being able to be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an error correction method according to the present invention, and FIG. 2 is a block diagram of a conventional error correction method. 101...Error correction encoder, 102...First conversion circuit, 103...Modulator, 104...Demodulator, 10
5... Second conversion circuit, 106... Error correction decoder, 201... First conversion circuit, 2021-2o2. %
... encoder, 203 ... modulator, 204 ... demodulator, 205, ~205. ...Decoder, 206...Second conversion circuit.

Claims (1)

[Claims] 1. In a digital microwave communication system in which a transmission signal is transmitted by 2^mQAM or 2^mPSK (m is a natural number of 2 or more), there are n columns (n is a natural number of 1 or more and less than m) on the transmitting side. ), n error correction encoders using block codes that output signals at a code rate f (bits/second, the same applies hereinafter);
The output of this encoder is expressed as m for each m encoded blocks.
A first conversion circuit that separates the column into binary signals and converts them into data at a speed of f·n/m, and a means for modulating and transmitting the output signal of this first conversion circuit are provided, and the receiving side means for receiving and demodulating signals, a second conversion circuit for converting the demodulated m-column signals into n-column data at a speed f, and an error correction decoder for decoding the output signal of the second conversion circuit. An error correction method characterized by providing the following. 2. The error correction system according to claim 1, wherein n is 1.