JPS6190545A - Pcm communication system - Google Patents
Pcm communication systemInfo
- Publication number
- JPS6190545A JPS6190545A JP59212115A JP21211584A JPS6190545A JP S6190545 A JPS6190545 A JP S6190545A JP 59212115 A JP59212115 A JP 59212115A JP 21211584 A JP21211584 A JP 21211584A JP S6190545 A JPS6190545 A JP S6190545A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- signal
- bits
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4915—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using pattern inversion or substitution
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- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 本発明はPCM通信方式に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a PCM communication system.
PCM通信方式において伝送路に信号を送出する場合、
伝送路符号としては、受信側でタイミング抽出が容易で
ある、回路構成が簡単である等の理由から、″l#と@
0”の発生確率がほぼ等しく一定の直流成分が保たれる
いわゆる平衡符号が望ましい。この様な符号を得る為に
、従来、情報信号とM系列信号発生器出力との排他的論
理和を伝送路信号としていた。When sending signals to the transmission path in the PCM communication method,
As transmission path codes, "l#" and @
It is desirable to use a so-called balanced code in which the probability of occurrence of "0" is approximately equal and a constant DC component is maintained.To obtain such a code, conventionally, an exclusive OR of an information signal and the output of an M-sequence signal generator is transmitted. It was used as a road signal.
この従来方式について第1図を用いて説明する。This conventional method will be explained using FIG. 1.
1は情報信号の加えられる六方端子で、この情報信号は
伝送路に送出される前に速度変換回路2で余剰ビットを
付加される。Reference numeral 1 denotes a hexagonal terminal to which an information signal is added, and surplus bits are added to this information signal by a speed conversion circuit 2 before being sent out to the transmission path.
速度変換後の信号は端子3に゛加えられるリセットパル
スにより一定周期毎にリセットされるM系列発生器4の
出力によ〕排他的論理和回路5で変調を受は伝送路信号
として伝送路に送出される。The signal after speed conversion is modulated by the exclusive OR circuit 5 (by the output of the M-sequence generator 4, which is reset at regular intervals by a reset pulse applied to the terminal 3), and then sent to the transmission line as a transmission line signal. Sent out.
この場合の伝送路信号は、比較的長い時間にわたってみ
た場合61#と@0”の発生確率がほぼ同程度の信号と
なハそのマーク率ははi1!′/2となる。しかし、リ
セットパルス周期程度の短期間では入力信号によっては
同符号連続の生じる場合があり、受信側でタイミング抽
出が困難となった〕、直流成分の変動によって識別マー
ジンが劣化することがある。また本方式では連続する同
符号数は確率的にしか把握できない。また全て同符号と
なることも確率的には在り得る。In this case, the transmission line signal is a signal in which the occurrence probabilities of 61# and @0'' are almost the same over a relatively long period of time, and the mark rate is i1!'/2. However, the reset pulse Depending on the input signal, the same sign may occur continuously over a short period of time, making it difficult to extract the timing on the receiving side], and the discrimination margin may deteriorate due to fluctuations in the DC component.Furthermore, in this method, continuous The number of identical signs that occur can only be determined probabilistically.Also, it is possible that they all have the same sign.
本発明の目的は、従来回路の欠点を改善し最悪の同符号
連続を一定値に保ちタイミング抽出等を容易にすること
が可能なPCM通信方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a PCM communication system that can improve the shortcomings of conventional circuits and can keep the worst case of the same code sequence at a constant value and facilitate timing extraction.
甲発讐つ嘴截→〔実施例〕
本発明の実施例について第2図を用いて説明を行う。1
1は情報信号の加えられる入力端子、12は速度変換回
路でその出力は同一極性信号計数回路13と排他的論理
和回路14に加えられる。速度変換回路12は入力端子
11に加えられる情報信号に余剰と、トを挿入するが、
余剰と、トは、情報と、トnビット毎に挿入されるもの
と、受信側でフレーム同期を取ることが可能な様に送信
側から送出するフレームパルスを挿入する為のものに分
けられる。[Embodiment] An embodiment of the present invention will be described with reference to FIG. 2. 1
1 is an input terminal to which an information signal is applied; 12 is a speed conversion circuit whose output is applied to a same polarity signal counting circuit 13 and an exclusive OR circuit 14; The speed conversion circuit 12 inserts a surplus into the information signal applied to the input terminal 11,
The surplus is divided into information, inserted every n bits, and inserted for frame pulses sent from the transmitting side so that frame synchronization can be achieved on the receiving side.
同一極性信号計数回路13は速度変換回路出力の情報ビ
ットとM系列発生器15の出力をnビット毎に予め比較
し両信号の排他的論理和を取った後の信号中にmビット
以上の連続した同一極性信号が含まれることが予測され
る場合、排他的論理和回路14に接続されているゲート
回路16に禁止信号17を送出しM系列発生回路出力1
8が排他的論理和回路14に加えられるのを禁止する。The same polarity signal counting circuit 13 compares the information bits of the speed conversion circuit output and the output of the M-sequence generator 15 every n bits in advance, and after taking the exclusive OR of both signals, the signal contains m or more consecutive bits. If it is predicted that a signal of the same polarity is included, the inhibition signal 17 is sent to the gate circuit 16 connected to the exclusive OR circuit 14,
8 is prohibited from being added to the exclusive OR circuit 14.
即ち情報信号とM系列の排他的論理和の取られることを
禁止する為情報信号が伝送路信号となる。In other words, the information signal becomes the transmission line signal to prohibit the exclusive OR of the information signal and the M sequence.
同一極性信号計数回路13の出力は余剰ビット制御回路
19に接続され、本回路は排他的論理和回路14の出力
のnビット毎に挿入される余剰ビットにM系列と情報信
号の排他的論理和を取らなかったことを情報として付与
する。M系列発生器15に入力端子20を介し加えられ
るリセットパルス周期はフレーム同期パルス周期または
nビット周期等にする。The output of the same polarity signal counting circuit 13 is connected to the surplus bit control circuit 19, and this circuit performs exclusive OR of the M sequence and the information signal on the surplus bits inserted every n bits of the output of the exclusive OR circuit 14. Add information that it was not taken. The reset pulse period applied to the M-sequence generator 15 via the input terminal 20 is a frame synchronization pulse period, an n-bit period, or the like.
本発明くよれば、情報ビットブロック長n、同−極性信
号数m、M系列発生器リセ、ト周期を適当に選ぶことに
より伝送路信号として連続した同一極性信号を一定数以
下に押さえることが可能となる。According to the present invention, by appropriately selecting the information bit block length n, the number m of same-polarity signals, and the M-sequence generator reset period, it is possible to suppress the number of consecutive same-polarity signals as transmission path signals to below a certain number. It becomes possible.
第1図は従来例を示すブロック図、第2図は本発明の実
施例を示すブロック図である。
l・・・・・・情報信号入力端子、2・・・・・・速度
変換回路、3・・・・・・リセットパルス入力端子、4
・・・・・・M系列発生器、5・・・・・・排他的論理
和回路、11・・・・・・情報信号入力端子、12・・
・・・・速度変換回路、13・・・・・・同一極性信号
計数回路1.14・・・・・・排他的論理和回路、15
・・・・・・M系列発生器、16・・・・・・ゲート回
路、17・・・・・・禁止信号、18・・・・・・M系
列発生回路出力、19・・・・・・余剰ビット制御回路
、21・・・・・・リセットパルス入力端子。
代理人 弁理士 内 原 音
華 l 図
$ 2 図FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. l...Information signal input terminal, 2...Speed conversion circuit, 3...Reset pulse input terminal, 4
...M sequence generator, 5...Exclusive OR circuit, 11...Information signal input terminal, 12...
... Speed conversion circuit, 13 ... Same polarity signal counting circuit 1.14 ... Exclusive OR circuit, 15
...M sequence generator, 16...Gate circuit, 17...Prohibition signal, 18...M sequence generation circuit output, 19... - Surplus bit control circuit, 21...Reset pulse input terminal. Agent Patent Attorney Onka Uchihara l Figure $ 2 Figure
Claims (1)
の排他的論理和を第一の伝送路信号として送出する手段
と、速度変換された入力信号の連続したnビット毎のブ
ロックを監視してこのnビットとM系列信号のnビット
との排他的論理和がmビット以上の連続した同一極性信
号を含んでいるブロックはそのまま第二の伝送路信号と
して送出し、速度変換により得られた挿入ビットに変調
の有無の情報を付与する手段とを有することを特徴とす
るPCM通信方式。means for transmitting the exclusive OR of the speed-converted input signal sequence and the output of the M-sequence signal generator as a first transmission line signal; Blocks in which the exclusive OR of n bits of the lever and n bits of the M-sequence signal contains continuous signals of the same polarity with m or more bits are sent as is as the second transmission line signal, and the block is obtained by speed conversion. A PCM communication system comprising: means for adding information on the presence or absence of modulation to inserted bits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59212115A JPS6190545A (en) | 1984-10-09 | 1984-10-09 | Pcm communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59212115A JPS6190545A (en) | 1984-10-09 | 1984-10-09 | Pcm communication system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6190545A true JPS6190545A (en) | 1986-05-08 |
Family
ID=16617121
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59212115A Pending JPS6190545A (en) | 1984-10-09 | 1984-10-09 | Pcm communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6190545A (en) |
-
1984
- 1984-10-09 JP JP59212115A patent/JPS6190545A/en active Pending
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