JPS6190545A - Pcm communication system - Google Patents

Abstract

PURPOSE:To attain ease of timing extraction by selecting properly an information bit block length (n), the same polarity signal (m), and an M-series generator reset period to suppress the consecutive same polarity signals as transmission line signals to a prescribed number or below. CONSTITUTION:A speed conversion circuit 12 inserts an excess bit to an input information signal. A same polarity signal counter circuit 13 compares an output information bit of the circuit 12 with an output of the M series generator 15 at each n bits in advance, and when it is estimated that consecutive same polarity signals of >=m bits are included in a signal after both signals are exclusively ORed through the comparison between an output information bit of the circuit 12 and an output of the M series generator 15 at each n bits in advance, an inhibition signal 17 is transmitted to a gate circuit 16 to inhibit an output 18 of the M series generating circuit from being fed to an exclusive OR circuit 14. The output of the circuit 13 is given to an excess bit control circuit 19, and this circuit gives it to an excess bit inserted at each n bits of the output of the circuit 14 as the information that the M series and the information signal are not exclusively ORed. The reset pulse period fed to the M series generator 15 via an input terminal 20 is used as the frame synchronizing pulse period or the n-bit period.

Description

[Detailed description of the invention] 〔Technical field〕 The present invention relates to a PCM communication system.

[Prior art]

When sending signals to the transmission path in the PCM communication method,
As transmission path codes, "l#" and @
It is desirable to use a so-called balanced code in which the probability of occurrence of "0" is approximately equal and a constant DC component is maintained.To obtain such a code, conventionally, an exclusive OR of an information signal and the output of an M-sequence signal generator is transmitted. It was used as a road signal.

This conventional method will be explained using FIG. 1.

Reference numeral 1 denotes a hexagonal terminal to which an information signal is added, and surplus bits are added to this information signal by a speed conversion circuit 2 before being sent out to the transmission path.

The signal after speed conversion is modulated by the exclusive OR circuit 5 (by the output of the M-sequence generator 4, which is reset at regular intervals by a reset pulse applied to the terminal 3), and then sent to the transmission line as a transmission line signal. Sent out.

In this case, the transmission line signal is a signal in which the occurrence probabilities of 61# and @0'' are almost the same over a relatively long period of time, and the mark rate is i1!'/2. However, the reset pulse Depending on the input signal, the same sign may occur continuously over a short period of time, making it difficult to extract the timing on the receiving side], and the discrimination margin may deteriorate due to fluctuations in the DC component.Furthermore, in this method, continuous The number of identical signs that occur can only be determined probabilistically.Also, it is possible that they all have the same sign.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a PCM communication system that can improve the shortcomings of conventional circuits and can keep the worst case of the same code sequence at a constant value and facilitate timing extraction.

[Embodiment] An embodiment of the present invention will be described with reference to FIG. 2. 1
1 is an input terminal to which an information signal is applied; 12 is a speed conversion circuit whose output is applied to a same polarity signal counting circuit 13 and an exclusive OR circuit 14; The speed conversion circuit 12 inserts a surplus into the information signal applied to the input terminal 11,
The surplus is divided into information, inserted every n bits, and inserted for frame pulses sent from the transmitting side so that frame synchronization can be achieved on the receiving side.

The same polarity signal counting circuit 13 compares the information bits of the speed conversion circuit output and the output of the M-sequence generator 15 every n bits in advance, and after taking the exclusive OR of both signals, the signal contains m or more consecutive bits. If it is predicted that a signal of the same polarity is included, the inhibition signal 17 is sent to the gate circuit 16 connected to the exclusive OR circuit 14,
8 is prohibited from being added to the exclusive OR circuit 14.

In other words, the information signal becomes the transmission line signal to prohibit the exclusive OR of the information signal and the M sequence.

The output of the same polarity signal counting circuit 13 is connected to the surplus bit control circuit 19, and this circuit performs exclusive OR of the M sequence and the information signal on the surplus bits inserted every n bits of the output of the exclusive OR circuit 14. Add information that it was not taken. The reset pulse period applied to the M-sequence generator 15 via the input terminal 20 is a frame synchronization pulse period, an n-bit period, or the like.

〔Effect of the invention〕

According to the present invention, by appropriately selecting the information bit block length n, the number m of same-polarity signals, and the M-sequence generator reset period, it is possible to suppress the number of consecutive same-polarity signals as transmission path signals to below a certain number. It becomes possible.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. l...Information signal input terminal, 2...Speed conversion circuit, 3...Reset pulse input terminal, 4
...M sequence generator, 5...Exclusive OR circuit, 11...Information signal input terminal, 12...
... Speed conversion circuit, 13 ... Same polarity signal counting circuit 1.14 ... Exclusive OR circuit, 15
...M sequence generator, 16...Gate circuit, 17...Prohibition signal, 18...M sequence generation circuit output, 19... - Surplus bit control circuit, 21...Reset pulse input terminal. Agent Patent Attorney Onka Uchihara l Figure $ 2 Figure

Claims (1)

[Claims] means for transmitting the exclusive OR of the speed-converted input signal sequence and the output of the M-sequence signal generator as a first transmission line signal; Blocks in which the exclusive OR of n bits of the lever and n bits of the M-sequence signal contains continuous signals of the same polarity with m or more bits are sent as is as the second transmission line signal, and the block is obtained by speed conversion. A PCM communication system comprising: means for adding information on the presence or absence of modulation to inserted bits.