CA1257933A - Synchronous encoder - Google Patents
Synchronous encoderInfo
- Publication number
- CA1257933A CA1257933A CA000530625A CA530625A CA1257933A CA 1257933 A CA1257933 A CA 1257933A CA 000530625 A CA000530625 A CA 000530625A CA 530625 A CA530625 A CA 530625A CA 1257933 A CA1257933 A CA 1257933A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- shift register
- encoder
- data signal
- bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
- H04L25/4923—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes
- H04L25/4925—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes using ternary codes using balanced bipolar ternary codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/16—Conversion to or from representation by pulses the pulses having three levels
- H03M5/18—Conversion to or from representation by pulses the pulses having three levels two levels being symmetrical with respect to the third level, i.e. balanced bipolar ternary code
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Dc Digital Transmission (AREA)
Abstract
SYNCHRONOUS ENCODER
Abstract of the Disclosure A synchronous encoder includes a 3-stage shift register, polarity control circuits, output gates, and unipolar-to-bipolar converter for producing a B3ZS bipolar signal from a binary input data signal. A detector detects occurrences of three consecutive zeros in the data signal, and upon each such detection modifies the data passing through the shift register to produce a desired bipolar code violation pulse and clears a parity circuit. The parity circuit controls the output gates to maintain an odd number of pulses between successive violation pulses of the bipolar signal.
- i -
Abstract of the Disclosure A synchronous encoder includes a 3-stage shift register, polarity control circuits, output gates, and unipolar-to-bipolar converter for producing a B3ZS bipolar signal from a binary input data signal. A detector detects occurrences of three consecutive zeros in the data signal, and upon each such detection modifies the data passing through the shift register to produce a desired bipolar code violation pulse and clears a parity circuit. The parity circuit controls the output gates to maintain an odd number of pulses between successive violation pulses of the bipolar signal.
- i -
Description
7~
SYNCHRONOUS EN~ODER
This invention relates to synchronous encoders.
Data signals are commonly encoded to facilitate their transmission and reception via transmission links, such as wire, optical, and radio transmission paths. In particular, it is well known to encode binary data signals into a bipolar format in order to provide the transmitted signal with an average zero d.c.
potential. Furthermore, it is well known to substitute strlngs of zero bits with code sequences including pulses in order to facilitate clock signal recovery from the received signal. To enable such zero bit strlngs to be reconstructed correctly at the receiver, at least one of the substituted pulses for each string is normally a bipolar code violatlon pulse, i.e. a pulse having the same polarity as the last preceding pulse of the bipolar signal.
At fast transmission speeds, for example for so-called DS-3 binary data signals having a bit rate of about 45Mb/s, the time which is required for achieving the encodlng presents a significant problem. The use of a synchronous encoder, which is driven by a clock signal at the data signal bit rate, reduces the time which is required for encoding, but known synchronous encoders have an undesired dependence upon the form of the clock signal (for example being driven by both rising and falling clock signal edges) and/or still exhibit an undue delay.
The encoding delay is particularly significant in that, for looped back checking of a transmission path including the encoder, transmitted bits must be stored during the delay period so that they can be compared individually with the looped-back bits. It is therefore necessary for the encoding delay to be constant and as short as possible.
An object of this invention, therefore, is to provide an improved synchronous encoder.
According to this invention there is provided a synchronous encoder for producing from a binary input data signal an encoded bipolar output signal which includes at least one bipolar code violation pulse in respect of each sequence of n consecutive zero bits of the data signal, where n is a plural integer, the encoder comprising: a shift register having an input for the data signal, ~ ~ 5~7~3;~:~
an outpu-t, and only n shift register stages therebetween; means for supplying a clock signal to the shift register for shifting bits of the data signal synchronously through the shift register stages;
detecting means coupled to the shift register for detecting n consecutive zero bits of the data signal; modifying means responsive to such detection by the detecting means for changing at least one of the n consecutive zero b;ts passing through the sh;ft register to a one b;t corresponding to said violat;on pulse; means responsive to the detecting means and to the data signal passing through the shift register for producing at least one polarity signal; gating means for gating data at the output of the shift reg;ster with the at least one polarity signal to produce two unipolar signals; and converting means responsive to khe two unipolar siynals for producing the encoded bipolar output signal; whereby pulses oF the bipolar output signal are produced with a delay of only n cycles of the clock signal relat;ve to corresponding bi-ts of the data signal.
Thus for a BnZS (bipolar with n-zero substitution) encoded signal, the synchronous encoder of this invention provides an encoding delay of only n clock cycles. The invention is particularly applicable to a B3ZS encoder for which n=3.
The encoder preferably includes parity means responsive to the detecting means and the data signal passing through the shift register for controlling the gating means to maintain a predetermined parity of pulses of the bipolar output s;gnal between success;ve violation pulses thereof. Conveniently, the parity means may comprise a bistable dev;ce which is responsive to said detect;on by the detecting means to adopt a predetermined state and which is responsive to each one bit in the data signal passing through the shift register to change its state.
The gating means is desirably responsive to the clock signal whereby the two unipolar signals are synchronized by the clock signal.
This avoids any need for retiming of the two unipolar signals and the consequent delay which this would entail.
The invention will be further understood from the following description with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates a B3ZS encoder in accordance with an embodiment of the invention; and 3 ~ ~57''3~
Fig. 2 is a timing diagram illustrating signals which may occur in operation of the encoder of Fig. 1.
ReFerring to Fig. 1, there is illustrated an encoder for producing a B3ZS (bipolar with three-zero substitution) encoded signal from a binary data signal, for example, at the so-called DS-3 signal bit rate of 44.736Mb/s.
As is known, in B3ZS encoding binary 1 bits are represented by alternately positive and negative pulses and each binary O bit is represented by no pulse, with the exception that each group of three consecutive zero bits is replaced by a sequence BOV or OOV, where ~
represents a pulse which violates the bipolar rule (i.e. it has the same polarity as the previous pulse) and B represents a pulse conforming with the bipolar rule, the choice between the sequences BOV and OOV being determined by a requirement that there be an odd number of pulses between consecutive V pulses. Thus, for example, if the last pulse was negative and an odd number of pulses has occurred since the last V pulse, then a binary sequence: 101000110000000010001 would be converted into the B3ZS sequence: +O 00-~-+0+-0-00+00~- with the B and V pulses: V B VB V
As the above example illustrates, the B3ZS encoding enables sequences of zeros in the binary data signal to be converted into pulses which facilitate clock signal recovery from the transmitted signal.
The encoder of Fig. 1 comprises four D-type flip-flops 11 to 14, three JK flip-flops 15 to 17, -five AND~NOR gates 18 to 22, a NAND gate 23, and a unipolar to bipolar converter 24. The flip-flops have data inputs D or J and -K (the latter being an inverting or active-O input), complementary data outputs Q and -Q, and clock inputs C. In addition, the JK flip-flop 16 has an active-O clear input CL. The encoder is supplied with a data signal to be encoded on a line 25 and a related clock signal on a line 26, and produces unipolar output signals P~ and P- on lines 27 and 28 respectively. The unipolar output signals P+ and P- are converted into a b polar B3ZS signal by the converter 24, which can be of any conventior,al form typically comprising a transformer having primary windings driven by the unipolar signals and a secondary winding 7~t'.~.3 producing the bipolar signal~ The output signal P~ is a logic 1 for each positive pulse in the B3ZS signal forrnat, and is otherwise a logic 0. Conversely, the output signal P- is a logic 1 for each negative pulse în the B3ZS signal format, and is otherwise a logic S 0.
The clock signal on the line 26 is supplied to the clock inputs C of the flip-flops 11 to 17 and to inputs of the gates 21 and 22, whereby the encoder operates synchronously with the clock signal and the pulse widths of the output signals P~ and P- are determined by the clock signal. The duty cycle of the clock signal supplied to the gates 21 and 22 can optionally be made variable, by means not shown, to provide for a B3ZS signal with an ad~lustable duty cycle. The synchronous operation of the encoder results in only a short delay of 3 clock cycles between the occurrence of an incoming data blt and the occurrence of the resultant B3ZS output signal, whereby bit-by-bit checking for a looped-back transmission path is facilitated. Furthermore, this is achieved without critical dependence upon the form of the clock signal, because only one edge of the clock signal is used for clocking the flip-flops, and the gating of the clock signal in the gates 21 and 23 avoids any need for retiming, and consequent undesired delay, of the output signals P~ and P-.
The encoder of Fig. 1 will be further described with additional reference to the timing diagrams, given by way oF
example, in Fig. 2. In addition to signals on the lines 25 to 28 already referred to, and a consequent B3ZS output shown at the bottom of Fig. 2, this figure also shows corresponding signals which occur on lines 29 to 36 of Fig. 1. For convenience and clarity~
these signals are also denoted by the same references as the lines on which they occur. The illustration of signals in Fig. 2 is based on the assumptions that, before the first data 1 bit shown, an even number of data 1 bits has occurred since the last V bit and the polarity of the last data 1 bit was negative.
Briefly, the flip-flops 11 to 13 constitute a 3-stage shift register through which incoming data bits are clocked in turn, thus providing the 3-clock-cycle encoding delay already referred to. The gate 18 and flip-flop 15 serve to detect the occurrence of three . , , ~ ~?r ~ j 7 ~3 3 ~
consecutive zeros in the incoming bi-t stream and upon such detection the ga-te 23, which is interposed in the data path between the flip-flops 11 and 12, serves to modify the third data bit from O to 1, this becoming the V pulse in the B3ZS signal. The flip-flops 16 and 14 serve to monitor parity between successive V pulses and provide accordingly for each B pulse in the B3ZS signal. The gates 19 and 20 in conjunction with the flip~flop 17 serve to control the polarity of the B3ZS signal pulses by disabling one of the gates 21 and 22 for each possible B3ZS output pulse.
In more detail, the data input line 25 is connected to the D
input of the flip-Flop 11, whose inverting output -Q is connected via the NAND gate 23 to the D input of the flip-flop 12, whose output Q ls connected to the D input o-f the Flip-flop 13. The data input line 25, and successively delayed signals from the Q outputs of the flip-flops 11 and 12 on the lines 29 and 30 respectively, are connec-ted to respective AND input gates of the AND-NOR gate 18.
Other inputs, not shown, of this and others of the AND-NOR gates 18 -to 22 are enabled. The output of the gate 18 is connected to the J
input of the flip-flop 15, whose inverting output -Q is connected to its -K input and via the line 31 to an input of the NAND gate 23.
As shown in Fig. 2, the signal 31 is normally high, enabling the NAND gate 23 so that data bits pass unchanged through the flip-flops 11 to 13. On the occurrence of three consecutive zeros in the data signal 25, the output of the gate 18 goes high, changing the state of the flip-flop 15 on the next clock pulse, as shown by the 000 detect signal 31 going low. The low state of the signal 31 inhibits the gate 23, which consequently produces a logic 1 or high output which is clocked into the flip-flop 12 on the next clock pulse to constitute a V pulse. This data modification is shown in Fig. 2 by the added logic 1 states, marked V 3 of the signal 30. The low state of the signal 31 lasts for only one clock cycle because of the supply of the signal 31 to the -K input of the flip-flop 15.
With each low state of the signal 31, the flip-flop 16 is cleared by the signal 31 being supplied to its clear input CL. The J and -K inputs of this flip-flop 16 are connected to the Q and -Q
outputs, respectively, of the flip-flop 12, whereby the flip-flop 16 changes state or is toggled with each logic 1 bit which is clocked 7~
into the flip-Plop 13. The -Q output of the flip flop 16 thus cons-titutes a parity signal on the line 33, and is delayed by one clock cycle to produce a delayed parity signal on the line 34 connected to the Q ou-tput of the flip-flop 14. The parity and delayed parity signals 33 and 34 represent whether an odd or even number of logic 1 bits have occurred since the last V bit.
For example9 considering the signals 30 to 33 in Fig. 2, with the first logic O state of the signal 31 the flip flop 16 is cleared so -that the parity signal 33 is (in this case remains) high.
At the end of the first V bit in the signal 30, i.e. when this bit is clocked into the flip-flop 13 so that the signal 32 goes high, the parity signal 33 goes low. With each successive logic 1 bit, referenced a, b, c for the signals 30 and 32, clocked into the fllp-flop 13, the parity slgnal 33 changes state. At the end of the bit b in the signal 32, the 000 detect signal becomes low again, so that the flip flop 16 is cleared and the parity signal 33 becomes high again.
The gate 20 produces a parity control signal on the line 35 from the signal 31 and the complements of the signals 32 and 34, and supplies this to -the J input of the Flip-flop 17. The gate 19 produces a complementary signal, from the signals 32 and 34 and the complement of the signal 31, and supplies this to the -K input of the Flip-flop 17. The flip-flop 17 produces a polarity signal on the line 36 which, when it is a logic 1, disables the gate 21, and produces a complementary signal at its -Q output for similarly controlling the gate 22.
The gates 21 and 22 are similarly disabled by each logic 1 state of the clock signal. In response to each logic 1 state o~` the signal 32, and hence logic O state at the -Q output of the flip-flop 13~ that one of the gates 21 and 22 which is not disabled by the pGlarity signal 36 or its complement produces a logic 1 output during the period when the clock signal 26 is a logic 0, as shown by the signals 27 and 28 in Fig. 2. In addition, even if the signal 32 is a logic 0, the relevant gate 21 or 22 produces an output pulse, constituting a B pulse, if both the 000 detect signal 31 and the delayed parity sigral 34 are logic 0. One such B pulse is shown in the signal 28 in Fig. 2.
. .
7 ~ ~5~933 In the encoder as illustrated in Fig. l, the JK flip~flops and AND-NOR gates can all be of the same type to Facilitate manufacture of the encoder. Al-ternatively, the gate 19 can be dispensed with if the flip-flop 17 instead has a non-inverting K
input, to which the signal 35 would then also be applied. The AND-NOR gate 18 can also be replaced by a NOR gate. The use of the AND-NOR gate, however, enables other irputs to be used for signals from a preceding descrambler, for example an RZ (return to zero) or NRZ (non-return to zero) descrambler which produces the data signal on -the line 25 by descrambllng a signal received via an optical transmission link, whereby the combined descrambler and B3ZS encoder do no-t produce any greater signal delay than the encoder alone.
Al-though the embodiment of the invention described above relates to a 33ZS encoder, it should be appreciated that the invention may be similarly applied to other encoding formats.
Numerous other variations, modifications, and adaptations may be made to the embodiment of the invention described above without departing from the scope of the invention as defined in the claims.
SYNCHRONOUS EN~ODER
This invention relates to synchronous encoders.
Data signals are commonly encoded to facilitate their transmission and reception via transmission links, such as wire, optical, and radio transmission paths. In particular, it is well known to encode binary data signals into a bipolar format in order to provide the transmitted signal with an average zero d.c.
potential. Furthermore, it is well known to substitute strlngs of zero bits with code sequences including pulses in order to facilitate clock signal recovery from the received signal. To enable such zero bit strlngs to be reconstructed correctly at the receiver, at least one of the substituted pulses for each string is normally a bipolar code violatlon pulse, i.e. a pulse having the same polarity as the last preceding pulse of the bipolar signal.
At fast transmission speeds, for example for so-called DS-3 binary data signals having a bit rate of about 45Mb/s, the time which is required for achieving the encodlng presents a significant problem. The use of a synchronous encoder, which is driven by a clock signal at the data signal bit rate, reduces the time which is required for encoding, but known synchronous encoders have an undesired dependence upon the form of the clock signal (for example being driven by both rising and falling clock signal edges) and/or still exhibit an undue delay.
The encoding delay is particularly significant in that, for looped back checking of a transmission path including the encoder, transmitted bits must be stored during the delay period so that they can be compared individually with the looped-back bits. It is therefore necessary for the encoding delay to be constant and as short as possible.
An object of this invention, therefore, is to provide an improved synchronous encoder.
According to this invention there is provided a synchronous encoder for producing from a binary input data signal an encoded bipolar output signal which includes at least one bipolar code violation pulse in respect of each sequence of n consecutive zero bits of the data signal, where n is a plural integer, the encoder comprising: a shift register having an input for the data signal, ~ ~ 5~7~3;~:~
an outpu-t, and only n shift register stages therebetween; means for supplying a clock signal to the shift register for shifting bits of the data signal synchronously through the shift register stages;
detecting means coupled to the shift register for detecting n consecutive zero bits of the data signal; modifying means responsive to such detection by the detecting means for changing at least one of the n consecutive zero b;ts passing through the sh;ft register to a one b;t corresponding to said violat;on pulse; means responsive to the detecting means and to the data signal passing through the shift register for producing at least one polarity signal; gating means for gating data at the output of the shift reg;ster with the at least one polarity signal to produce two unipolar signals; and converting means responsive to khe two unipolar siynals for producing the encoded bipolar output signal; whereby pulses oF the bipolar output signal are produced with a delay of only n cycles of the clock signal relat;ve to corresponding bi-ts of the data signal.
Thus for a BnZS (bipolar with n-zero substitution) encoded signal, the synchronous encoder of this invention provides an encoding delay of only n clock cycles. The invention is particularly applicable to a B3ZS encoder for which n=3.
The encoder preferably includes parity means responsive to the detecting means and the data signal passing through the shift register for controlling the gating means to maintain a predetermined parity of pulses of the bipolar output s;gnal between success;ve violation pulses thereof. Conveniently, the parity means may comprise a bistable dev;ce which is responsive to said detect;on by the detecting means to adopt a predetermined state and which is responsive to each one bit in the data signal passing through the shift register to change its state.
The gating means is desirably responsive to the clock signal whereby the two unipolar signals are synchronized by the clock signal.
This avoids any need for retiming of the two unipolar signals and the consequent delay which this would entail.
The invention will be further understood from the following description with reference to the accompanying drawings, in which:
Fig. 1 schematically illustrates a B3ZS encoder in accordance with an embodiment of the invention; and 3 ~ ~57''3~
Fig. 2 is a timing diagram illustrating signals which may occur in operation of the encoder of Fig. 1.
ReFerring to Fig. 1, there is illustrated an encoder for producing a B3ZS (bipolar with three-zero substitution) encoded signal from a binary data signal, for example, at the so-called DS-3 signal bit rate of 44.736Mb/s.
As is known, in B3ZS encoding binary 1 bits are represented by alternately positive and negative pulses and each binary O bit is represented by no pulse, with the exception that each group of three consecutive zero bits is replaced by a sequence BOV or OOV, where ~
represents a pulse which violates the bipolar rule (i.e. it has the same polarity as the previous pulse) and B represents a pulse conforming with the bipolar rule, the choice between the sequences BOV and OOV being determined by a requirement that there be an odd number of pulses between consecutive V pulses. Thus, for example, if the last pulse was negative and an odd number of pulses has occurred since the last V pulse, then a binary sequence: 101000110000000010001 would be converted into the B3ZS sequence: +O 00-~-+0+-0-00+00~- with the B and V pulses: V B VB V
As the above example illustrates, the B3ZS encoding enables sequences of zeros in the binary data signal to be converted into pulses which facilitate clock signal recovery from the transmitted signal.
The encoder of Fig. 1 comprises four D-type flip-flops 11 to 14, three JK flip-flops 15 to 17, -five AND~NOR gates 18 to 22, a NAND gate 23, and a unipolar to bipolar converter 24. The flip-flops have data inputs D or J and -K (the latter being an inverting or active-O input), complementary data outputs Q and -Q, and clock inputs C. In addition, the JK flip-flop 16 has an active-O clear input CL. The encoder is supplied with a data signal to be encoded on a line 25 and a related clock signal on a line 26, and produces unipolar output signals P~ and P- on lines 27 and 28 respectively. The unipolar output signals P+ and P- are converted into a b polar B3ZS signal by the converter 24, which can be of any conventior,al form typically comprising a transformer having primary windings driven by the unipolar signals and a secondary winding 7~t'.~.3 producing the bipolar signal~ The output signal P~ is a logic 1 for each positive pulse in the B3ZS signal forrnat, and is otherwise a logic 0. Conversely, the output signal P- is a logic 1 for each negative pulse în the B3ZS signal format, and is otherwise a logic S 0.
The clock signal on the line 26 is supplied to the clock inputs C of the flip-flops 11 to 17 and to inputs of the gates 21 and 22, whereby the encoder operates synchronously with the clock signal and the pulse widths of the output signals P~ and P- are determined by the clock signal. The duty cycle of the clock signal supplied to the gates 21 and 22 can optionally be made variable, by means not shown, to provide for a B3ZS signal with an ad~lustable duty cycle. The synchronous operation of the encoder results in only a short delay of 3 clock cycles between the occurrence of an incoming data blt and the occurrence of the resultant B3ZS output signal, whereby bit-by-bit checking for a looped-back transmission path is facilitated. Furthermore, this is achieved without critical dependence upon the form of the clock signal, because only one edge of the clock signal is used for clocking the flip-flops, and the gating of the clock signal in the gates 21 and 23 avoids any need for retiming, and consequent undesired delay, of the output signals P~ and P-.
The encoder of Fig. 1 will be further described with additional reference to the timing diagrams, given by way oF
example, in Fig. 2. In addition to signals on the lines 25 to 28 already referred to, and a consequent B3ZS output shown at the bottom of Fig. 2, this figure also shows corresponding signals which occur on lines 29 to 36 of Fig. 1. For convenience and clarity~
these signals are also denoted by the same references as the lines on which they occur. The illustration of signals in Fig. 2 is based on the assumptions that, before the first data 1 bit shown, an even number of data 1 bits has occurred since the last V bit and the polarity of the last data 1 bit was negative.
Briefly, the flip-flops 11 to 13 constitute a 3-stage shift register through which incoming data bits are clocked in turn, thus providing the 3-clock-cycle encoding delay already referred to. The gate 18 and flip-flop 15 serve to detect the occurrence of three . , , ~ ~?r ~ j 7 ~3 3 ~
consecutive zeros in the incoming bi-t stream and upon such detection the ga-te 23, which is interposed in the data path between the flip-flops 11 and 12, serves to modify the third data bit from O to 1, this becoming the V pulse in the B3ZS signal. The flip-flops 16 and 14 serve to monitor parity between successive V pulses and provide accordingly for each B pulse in the B3ZS signal. The gates 19 and 20 in conjunction with the flip~flop 17 serve to control the polarity of the B3ZS signal pulses by disabling one of the gates 21 and 22 for each possible B3ZS output pulse.
In more detail, the data input line 25 is connected to the D
input of the flip-Flop 11, whose inverting output -Q is connected via the NAND gate 23 to the D input of the flip-flop 12, whose output Q ls connected to the D input o-f the Flip-flop 13. The data input line 25, and successively delayed signals from the Q outputs of the flip-flops 11 and 12 on the lines 29 and 30 respectively, are connec-ted to respective AND input gates of the AND-NOR gate 18.
Other inputs, not shown, of this and others of the AND-NOR gates 18 -to 22 are enabled. The output of the gate 18 is connected to the J
input of the flip-flop 15, whose inverting output -Q is connected to its -K input and via the line 31 to an input of the NAND gate 23.
As shown in Fig. 2, the signal 31 is normally high, enabling the NAND gate 23 so that data bits pass unchanged through the flip-flops 11 to 13. On the occurrence of three consecutive zeros in the data signal 25, the output of the gate 18 goes high, changing the state of the flip-flop 15 on the next clock pulse, as shown by the 000 detect signal 31 going low. The low state of the signal 31 inhibits the gate 23, which consequently produces a logic 1 or high output which is clocked into the flip-flop 12 on the next clock pulse to constitute a V pulse. This data modification is shown in Fig. 2 by the added logic 1 states, marked V 3 of the signal 30. The low state of the signal 31 lasts for only one clock cycle because of the supply of the signal 31 to the -K input of the flip-flop 15.
With each low state of the signal 31, the flip-flop 16 is cleared by the signal 31 being supplied to its clear input CL. The J and -K inputs of this flip-flop 16 are connected to the Q and -Q
outputs, respectively, of the flip-flop 12, whereby the flip-flop 16 changes state or is toggled with each logic 1 bit which is clocked 7~
into the flip-Plop 13. The -Q output of the flip flop 16 thus cons-titutes a parity signal on the line 33, and is delayed by one clock cycle to produce a delayed parity signal on the line 34 connected to the Q ou-tput of the flip-flop 14. The parity and delayed parity signals 33 and 34 represent whether an odd or even number of logic 1 bits have occurred since the last V bit.
For example9 considering the signals 30 to 33 in Fig. 2, with the first logic O state of the signal 31 the flip flop 16 is cleared so -that the parity signal 33 is (in this case remains) high.
At the end of the first V bit in the signal 30, i.e. when this bit is clocked into the flip-flop 13 so that the signal 32 goes high, the parity signal 33 goes low. With each successive logic 1 bit, referenced a, b, c for the signals 30 and 32, clocked into the fllp-flop 13, the parity slgnal 33 changes state. At the end of the bit b in the signal 32, the 000 detect signal becomes low again, so that the flip flop 16 is cleared and the parity signal 33 becomes high again.
The gate 20 produces a parity control signal on the line 35 from the signal 31 and the complements of the signals 32 and 34, and supplies this to -the J input of the Flip-flop 17. The gate 19 produces a complementary signal, from the signals 32 and 34 and the complement of the signal 31, and supplies this to the -K input of the Flip-flop 17. The flip-flop 17 produces a polarity signal on the line 36 which, when it is a logic 1, disables the gate 21, and produces a complementary signal at its -Q output for similarly controlling the gate 22.
The gates 21 and 22 are similarly disabled by each logic 1 state of the clock signal. In response to each logic 1 state o~` the signal 32, and hence logic O state at the -Q output of the flip-flop 13~ that one of the gates 21 and 22 which is not disabled by the pGlarity signal 36 or its complement produces a logic 1 output during the period when the clock signal 26 is a logic 0, as shown by the signals 27 and 28 in Fig. 2. In addition, even if the signal 32 is a logic 0, the relevant gate 21 or 22 produces an output pulse, constituting a B pulse, if both the 000 detect signal 31 and the delayed parity sigral 34 are logic 0. One such B pulse is shown in the signal 28 in Fig. 2.
. .
7 ~ ~5~933 In the encoder as illustrated in Fig. l, the JK flip~flops and AND-NOR gates can all be of the same type to Facilitate manufacture of the encoder. Al-ternatively, the gate 19 can be dispensed with if the flip-flop 17 instead has a non-inverting K
input, to which the signal 35 would then also be applied. The AND-NOR gate 18 can also be replaced by a NOR gate. The use of the AND-NOR gate, however, enables other irputs to be used for signals from a preceding descrambler, for example an RZ (return to zero) or NRZ (non-return to zero) descrambler which produces the data signal on -the line 25 by descrambllng a signal received via an optical transmission link, whereby the combined descrambler and B3ZS encoder do no-t produce any greater signal delay than the encoder alone.
Al-though the embodiment of the invention described above relates to a 33ZS encoder, it should be appreciated that the invention may be similarly applied to other encoding formats.
Numerous other variations, modifications, and adaptations may be made to the embodiment of the invention described above without departing from the scope of the invention as defined in the claims.
Claims (6)
1. A synchronous encoder for producing from a binary input data signal an encoded bipolar output signal which includes at least one bipolar code violation pulse in respect of each sequence of n consecutive zero bits of the data signal, where n is a plural integer, the encoder comprising:
a shift register having an input for the data signal, an output, and only n shift register stages therebetween;
means for supplying a clock signal to the shift register for shifting bits of the data signal synchronously through the shift register stages;
detecting means coupled to the shift register for detecting n consecutive zero bits of the data signal;
modifying means responsive to such detection by the detecting means for changing at least one of the n consecutive zero bits passing through the shift register to a one bit corresponding to said violation pulse;
means responsive to the detecting means and to the data signal passing through the shift register for producing at least one polarity signal;
gating means for gating data at the output of the shift register with the at least one polarity signal to produce two unipolar signals; and converting means responsive to the two unipolar signals for producing the encoded bipolar output signal;
whereby pulses of the bipolar output signal are produced with a delay of only n cycles of the clock signal relative to corresponding bits of the data signal.
a shift register having an input for the data signal, an output, and only n shift register stages therebetween;
means for supplying a clock signal to the shift register for shifting bits of the data signal synchronously through the shift register stages;
detecting means coupled to the shift register for detecting n consecutive zero bits of the data signal;
modifying means responsive to such detection by the detecting means for changing at least one of the n consecutive zero bits passing through the shift register to a one bit corresponding to said violation pulse;
means responsive to the detecting means and to the data signal passing through the shift register for producing at least one polarity signal;
gating means for gating data at the output of the shift register with the at least one polarity signal to produce two unipolar signals; and converting means responsive to the two unipolar signals for producing the encoded bipolar output signal;
whereby pulses of the bipolar output signal are produced with a delay of only n cycles of the clock signal relative to corresponding bits of the data signal.
2. An encoder as claimed in claim 1 and including parity means responsive to the detecting means and the data signal passing through the shift register for controlling the gating means to maintain a predetermined parity of pulses of the bipolar output signal between successive violation pulses thereof.
3. An encoder as claimed in claim 2 wherein the parity means comprises a bistable device which is responsive to said detection by the detecting means to adopt a predetermined state and which is responsive to each one bit in the data signal passing through the shift register to change its state.
4. An encoder as claimed in claim 1, 2, or 3 wherein n=3 and the bipolar output signal is a B3ZS signal.
5. An encoder as claimed in claim 1, 2, or 3 wherein the modifying means comprises a gate for gating a bit of the data signal passing through the shift register with an output signal of the detecting means.
6. An encoder as claimed in claim 1, 2, or 3 wherein the gating means is responsive to the clock signal whereby the two unipolar signals are synchronized by the clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000530625A CA1257933A (en) | 1987-02-25 | 1987-02-25 | Synchronous encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000530625A CA1257933A (en) | 1987-02-25 | 1987-02-25 | Synchronous encoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1257933A true CA1257933A (en) | 1989-07-25 |
Family
ID=4135052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000530625A Expired CA1257933A (en) | 1987-02-25 | 1987-02-25 | Synchronous encoder |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1257933A (en) |
-
1987
- 1987-02-25 CA CA000530625A patent/CA1257933A/en not_active Expired
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5200979A (en) | High speed telecommunication system using a novel line code | |
| US4584695A (en) | Digital PLL decoder | |
| US3893072A (en) | Error correction system | |
| US4234897A (en) | DC Free encoding for data transmission | |
| EP0040632B1 (en) | Data processing system with serial data transmission between subsystems | |
| US3453592A (en) | Delay time control system for signal check or correction | |
| IE45458B1 (en) | Miller-encoded message decoder | |
| KR860001257B1 (en) | Data reading apparatus for data transmission | |
| US5056114A (en) | Method and apparatus for decoding Manchester encoded data | |
| US4849995A (en) | Digital signal transmission system having frame synchronization operation | |
| US3825683A (en) | Line variation compensation system for synchronized pcm digital switching | |
| US6694377B1 (en) | Communications interface for the serial transmission of digital data, and corresponding data transmission method | |
| US5717728A (en) | Data/clock recovery circuit | |
| US5655078A (en) | Apparatus and method for encoding data in a fiber data distributed interface (FDDI) | |
| CA1257933A (en) | Synchronous encoder | |
| US5063575A (en) | Apparatus and method for proper byte alignment in an encoder/decoder | |
| US6192093B1 (en) | Enhanced CIMT coding system and method with automatic word alignment for simplex operation | |
| EP0549047A1 (en) | Scrambler/descrambler and synchronizer for a data transmission system | |
| US6990122B2 (en) | Synchronism phase-switching circuit for the recovery of received data | |
| US4203003A (en) | Frame search control for digital transmission system | |
| GB1598798A (en) | Data transfer system | |
| US5265105A (en) | Decoding circuit for inhibiting error propagation | |
| US4928289A (en) | Apparatus and method for binary data transmission | |
| US5107263A (en) | NRZ to CMI (II) encoding circuit | |
| US4498167A (en) | TDM Communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |