JPS6039870A - Manufacture of gaas semiconductor device - Google Patents

Abstract

PURPOSE:To operate a GaAs IC at high speed and increase the performance of the IC by forming the whole or at least a section being in contact with a substrate of a gate electrode in a tungsten nitride film and forming the tungsten nitride film through a reactive sputtering method in a mixed gas of nitrogen gas at a specific partial pressure ratio and argon gas. CONSTITUTION:Si<+> ions are implanted to a semi-insulating GaAs crystal substrate 31 while using a SiO2 film 32 as a mask, and an active layer 33 is formed through heat treatment. A WN film 34 is deposited on the whole surface of the substrate through reactive sputtering. The sputtering is executed in a mixed gas of N2, a partial pressure ratio thereof is brought to 0.03-0.2, and Ar. The WN film 34 is patterned through dry etching while using a photo-resist as a mask to form a gate electrode. Si<+> ions are implanted again while employing the gate electrode as a mask to shape ion implantation layers 35, 36. The whole surface of the substrate is coated with a PSG film 37, and source and drain regions 35', 36' are formed through heat treatment. Openings are bored to the PSG film 37, and source and drain electrodes 38, 39 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a Schottky gate type GaAs semiconductor device.

[Technical background of the invention and its problems]

GaAg integrated circuits (ICs) are attracting attention for use in logic circuits and memory circuits capable of high-speed operation.

Among them, DCFL (Direct Coupled F
ET Logic) is said to be suitable for large-scale integrated circuits (LSI) as a basic logic element that can operate at high speed and with low power consumption. High speed DCFL type GaAs I
The most important issue in realizing C is the switching FET.
Normally off type Schottky goo) FET
(MESF'ET).

The figure of merit of a GaAs FET is expressed as CgS//Gm.

Here, Cgs is the gate-source volume, j),
Gm is the mutual conductance of the FET. Therefore, Cg
! By reducing l and increasing Gm, the figure of merit Q
'improved i'. Substituting Gm, the actual Gm is Gm'' Gmo / (1+Gyy1 o・Ra). Grrlo is the intrinsic transconductance determined from the percentage characteristic of the channel part of the FET. This cm.

is the maximum Gm that can be extracted, but in the conventional MESFET as shown in Figure 1, the series resistance RIl between the source and the dirt is large, so the actual Gm is smaller than Gmo as shown in the above equation. . Therefore, the key to reducing this series resistance R8 is to obtain a large Gm and
This is the key to improving high frequency characteristics.

In FIG. 1, 11 is a semi-insulating GaAs crystal substrate, and 12 is a semi-insulating GaAs crystal substrate.
- Active layer, 13 is the dart electrode, 14° and 15 are the drain electrodes.

A self-line (self-alignment) method is known as a method for reducing the above-mentioned series resistance R8 of the lV S FET. There are several ways to do this, and a typical example is shown in Part 21, Part 1. This is done by performing high ρ ion implantation using the gate redundant electrode 23 as a mask, and m-
The drain region 24.25 with a diameter of 1 cm 2 or more is formed close to the dart electrode 23. 211'' Semi-insulating GaAs crystal substrate, 22): i active state;, 26
, 27 are source and drain electrodes, respectively. Manufacturing a MESFET using such a self-aligned cell line r', J (6), the most difficult thing in ζ is the selection of the dirt electrode gold.The source and drain regions are Although a heat treatment step for activating the impurities is essential for forming the GaAe layer, the treatment temperature for activating the donor ion implantation layer in GaAe is usually about 80℃.
The temperature can reach as low as 0℃. It is necessary for the gate electrode used as a mask to maintain a good Schottky barrier with the GaAs substrate even after such high-temperature heat treatment, and there are only a few metals that meet this condition. ), tungsten silicide (WSi), and other experimental examples have only raised concerns (for example, N, Yokogawa etal 1981).
．． l5SCC). Moreover, in order to obtain a large operating margin in a DCFL high-speed logic circuit using a general V (normally-off type MEESFET), it is necessary to have a high Schottky barrier height φB, but these W +
The height of the Schottky barrier for GaAs such as TIW + WSix is as low as φ, = 0.7 to 075 [V].

In addition, the n value, which is an indicator of the rectification characteristics of the Schottky barrier, and the resistance value of the gate electrode are important in obtaining excellent logic circuit characteristics, but conventional gate electrode materials and gate electrode formation methods do not fully satisfy these requirements. Not satisfied.

[Purpose of the invention]

The present invention realizes a high-speed GaAs IC with OJ performance.
An object of the present invention is to provide a method for manufacturing an aAs semiconductor device.

[Summary of the invention]

Invention i] The entire or at least w
One of the points is to use a tungsten oxide (WN) film on the part that contacts the plate, and to replace this WN y@, with nitrogen (N2).
) It is characterized in that it is formed by the reactive Nuno or Tsuta method in which a W target is sputtered in a mixed gas of N2 gas and Argon (Ar) gas with a residue pressure of 0.03 to 0.2.

Here, the reason for limiting the N2 gas partial pressure to the above range is A.
'y I K % By setting this to 003 or more, the Schottky height φ8 of the wall becomes a large value of around 0.5 (V), and the n value shows a sufficiently small value. Second, when the N2 gas partial pressure is made larger than 0.2,
The specific resistance ρ of the membrane increases rapidly to MESFli;
Nitrogen (
It becomes almost as large as the case where I-inclusion is not included.

The experimental data that served as the basis for these limitations will be explained below. A WN film formed by a reactive sputtering method using a mixed gas of Ar and N2 (-6X10-3 Torr) exhibits better external adhesion to a GaAs substrate than a W film formed by a Suzetta method. This was revealed through experiments. However, depending on the composition, the WN film produced by the above-mentioned h method has a diameter of φ3,
The n value and ρ change. Figure 3 shows the N2 partial pressure ratio PN2/(PN2+PAr) when the respective partial pressures in the mixed gas of Ar and N2 are PAr ``N2, and the horizontal axis is φ.
Figure 4 1d also shows ρ. The WN film of this V → combination is about 1000X,
The data in FIGS. 3 and 4-1 are the results measured after WN IMs were subjected to heat treatment at 800° C. after Nupatta. It is clear from these figures that the N2 partial pressure ratio is 0.0
3 or more, it shows an unprecedentedly high φ8, and the n value is small. In addition, as the N2 partial pressure ratio increases, ρ increases and the n value also tends to increase.
When the partial pressure ratio is 0.2 or more, ρ increases rapidly.

From these data, it can be seen that it is desirable to set the N2 partial pressure ratio in the range of 003 to 02.

Figure 5 shows 1. When the heat treatment temperature was changed, the φ8 and n values of the WN film formed at a N2 partial pressure ratio of 0.06 were shown to change. From the results of Jin, the WN film was heated at a heat treatment temperature of 800 CM.
After f+, J Ken also has a high φ8. This temperature is the source
Heat treatment Yfia for activating drain ion implantation layer
The degree of helical diameter corresponds to 750 to 850°C, which is convenient for device fabrication.

〔Effect of the invention〕

According to the present invention, φ8 of the shot pump electrode
MESF with small n1 old and small resistivity ρ
ET is 40 ra i. Therefore, if the present invention is applied to, for example, a DCFL-type GaAs IC, it is possible to realize a logic circuit with a large logic amplitude and a wide operating margin, and a logic circuit that can operate at higher speed than before. .

[6 Achievements] Hereinafter, embodiments to which the DCFL type GaAs ICK of the present invention is applied will be described. Normally-off MESFET and normally-on MESF that make up the DCFL circuit
The active layer of ET is selectively formed by ion implantation using s lo 21]"i as a mask. FIG.
(g) shows the manufacturing process of the normally-off type MESFET section. That is, 5 81 ions are applied to the semi-insulating GaAs crystal substrate 31 using the 5IO2 film 32 as a mask.
Injected under the conditions of 0 keV, 2 x 10'% m-2,
A heat treatment is performed at 850° C. for 15 minutes to form the active layer 33 (,).

Next, WN is applied to the entire surface of this board using reactive vines.
Deposit film 34 by 3000X (b). This spatter is
A mixed gas of N2 and Ar with a N2 gas partial pressure ratio of 006 (
6X 10-5 Torr). After this, dry etching is performed using the photoresist as a mask to remove the WN film 3.
4 is turned 29 times to form a gate electrode (C). Then, using the dirt electrode j-turn as a mask, St+ ions were applied again at 2 (10 ke'V).

Ion implantation is performed under the conditions of 3 x 10"tM-2 to form ion-implanted layers 35 and 36 that are self-aligned to the gate electrode (d). Next, the entire surface of this substrate is covered with a PSG film 37 and heated at 800°C. , a heat treatment is performed for 10 minutes to form source and drain regions 35' and 36' (e).

Next, the PSG film 37 is opened f) and the source and drain positive electrodes 3 B, , ? made of Au/AuGe are opened. 9' to complete the normally-off MESFET (g)
.

MESF'ET tri j obtained by this example
The g-series resistance R is small, and Gm is approximately 180 mσ, which is more than twice that of the G-column shown in FIG. Map ζ this M
Consisting of ESFET/I) -0.6V in CF L circuit
It shows a large logic amplitude of 150 mV or more as a permissible operating margin. In addition, when the gate length is 1 μm, the propagation delay distance τpd is 11'·! As a result of the measurements made, it was confirmed that the present invention was 20 to 30 psec faster than the conventional type shown in FIG.

Next, we will discuss an example in which the cutting and turning of the U pole is carried out by lift-off processing using an insulating film Nubesa.
This will be explained with reference to Figures (,) to (e). Semi-insulating Ga
The process is the same as the previous embodiment until the active layer 42 is formed by selectively ion-implanting St+ into the As crystal substrate 41. After that, a PSG film 43 of 8000X was coated on the entire surface of the substrate by CVD method, and then a SiO2 film 43 of 3000X
4 all 44 (a). After forming a photorenost groove 45 having an opening in the gate electrode region, the 5IO2 film 44 and the PSG film 43 are continuously etched using ammonium fluoride (b). PS from the SiO2 film 44
Since the etching speed of the G film 43 is fast, it is possible to perform overhanging etching as shown in the figure. After this, under the same conditions as in the previous example, Q
A WN film 46 of about 2000X is deposited, and then a TiN II film 47 of about 3000X is deposited as a low resistance metal film (c). At this time, as shown in the figure, the WN film 46 and the Ti
The laminated film of the N film 47 is connected to the PSGll 43 and the sio□ film 44.
A step break occurs at the step portion due to the laminated film. Then, by etching away the 5xO21t% 44 and the PSG film 43, a dirt electrode consisting of the WN film 46 and the TIN film 47 is patterned (d). After this, CF4
The side surface of the W, N film 46 is recessed by slightly dry etching with 0.0 and 0.02 (e). After this, it is not shown, but the first fire/it! Same as example i (child process η−′
l: ESFET can be obtained.

In this actual measurement example, W N ll+,! 4.61/C
TiN ll...147 is stacked on W N I
Make the gate voltage sufficiently thick with only Ico'+ (However, if you try to lower the resistance, the stress will be large, so 'rsNII
This is because Q47 reduces the IK pole by 1 degree. TiN1l'fu4vliCF4+ 02K
YORU TRIE Y f 7 F TE'SV N 111J
46 side etching to obtain the desired length of the case. 11) It is possible to use a metal other than the TiN film.

According to this embodiment, in addition to obtaining the effect of the previous implementation fl;II and times(·k), 'rli-iq1. By lowering the resistance, even higher speed IJ output is achieved.

Incidentally, a lift-off force of 11'' and a knee pattern may also be used. However, if reactive sputtering is performed for a long time with the resist/base turns remaining, the resist will denature, resulting in turn conversion errors due to the deformation. Therefore, it is preferable to use a laminated film of a PSG film and a 5I02 film as an insulating side striper as in this embodiment.

The gate electrode is made of 3-layer Sakaki structure, which reduces the gate resistance by 1.
A single embodiment will be explained using the 81st sheet (a) to (g). S t in semi-insulating GaAs crystalline material 5)
o 2 bile, 52 as a mask and 50 S 1 ions
The active layer 53 is selectively formed by implanting 2×10 cm at keV and performing heat treatment at 850° C. for 15 minutes (,).

After this, the reactivity of the same girl as in the first fruit//ili example is shown as follows:
00 X Jffi J,! - Set it on the same Champer If3 and use the chiri target and the An target in the 1111th order to create this -VN II<! s 4 Sat 500 people'I'iN 1111+55.3000λ
Au115. Sputter J56 in a continuous L/C manner and deposit 4.
7'j tro(1]). Then, by dry etching using photorenost as a mask, t:' of the above three layers is removed from layer j1.
・Zetern the fist to form a dart electrode (
c). Then, using this gate lte rod as a mask, perform SI again.
An ion-implanted layer 57 in which + ions were implanted at 200 keV to a depth of 3×10 cm and self-aligned to the dart electrode.
58 (d). And all white PSG IF, i
A source region 57' and a drain region 58' are formed by performing heat treatment at 800° C. for 10 minutes to activate the implanted impurities (o). After this, the PSG removal 59 is opened f), and the evaporation percentage of Au/AuGe is
Ter = 7 IF) Saone 7h Flood 1 (60, forming the drain electrode 61 (g).

This fruit: 6f! In the i example, the intermediate layer of the gate electrode is TiN! 55 is diffusion barrier gold 1. It acts as an arc, and the Au'' film retains its shape even after heat treatment at 56 to 1800°C.

From the data in Figure 8114, when forming a gate voltage p, > with a dart length of 1 μm and a gate width of 20 mm using only the WN film of aoool, the resistance will be approximately 50 Ω, but this actual ) In the case of J1!1, the gate resistance is significantly reduced to 8Ω using the same method. From the measurement results of a ring-on-lator with a groove bottom made of GaAs MESFET according to this example and arranged with 1゛1-Pt-Au, the transmission delay time τpd is equivalent to the conventional type shown in Fig. 1 when converted to a gate length of 11tm. In comparison, it was suppressed to be more than 20 psec faster.

In addition, the above actual Ali! The same results can be obtained by using the example AnljQ as an A membrane. 3 layer J again? It is also possible to pattern the ``+'' composite electrode using a liftman as in the previous embodiment.

As described above, excluding the embodiments, by using the method of the present invention, it is possible to achieve high-speed operation and high performance of a GaAs IC.

In the present invention, a WN film is formed using a reactive sputtering method under predetermined conditions. Even if a WN target with a determined K'P composition is prepared and a WN film is formed by the conventional S-Zetta method, the same i-top SNO-J can be expected.

[Brief explanation of drawings]

Fig. 1 shows a conventional fA MESFET, and Fig. 2 shows a self-line type MESF targeted by the present invention.
Figures showing ET, Figures 3 to 5 are diagrams showing data supporting the basis of numerical limitations in the method of the present invention, and Figures 6 (a) to 5.
(g) is a diagram showing the MESFET construction process of the present E-circuit JlJ example, and Figs.
Figures 8(a) to 8(g) are diagrams illustrating the manufacturing process of an F25FET according to another embodiment of the present invention. Semi-insulating GaAs crystal substrate, 3 3 , 4 2 , 5 3 . . .
, 36, 57.58... ion implantation layer, 35', 5
7'... Source region, 36', 5B'... Drain region, 38, 6Q... Source 1 (j, l gold, 39° 67- + Il;; i, 4.9 ...PS
G JIH: 4. 44 =-8r 02 membrane, 47...
・1"iN film, 55...']"iN llf, i, 5
6. An escape. 11 Applicants Patent Attorney Takeshi Suzue Outer Box Figure 1 or Figure 2, Figure 3 Aγ, N2 T/4 T: L'r1. I N2 force °S39 h W (-PN2/(PN2÷PAr)πt
6 Jb 36 jl Fig. 7

Claims (4)

[Claims] (1) GaAs having the steps of forming a dirt electrode to create a Schottky barrier on a GaAs substrate, performing ion implantation using the dirt electrode as a mask, and activating the thin film by heat treatment to form source and drain regions.
s In the method for manufacturing the semiconductor device 111, the entire dirt electrode or at least the portion in contact with the substrate is a tungsten nitride film, and the dirt electrode is made of a tungsten nitride film with a nitrogen gas partial pressure ratio of 0.03 to 0.2. A reactive snowball that targets a tungsten target in a mixture of nitrogen and argon gas! A method for manufacturing a GaAg semiconductor device characterized by forming it by the ivy method. (2) The heat treatment for activating impurities in the source and drain regions is performed at 750 to 850°C.
A method for manufacturing a GaAg semiconductor device as described in 1. (3) The method for manufacturing a QaAs semiconductor device according to claim 1, wherein the patterning of the gate electrode is performed by lift-off processing using an insulating film nubasa. (4) Is the gate electrode reactive? A method for manufacturing a GaAs semiconductor device according to claim 1, in which a low abrasive metal removal layer is formed by laminating a tungsten nitride film on top of a tungsten nitride film by the ivy method.