JPS603709B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device constructed of insulated gate field effect transistors and exclusively used for reading information.

In recent years, as various electronic circuits have become faster, faster fixed memory circuits (ROMs) have also been desired.

FIG. 1 is a block diagram of a conventional ROM. Reference numeral 11 denotes a storage section in which information is fixedly stored, and when an address input is given, this storage section 11 reads out information corresponding to the address.

The information read from the storage section 11 is stored in the sense amplifier 1.
2, where the output information is detected. Figure 2 is a concrete example of the conventional ROM mentioned above, and here it is shown as C-
A dynamic ROM having a MOS configuration is shown.

In the figure, parts corresponding to those in FIG. 1 are given the same reference numerals. Further, FIG. 3 is a waveform diagram showing the operation of the circuit shown in FIG. 2. now? OT where T, is ○(V)
, address input signals AD, ~AD during the precharge period of ,
In parallel with the determination of the level of n, the N-channel MOS transistor 13 in the storage section 11 becomes conductive. When the transistor 13 conducts, 1 E (V) is applied to the capacitor 14 through the transistor 13, so T
, the capacitor 14 is precharged and given a negative charge, and the level of the node 15 is 1E.
(V). Furthermore, at this time, the output 16 of the sense amplifier 12 is ◯ (V). Then ◇T, is -E(V)
During the information detection period T2, the transistor 13 becomes non-conductive, while the P-channel MOS transistor 17 in the storage section 11 becomes conductive. During this period of T2, at least one of the address inputs AD, ~ADn is ○(V
), the negative charge stored in the capacitor 14 is not discharged to the ○(V) point, and the node 15 dynamically maintains 1E(V). Therefore, the output 16 of the sense amplifier 12 remains at ○(V), and in this case “
1" level information has been detected. Also, during the period T2, all of the address inputs AD, ~ADn become -E(V
), the negative charge stored in the capacitor 14 is A
The node 15 is discharged through the P-channel MOS transistors 8, -18n, which have gate inputs D, -ADn as gate inputs, and the transistor 17, and the level of the node 15 changes to .largecircle. (V) over the time constant of this discharge. During this change, when the level of the node 15 reaches the circuit threshold voltage V of the sense amplifier 12, the output 16 of the sense amplifier 12
is reversed and becomes -E(V). In other words, in this case “
0" level information has been detected. The speed at which information is read from the ROM in this way is determined by the capacitor 4.
What is the time constant due to the capacitance of and the series resistance of transistors 18, ~18n and 17? and depends largely on the circuit threshold voltage of the sense amplifier 12.

Conventionally, the following measures have been taken to increase the speed of the ROM. {a} Reduce the time constant of discharge from the capacitor 14. [b- Devise the circuit threshold voltage of sense amplifier 12However, 'a'
The only way to counter this is to reduce the capacitance of the capacitor 14 and further reduce the conduction resistance of the transistors 18-18n and 17 by 4. On the contrary, this tends to increase the capacitance and conduction resistance.

Therefore, the time constant cannot be reduced by 4 points without limit. Regarding the improvement of the sense amplifier 12 of 'b1,
This has major disadvantages, such as the circuit configuration becoming complicated and the chip area increasing, and various manufacturing margins being narrowed. Although various improvements have been made in the conventional ROM, it is difficult to say that much has been achieved.

This occurs because the output of the memory section 11 is directly input to the sense amplifier 12, and the output level of the memory section 11 is quickly adjusted to the circuit threshold voltage Vth of the sense amplifier 12,
This is because the circuit threshold voltage VtM of the sense amplifier 12 must be brought close to the output level of the storage section 11. This invention has been made in consideration of the above circumstances, and its purpose is to provide a semiconductor memory device that has a simple configuration, is suitable for increasing capacity, and is capable of speeding up information readout. .

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 4 is a configuration diagram when the semiconductor memory device of the present invention is implemented in a dynamic ROM having a C-MOS configuration.
The same reference numerals are given to the parts corresponding to those in FIG. 2, and the explanation thereof will be omitted. Therefore, only the configurations different from those in FIG. 2 will be explained. In the figure, a capacitor 20 is connected between the output of the storage section 11, that is, the node 15, and the input terminal of the sense amplifier 12, that is, the node 19. Further, one end of a resistor 21 is connected to the / lead 19, and between the other end of this resistor 21 and the -E(V) application point,
The signal J? applied to the gate of the transistor 13? ，
N-channel MOS transistor 2 whose gate input is
2 is connected. Similarly, one end of a resistor 23 is connected to the node 19, and the other end of this resistor 23 is connected to a voltage of 0 (V).
What is there between the application point and the application point? A P-channel MOS transistor 24 is connected to the gate of which a signal JT, which forms a complementary pair with T, is input. A pair of series circuits consisting of the resistors 21 and 23 and the transistors 22 and 24 set the level of the node 19 to a level - Eo (V) slightly lower than the circuit threshold voltage Vth of the sense amplifier 12. A voltage setting circuit 25 is configured for this purpose. That is, the transistors 22 and 24 in the voltage setting circuit 25
becomes conductive, the level of the node 19 becomes equal to the resistance R, which is the sum of the resistance 21 and the conduction resistance of the transistor 22, and the resistance 23.
and the conduction resistance of the transistor 24, which is determined by the ratio of the resistance R2, which is set in advance so that the level of the node 19 becomes the above value. It is. Next, the operation of the circuit configured as described above will be explained with reference to the waveform diagram of FIG.

First, during the precharging period of T, when the signal OT is at ○ (V), the transistor 3 is conductive and the transistor 17 is non-conductive, so the capacitor 14 has -E.
(V), the node 15 is precharged with negative charges, and the level of the node 15 becomes -E(V). Also, during the period T, both transistors 22 and 24 in the voltage setting circuit 25 are conductive, so the level at the node 19 is at a level -Eo (V ) is set. Therefore, at this time, the output 16 of the sense amplifier 12 is ○(V). Furthermore, T,
During the period, the level of node 15 is -E(V), node 19
Since the level of is set to -Eo (V), the potential difference △V between both ends of the capacitor 20 is finally IE-E
Reach ol. Next, in the signal, T becomes 1 E (V).
During the information detection period, both transistors 22 and 24 in the voltage setting circuit 25 become non-conductive, and the node 19 becomes ΔV.
It is simply coupled to node 15 via capacitor 20 having a potential of . Further, during the period T2, the transistor 13 in the storage section 11 is non-conductive, and the transistor 1
7 becomes conductive, charging of the capacitor 14 is stopped, and conversely, discharging from the capacitor 14 becomes possible. At this time, if at least one of the transistors 18, - 18n in the storage unit 11 whose gate inputs are address inputs AD, -ADn becomes non-conductive, the pre-charged capacitor 4 is not discharged. Node 15 is one E
It remains unchanged at (V). Therefore, at this time, the output 16 of the sense amplifier 12 remains ○(V). On the other hand, T2
If all the transistors 181 to 18n become conductive during the period, a discharge path is formed in the storage section 11, and the capacitor 1
The negative charges accumulated in 4 are discharged. Therefore, at this time, the level of node 15 is ○
(V) is reached. Next, the operation when the capacitor 4 is discharged will be explained in detail.

As mentioned above, during the period T2, the transistors 22 and 24
Since both become non-conductive and no new charge is supplied to node 19, as shown in FIG.
The level of 9 changes toward ○(V). At this time, as mentioned above, the initial level of node 19 is set to a level -Eo (V) that is slightly lower than the circuit threshold voltage V peak of sense amplifier 12, so the level of node 15 begins to change. And after a short period of time /
The level of the node 19 is the threshold voltage V of the sense amplifier 12.
th, is reached. That is, when discharge from the capacitor 14 starts in the storage section 11, the output 16 of the sense amplifier 12 is inverted much earlier than the level of the node 15 reaches Vth. The time required from the start of this discharge until the output 16 of the sense amplifier 12 is inverted is the initial setting level in the voltage setting circuit 25 -
As the potential difference between Eo (V) and the V skin of the sense amplifier 12 is reduced, the voltage setting circuit 25
You can freely set the initial level in .
In this way, according to the embodiment described above, the connection between the output end of the storage section 11 and the input end of the sense amplifier 12 can be made without any special devising of the time constant during discharging from the capacitor 14 or the circuit configuration of the sense amplifier 12. With a simple configuration in which a capacitor 20 is coupled and a voltage setting circuit 25 is further provided, it is possible to increase the speed of reading information.

Moreover, by appropriately setting the potential difference between the initial setting level of the node 19 - Eo (V) and the circuit threshold voltage Vth of the sense amplifier 12, the dimensions of each transistor used in the storage section 11 can be minimized. Is possible. Furthermore, the fact that there is no need to particularly devise the circuit configuration of the sense amplifier 12 means that the sense amplifier can be configured with only a simple inverter, which, together with the reduction in the dimensions of the transistors in the storage section 11, reduces the chip area. It can be downsized and can sufficiently cope with increasing the capacity of ROM. Note that the present invention is not limited to the above-mentioned embodiments. For example, in the storage unit 11, the transistors to which address inputs AD, to ADn are applied are P-channel type transistors, but this is an N-channel type transistor. Of course, it may be composed of other things.

As described above, the semiconductor memory device of the present invention has a simple structure, can increase capacity, and can read information at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a conventional ROM, FIG. 2 is a configuration diagram specifically showing the above-mentioned ROM, FIG. 3 is a waveform diagram showing its operation, and FIG. 4 is a configuration diagram of an embodiment of the present invention. , FIG. 5 is a waveform diagram showing the operation. 11... Storage unit, 12... Sense amplifier, 13, 22...
N-channel type MOS transistor, 14,'20...Capacitor, 17,18,~18n,24...P-channel type M
OS transistor, 21, 22...resistor, 25...voltage setting circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Scope of Claims] 1. A semiconductor memory device having an information storage section and a sense amplifier, and detecting information read out from the information storage section by the sense amplifier after precharging is performed in the information storage section, wherein the information storage section A capacitor is inserted in series between the information output terminal of the sense amplifier and the information detection terminal of the sense amplifier, and during the precharge period, the voltage level of the information detection terminal of the sense amplifier is brought close to the circuit threshold voltage level of this sense amplifier. 1. A semiconductor memory device comprising voltage setting means for setting a voltage. 2. The voltage setting means is inserted between one and the other of the power supplies and the information detection terminal of the sense amplifier, and is constituted by a pair of series circuits consisting of a switch element and a resistor, which become conductive during the precharge period. A semiconductor memory device according to claim 1.