JPS6236310B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic MOS memory circuit using an insulated gate field effect transistor (hereinafter referred to as a transistor).

Dynamic MOS memory circuits detect extremely small signals and discriminate information, and enable high-density integrated circuit configurations, so they require a memory circuit with a simple circuit configuration, low power consumption, and high detection sensitivity. shall be. This tendency is particularly noticeable in one-transistor random access memory (ITr-RAM), which uses transistors and capacitors as memory cells, and it is not possible to directly charge up the sense node of the sense amplifier as in conventional circuits. In a circuit configuration that uses static current, power consumption is large, and in order to prevent this, a complicated circuit configuration that is inconvenient for integrated circuit configurations is required.

An object of the present invention is to provide a memory circuit with high sensitivity and low power consumption in a simple circuit.

The dynamic MOS memory circuit according to the present invention includes a pair of transistors 1 and 2 whose drains or sources and gates are cross-connected, and a drive transistor 3 that pulls the common source of the transistors to a low potential.
and a sense node pair A of the pair of transistors,
Transfer transistors 4 and 5 that control signal transmission between B and a pair of digit lines D, a pair of bus lines (I/O), memory cells 10 and 11 and a dummy cell 1 connected to the respective digit lines
2 and 13, a pair of selection transistors are provided between the sense nodes A and B and the bus line in the precharge period and the read period, and data transmission between the sense nodes and the bus line is performed. The feature is that this is performed without using a transfer transistor.

Further, in the present invention, preferably, the memory cell and the dummy cell have substantially the same geometrical shape and are configured as an integrated circuit together with other circuit elements. Furthermore, the transfer transistors 4 and 5 operate in the triode region before the start of sensing, and are driven at the symbol _φT , which is a substantial reference potential, during the period from the start of sensing to the completion of operation of the charge-up transistor, and one Preferably, the transistor is a depletion type transistor, which reenters the triode region as the sense node approaches the reference potential.

In the MOS memory circuit according to the present invention, since the selection transistor is connected to the sense node, high-speed memory reading can be performed.

As shown in FIG. 1, a memory circuit according to an embodiment of the present invention includes a pair of transistors 1 and 1, which are cross-connected such that their gates are coupled to the drains of the other transistors.
2, and a drive transistor 3 that lowers the common source node C of each transistor 1, 2 to a low potential after the start of sensing by the rise of the drive pulse φ _S. Sense nodes A and B, which are the drains corresponding to the crossing and connecting points of the pair of transistors 1 and 2, connect the drains and sources of the transfer transistors 4 and 5 whose gates are driven by the transfer pulse φ _T to the respective digit lines D. are connected via each. These transistors 4 and 5 are depletion type transistors that exhibit low impedance when their gates are set to a reference potential (GND), as will be described later.
This embodiment has a gate value of -1.5V for a power supply voltage of 5V. The transistors in the circuit of this figure are all N-channel MOS transistors and have an integrated circuit configuration. digit line D,
are transistors 6 and 7 whose drains are connected to the intermediate voltage source line V _p whose level is approximately 1/2 of the power supply voltage V _p
When precharging is performed by a pulse φ _p applied to the gate, the power supply voltage V _p is about 2 V, which is about the middle of the power supply voltage. In addition, when the transfer transistor is in the cutoff state after the start of sensing, charge up transistors 8 and 9 whose gates are driven by the pulse _φB are used to charge the digit line _D to a potential close to the 5V power supply voltage Vp. The sources are coupled to the respective digit lines D, and the drains are connected to the power supply line _VD .

Memory cells 10, 11 and dummy cell 12,
In the integrated circuit configuration of this embodiment, 13 is a one-transistor type cell obtained in substantially the same geometric shape on the same surface of the silicon substrate. Transistors 14, 15, 16, 1 in each memory cell
In 7, the gate electrode is connected to the word line φ _Wi+1 or the dummy word lines φ _DW and φ' _DW , one of the drain and source is connected to the digit line D, and the other common end is connected to the power line V _D. It is connected to the other ends of the capacitive elements 18, 19, 20, and 21 to be coupled.

In addition, the memory circuit of this embodiment allows for a charge increase after the start of sensing the digit line D, and in order to ensure high-speed access time characteristics,
A pair of input/output lines I/O for information signals are coupled to sense nodes A and B via transistors 22 and 23 whose gates are driven by a decode output control signal Y, respectively. cross-connected transistor 1,
The common source node C of the transistors 3 and 2 is connected to the transistor 3 whose potential is lowered by applying a pulse φ _S to the gate.
It is also coupled to the intermediate power supply line V _p through a transistor 24 which charges the sense node C to an intermediate potential by a precharge pulse φ _P .

FIG. 2 is an operational waveform diagram for better understanding the operation of the embodiment shown in FIG. As shown in this figure, in the embodiment of FIG. ₁ , _the digit lines _D ,
And sense nodes A and B are charged to about 2V. Since the precharge potential V _P is lower than the power supply voltage V _D , the precharge time, ie, the reset time, can be shortened to 50 nS or less. When signal detection starts after the precharge period, the word line drive pulse φ _W and the dummy word line drive pulse φ _DW
becomes a high potential, the transistors of one memory cell and the other dummy cell of the digit line pair D extending from the sense amplifier become conductive, and the digit line potential changes in accordance with the charge of each capacitive element. The potentials of sense nodes A and B also change. Next, the transmission pulse φ _T falls to the reference potential, and the driving pulse φ _S gradually increases, thereby entering the sensing period t ₂ . Immediately after sensing starts, both transfer transistors 4 and 5 are in a cutoff state, and only the potential difference between the sense node pair A and B in the sense amplifier begins to be amplified. At this time, the digit line pair D is raised to the power supply voltage VP by applying a charge up pulse φ _B to the digit line pair _D at a high potential. Charging period for each digit wire pair
Before and after the end of _t3 , one of the transfer transistors 4 and 5 coupled to this node becomes conductive due to the drop in the potential of one of the sense nodes A and B, and one of the digit line pairs D is connected to the sense nodes A and B. creates a current path to one side of the The high potential side of the sense node and the high potential side of the digit line are kept at a charged up potential, and during the refresh period _t4 after the transmission pulse φ _T becomes high potential again, the potentials of the digit line pair V _D , V _D is the reference potential 0 and the power supply potential V _D
During this period _t4 , the control signal Y becomes high level and reading is performed. Word line φ
As the potential of _{the W} pulse φ _W falls, the refresh period is completed, and refresh information is accumulated in the capacitor of the memory cell. When the drive pulse φ _S falls and the precharge pulse φ _P rises, the precharge period again enters, and when the digit line pair D is charged to the intermediate potential within this period, the drive pulse φ _DW to the dummy word line is applied. Then, the dummy cell refresh period _t5 ends.

During this operation period, the signal transmission to the input/output line is completed near the charge-up period because the capacitance of the sense node is extremely small compared to the digit line, and there is no delay in access time due to charge-up to the digit line. Also, since the transfer transistor is substantially cut off during the charge-up period to the digit line, no charge-up current flows through the sense amplifier, and there is no electrostatic loss in power consumption. Since the memory cell and the dummy cell are compared using the same capacitive element of the same shape, information detection with excellent balance and high sensitivity is realized.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram for explaining the operation of the embodiment of FIG. In the figure, 1, 2...a pair of transistors in the sense amplifier, 3...a drive transistor that controls the potential of the common source node C, 4, 5...a digit line D, and sense nodes A, B. Transfer transistors to be coupled, 6, 7... Precharge transistor, 8, 9... Charge up transistor, 10, 11... Memory cell, 12, 13...
dummy cell.

Claims (1)

[Claims] 1 a sense amplifier having a pair of input/output terminals,
a pair of digit lines, a pair of depletion type transfer transistors connecting the pair of digit lines and the pair of input/output terminals, a pair of common data lines, and the pair of data lines and the pair of input/output terminals; a pair of selection transistors directly connected between the input/output terminals and the common data line, and data transmission between the pair of input/output terminals and the common data line is performed without passing through the transmission transistors; Before the sense amplifier is activated, it operates in a triode region, and after the sense amplifier is activated, it operates in a non-triode region until the potential of one terminal of the pair of input/output terminals approaches a reference potential. A memory circuit characterized in that it is made as follows.