JPS6034191B2 - memory circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory circuit using a Hagi insulated gate field effect transistor called an IC memory or MOS memory.

Integrated circuits using insulated gate field effect transistors are being developed into large-scale integrated circuits because they can be easily increased in density.

In particular, a large-capacity memory integrated circuit has large-capacity memory cells on a common semiconductor substrate, and realizes a high-performance, highly reliable semiconductor device. For this reason, a preferred memory cell is a one-transistor random access memory (ITR-RAM).
), transistors for switching and capacitive elements for information storage are arranged at matrix intersections where word lines and digit lines intersect, so that the MOS memory IJ' is included in the MOS memory IJ'. In this ITR-RAM, in order to prevent the capacitance value of the capacitive element from increasing as the capacity increases, it becomes necessary to add a highly sensitive sense amplifier circuit to the digit line. Conventional circuit technology couples the sense circuit and digit lines with transistors that operate in saturation. In addition, this circuit technology was introduced in 1975 by Wang's ``I.S.S.C. Technical Digest Base'75 (
ISSCCDihokostTechnica! Papers
), page 112 of ``L.○. Heller'', the sensing operation is started by a signal to the sense node that is larger than the signal oscillation of the digit line. However, in this conventional circuit technology, the precharge state of the digit line before the start of the sense operation governs the conditions at the start of the sense circuit operation, and this precharge operation is performed through a transistor in the saturated state, so both sides of the sense circuit are It takes a long time to reach the equilibrium precharge obtained at the end of precharging of the digit line, and the cycle time when performing information read operations one after another is long, and if the cycle time is shortened, the sense node is for reliable information read operations. There is a drawback that you will not be able to get a full swing.

An object of the present invention is to provide a memory circuit having a highly sensitive and highly reliable circuit configuration that provides stable read operations and short cycle times.

According to this invention, a memory having a transistor and a capacitive element is provided at each intersection of a matrix where a plurality of word lines and a plurality of digit lines intersect, and a signal generated from a memory cell to a first digit line is brought into a saturated state. a storage circuit for transmitting a digit line to a first sense node of a sense circuit through a transistor operating in saturation, and coupling a second digit line to a second sense node of the sense circuit through another transistor operating in saturation; , a charging transistor whose source is connected to the first digit line and charges the first digit line to a predetermined value before the sensing circuit starts operating; another charging transistor that charges the line to the predetermined value before the sense circuit starts operating; and a signal that has one end connected to each of the first and second sense nodes and whose other end is activated after charging the digit line. and first and second capacitors arranged in the line.

Since the memory integrated circuit of the present invention is provided with a charging transistor that charges (precharges) the first and second digit lines in advance before starting the sensing operation, the digit lines are charged quickly and reliably and are brought into an equilibrium state. , the read operation starts earlier.

Therefore, the access time and cycle time of the memory circuit can be shortened, and the speed of the memory device can be increased. Furthermore, since the precharge level of the digit line can be one step lower than the gate threshold voltage of the precharge transistor from the source line, the high level write voltage can be increased and the operation stability is excellent.

Since the sense node is charged to a sufficiently high level through the coupling capacitance from the signal line that is activated after the digit line is charged, a sense circuit with extremely high sense sensitivity can be realized. Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the invention.

In this embodiment, a plurality of word lines W, Wd, . . .
and a plurality of digit lines D, D, . . . and a plurality of digit lines D, D, . To simplify the explanation, only one address signal line 11 as a word line, one dummy address signal line 12, and digit lines D and D extending on both sides of the sense circuit 10 are shown in this figure. The dummy address signal line 12 is driven by a dummy address signal Wd when reading the information of a memory cell coupled to one digit line D, and transmits the information of the dummy cell to the other digit line D. That is, one of the drain and source of the transistor QM of the memory cell is connected to one digit line D, the other is connected to one end of the storage capacitor element CM, and the gate electrode is driven by the address signal W. Also, the dummy cell transistors Qd, . One of its drain and source is connected to the other digit line D, the other is coupled to one end of the storage capacitor element Cd2, and its gate electrode is driven by a dummy address signal Wd. Transistors Qd, . A transistor Q is also connected between the connection point between and the capacitance Cd2, and the ground, and the signal L applied to the gate causes the capacitance C of the dummy cell to increase.
This resets the potential of d2. Also, a transistor Q is connected between each digit line D, D and the sense circuit 10.
R,. , QR2, are provided respectively, and the digit line D
, D and sense nodes A and B of the sense circuit are connected to output regions called drains and sources of each transistor QR2 and QR2, respectively. Transistor QR, . ,QR2,
applies a power supply voltage Vo to the gate electrode to operate in a saturated state as described later. Also, the drain is connected to the power supply line VD, and the gate is closed.

Two precharging transistors Q are connected to the IJ charge signal line L, and their sources are connected to the first and second digit lines D and D, respectively. , Q and 2 are provided. Sense circuit 10' has sense transistors QD, . and the gate of the second sense transistor Qo2 are connected,
Similarly, the second sense node B is connected to the drain of the second sense transistor Qo2 and the gate of the first sense transistor Qo. The sources of the sense transistors QD... and QD2 are commonly coupled to the drain of a sense drive transistor Qs, and the sense circuit 10 is activated by driving the gate of this transistor Qs with a sense signal ■s. A smoothing transistor Q whose gate is connected to the precharge signal line and smoothes the first and second sense nodes A and B during precharging.
U, is connected between sense nodes A and B. The first and second coupling capacitances Cp, . , Cp2, are the boot-up signal line B that raises the potential of the sense node to a high potential at the start of sensing, and the first and second sense nodes A and B, respectively.
is connected between. All transistors and capacitive elements are N-channel insulated gate field effect type;
By configuring the memory circuit in an integrated circuit formed on the same semiconductor substrate and applying a −2V substrate voltage to the substrate, the transistor has a reference gate threshold voltage of IV.

FIG. 2 is an operational waveform diagram of the embodiment of FIG. 1.

The first and second
The digit line potentials Va, Vb and the first and second sense node potentials V^, VB are set to the charging transistor Q by setting the precharge signal L to high level, , , QL2,
By turning on, it is precharged to the same potential. In this embodiment, the boot up signal line B is activated at the same time or after the precharge signal line B falls to low level.
rises to a high level. At this time, the sense node is activated through the first and second coupling capacitances Cp,1, Cp2,
It suddenly lifts due to the tosstrap phenomenon. Next, when the address signal line 11 and the dummy address signal line 12 are driven by the signals W and Wd, respectively, an information signal of the memory cell is generated on the digit line, and the first and second coupling transistors QR, which are turned off in a saturated state, are 、． , QR illusion, a potential difference approximately five times or more of the signal potential difference produced between the digit lines is generated between the sense nodes A and B. This increasing effect increases the potential of the sense node by capacitance Cp, . , Cp2, the source and drain of the coupling transistor become saturated in terms of circuit function. In this embodiment, the digit line is precharged directly from the high power supply line VD through the precharge transistor, so the precharge period is short. Highly reliable operation is possible. In addition, the sense node potential is set to a high power supply potential V
Since the potential can be raised to the same level as or higher than o, it is possible to achieve a sense sensitivity that is about five times or more than that of a normal sense circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention.
FIG. 3 is an operation waveform diagram illustrating the operation of the illustrated embodiment. QL,. , QL2, ... precharge transistor, Q
. ,,,Q. 2, ... sense transistor, Qs, ... drive transistor, QU. ... Smoothing transistor, QR, . , QR2. ......coupling transistor,
Cp, . , Cp2,...coupling capacitance, D, a, D, b...
Digit line, A, B... sense nodes. Figure 1 Figure 2

Claims (1)

[Claims] 1. A memory cell having a transistor and a capacitive element is provided at each intersection of a matrix where a plurality of word lines and a plurality of digit lines intersect, and a first
A signal generated on the digit line is transmitted to a first sense node of the sense amplifier circuit through a transistor whose gate has a power supply voltage applied thereto, and a power supply voltage is applied to the other gate of the second sense node of the sense circuit. a charging transistor, which couples a second digit line through a transistor connected to the first digit line, has a source connected to the first digit line, and charges the first digit line to a predetermined value before starting operation of the sense circuit; A source is connected to the second digit line, and one end is connected to a transistor for charging the second digit line to the predetermined value in advance, and to the first and second sense nodes before the start of operation of the sense circuit. and first and second capacitors, the other end of which is connected to a signal line that is activated only after the digit line is charged.