KR930005783Y1 - Sense amplifier boot strap type dram - Google Patents

Abstract

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Description

Bootstrap Dram Sense Amplifier

Figure 1a is a conventional DRAM sense amplifier circuit diagram.

1B is an array structure diagram of a conventional DRAM sense amplifier.

2 is a waveform diagram of an operation of a conventional sense amplifier.

Figure 3a is a DRAM sense amplifier circuit diagram according to the present invention.

3b is an array structure diagram of a DRAM sense amplifier according to the present invention.

Figure 4 is a waveform diagram of the operation of the sense amplifier according to the present invention.

* Explanation of symbols for main parts of the drawings

1, 2: cross-coupled NMOS transistor 3: pull-down NMOS transistor

4: capacitor 6: MOS capacitor

7: delay gate 10: sense amplifier

The present invention relates to a DRAM circuit, and more particularly, to a bootstrap type DRAM sense amplifier that enables a sense amplifier of a DRAM circuit to operate at high speed.

The conventional sense amplifier circuit is composed of cross coupled transistors 1 and 2 as shown in FIG. 1A and the source connection point (SNC node) of the transistors 1 and 2 has a pull-down transistor 3 and a capacitor 4. It is a configuration that is grounded through each.

The array of conventional sense amplifiers is configured in common to the SNC node as shown in FIG. 1b. In FIG. 1b, the pull-down transistor 3 is composed of one or more transistors. Starting the discharge of the node from the pre-charge voltage to OV is the start of the sensing operation of the DRAM sense amplification.

The capacitor 4 is an equivalent capacitance that includes all capacitances of the SNC node. In general, the configuration of the sense amplifier is composed of only the cross-coupled enmoose only and cross-coupled enmoose only, as shown in FIG. There may be, but here we are based on cross-coupled enmoose and we also use Bit, Bitbar ( ) The precharge voltage of the SNC node is set to Vcc / 2. The operation state of the conventional sense amplifier will be described in detail with reference to the waveform of FIG. 2 as follows.

First, when the chip is in standby mode, Bit, Bitbar ( The SNC is precharged to Vcc / 2.

After that, when the chip starts a read operation, the information stored in the memory cell is changed to the bit bar ( ) And the voltage on the bitbar line changes by ΔV from Vcc / 2 (in this case, Assume Becomes At this time, the gate voltage VG1 of the pull-down transistor 3 goes high, and the SNC node starts to discharge from Vcc / 2 to OV. At this time, the slope of the SNC node is S1. When the NMOS transistor 2 reaches the gate-to-source voltage of V _TN , the NMOS transistor 2 is turned on so that the bitbar ( The line voltage starts to discharge to OV. (The slope of the SNC node is S2.)

In the section where the slope of the SNC node is S2, the slope S2 becomes much gentler than the slope S1 since the pull-down transistor 3 must discharge not only the SNC node but also a plurality of bit voltages through the plurality of sense amplifiers.

However, in the conventional sense amplifier circuit as described above, the SNC node When the voltage reaches one of the transistors of the sense amplifier, the transistor first 'on' and starts the sensing operation (in this case, the slope of the SNC node is S2), and the bitbar line voltage follows the SNC voltage with the slope of S2. There was a disadvantage that the sensing operation is quite slow.

The present invention is devised to solve these disadvantages and will be described in detail with reference to the accompanying drawings.

First, as shown in FIG. 3A, the cross-coupled transistors 1 and 2 constituting the sense amplifier, a pull-down transistor 3 for discharging the SNC node during the sensing operation, and a capacitor for bootstrapping the SNC node during the sensing operation. (6) and a delay gate (7) for delaying (Vb) the gate voltage (VG1) of the pull-down transistor (3) to operate the capacitor (6).

That is, the bit line Bit is simultaneously connected to the gate of the cross-coupled NMOS transistor 2 and the drain of the NMOS transistor 1, and the bit bar line ( ) Is simultaneously connected to the gate of the NMOS transistor 1 and the drain terminal of the NMOS transistor 2, and the source terminal connection point of the NMOS transistors 1 and 2 is connected to the output terminal of the delay gate 7 through the capacitor 6). The ground voltage is connected to the ground through the pull-down NMOS transistor 3 and the capacitor 4 and the gate voltage VG1 is connected to the gate of the NMOS transistor 3 and is connected to the input terminal of the delay gate 7. . An operation of the configuration circuit will be described in detail with reference to the waveform diagram of FIG. 4 as follows.

First, when the chip is in standby mode, Bit, Bitbar ( When the voltage of the SNC node is precharged to Vcc / 2, which is the initial voltage, and the read operation starts, the voltage of the bit line becomes Becomes

At this time, when the gate signal VG1 changes from 'low' to 'high', the pull-down NMOS transistor 3 is 'on' so that the SNC node starts discharging. Will be reached.

At this time, the discharge slope of the SNC node is S1 and is the same as the conventional operation.

The voltage of the SNC node When is reached, the gate-to-source voltage of the cross-coupled NMOS transistor 12 reaches V _TN , so that the NMOS transistor 2 is 'on' and the bitbar ( The line voltage is discharged at the same time The line voltage slowly discharges, but the signal Vb that delays the gate signal VG1 through the delay gate 7 changes from 'high' to 'low' and bootstraps down the SNC node through the capacitor 6. As a result, the voltage of the SNC node drops sharply due to the bootstrap effect.

So bitbars ( Since the line voltage drops along the voltage of the SNC node which is bootstraped down, it becomes much faster than the conventional method and thus enables high-speed sensing operation.

That is, the present invention bootstrap down the drive node (SNC) of the sense amplifier when the sense amplifier of the DRAM performs the sensing operation has an effect that can perform a high-speed sensing operation.

Claims (2)

A DRAM sense amplifier comprising at least one pair of cross-coupled transistors and one or more pull-down transistors, comprising: connecting at least one MOS capacitor to bootstrap a drive node of the sense amplifier during a sensing operation. Bootstrap type DRAM sense amplifier. The bootstrap type DRAM sense of claim 1, wherein the signal Vb for driving the MOS capacitor is configured to have a predetermined delay time through a delay gate than the signal VG1 for driving the pull-down transistor. amplifier.