JPS603699B2 - Memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous memory access method from a memory control device in a central processing unit of a computer to a main memory, and in particular, after a request for a memo IJ' is issued, the main memory is The present invention relates to a memory access method suitable for shortening the time required to start up a memory.

FIG. 1 shows a processing device equipped with an asynchronous memory interface.

1 is a memory device, 2 is a memory control device, 3 is an arithmetic processing device, 4 is an input/output device, 11 is a timing signal, 13 is an address signal, 14 is a transfer direction instruction signal, 15 and 16 are data signals, 21, 26 is the memory activation request signal, 22,2
7 is a data transfer direction instruction line, 23 and 28 are transfer end signals, 24 and 29 are address lines, and 25 and 30 are data signal lines.

As described above, on the conventional asynchronous memory interface, only one timing signal 11 is sent from the memory control device to the main storage device, so as shown in the time chart in FIG. The address signal 13 and transfer direction instruction signal 14 of the memory to be accessed must be determined at the time of output, and if the transfer direction is a write mode from the memory control device to the main storage device, the transfer data signal 15 is also output. It needed to have been done.

This means that the address signal 13 and the transfer direction instruction signal 1
4 and the number that is the latest to be output among the transfer data signals 15 - In FIG. It means not to obey.

On the other hand, in order to improve the reliability of the memory, within the memory control device, an activation request to the memory is output only after the parity check or protection check for the address sent from the input/output device or the arithmetic processing unit is completed.

This means that the output of the timing signal 11 is made to wait until the check circuit completes its operation. For this reason,
In the above error check circuit, if no error occurs, the output of the timing signal 11 will be delayed even though the address signal 13 has been determined a long time ago, which will reduce the responsiveness of the memory. .

This delay time is as long as several tens of ns, and the memory response time
This results in a delay of 0% to 20%. An object of the present invention is to provide the timing signal 1 from the memory control device to the memory.
1 into two signals, each of which can be output separately, thereby shortening the response time of the memory.

The present invention focuses on the fact that function signal determination indicating input/output of data to and from a dynamic ICRAM, which is recently used as an element for a large-capacity main memory device, and data determination during writing may be slower than address determination. However, by providing an address timing signal 311 that waits for confirmation of the address signal 13 on the memory interface and outputs it, and a data transfer timing signal 313 that controls the memory transfer direction and data signal transmission/reception, the address transmission can be performed. This method aims to speed up memory startup by activating the memory in advance using only the following commands.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an example of the configuration of a computer using the memory access method according to the present invention. 5 is a timing chart of the memory interface, and FIG. 6 is a detailed diagram of the memory interface signal line output circuit 33 in FIG. 4.As shown in FIG. The request is output from the arithmetic processing device 3 or the input/output device 4 to the memory control device 2 .

The memory control device 2 performs selection control and access control of the request, and outputs the memory request to the memory device 1. The present invention relates to a memory interface from this memory control device 2 to the memory device 1. When a memory request cause occurs in the arithmetic processing unit 3 and the input/output device 4, a memory request is output, but the method is the same for both the arithmetic processing unit 3 and the input/output device 4, so the following In the following, the arithmetic processing unit 3 side will be explained as an example.

Memory requests from the arithmetic processing unit 3 are sent to the address line 2.
4. After the data is output to the line 22 indicating the data transfer direction and the data signal line 25 when the data transfer is for writing to the memory, the memory activation request signal 2 is output.
This is done by outputting 1. Memory control device 2
controls access to the memory 1 in response to the memory activation request signal 21, and its method will be explained below using FIGS. 4 and 5.

When receiving the memory activation request signal 21 from the arithmetic processing unit 3 or the memory activation request signal 26 from the input/output device 4, the selection circuit 31 selects the memory request on the memory interface if the previous transfer has been completed. A signal 302 is output.

This signal 302 causes the address selection circuit 32 to operate so as to output the selected requesting address as the address signal 13 on the memory interface. On the other hand, the memory interface signal line output circuit 33 receives the memory request selection signal 302 and delays until the output of the address signal 13 is completed, and then outputs an address signal to notify the memory device 1 of the determination of the address signal 13 on the memory interface. The timing signal 311 is lowered. Thereafter, after waiting for the outputs of the check circuits 34 and 35 and confirming the transfer direction instruction signal 14, the corresponding data transfer timing signal 313 falls. On the memory device 1 side, in response to the falling edge of the address timing signal 311, the address is sent to the IC memory card.

Then, the IC memory indicated by this address starts accessing. Thereafter, the transfer direction is indicated by the transfer direction instruction signal 14 at the falling edge of the data transfer timing signal 313, and the memory operates accordingly. Next, after the IC memory operates and data reading or writing is completed, the memory device 1 notifies the memory control circuit 2 of this by lowering the end signal 314.
When the signal 314 falls, the signal 311 and the signal 313
stands up.

When the rising edge of the signal 313 is detected, the memory side also raises the signal 314 to complete the transfer and release the bus.
If there is a next memory request at this point, it will be accessed. When using the above control method, the problem is that memory activation is performed regardless of the presence or absence of an error.

That is, how to perform post-processing on the memory that has already been activated when an error is detected.
For the IC memo, the address has already been sent and the address timing signal 311 has fallen, indicating the start of the operation, so it is impossible to stop the operation midway. However, in response to this, reading only the memory itself does not affect the entire processing device, and by dividing the timing signal on the memory interface into two according to the present invention, the following can be achieved. has been resolved. Now, suppose that by checking the address line 24, it is found that a protection error has occurred in a memory write request from the arithmetic unit 3, and that an error signal 303 is output.

The error signal 303 is sent from the protection check circuit 34 to the memory interface signal line output circuit 33, as shown in FIG. FIG. 6 shows the internal logic of the memory interface signal line output circuit 33 that receives the signal 303.

When the error signal 303 is output and indicates a low voltage level, the gate 54 forcibly changes the request to a read request even if the data transfer direction instruction line 22 from the arithmetic processing unit 3 indicates a write request. This is output as a transfer direction instruction signal 14 on the memory interface.

Thereafter, the transfer direction timing signal 313 is output by setting the flip-flop 58, so that even though the memory request from the arithmetic processing unit 3 is a write request, the memory is read. Even if the memory is read, the arithmetic processing unit 3 is not controlled to take in the data, so it is equivalent to not doing anything as a whole, and the memory is protected. In this way, in the event of an error, it is possible to handle the error by changing the writing to the reading.The reason why the present invention allows the timing signal for the memo to be changed to the address transfer timing signal 311 and the data transfer timing signal 313. This is due to separation.

Next, a control method when consecutive memory requests occur will be described with reference to FIGS. 4, 6, and 7.

When the memory activation request signal 21 is output from the arithmetic processing unit 3 when there is no memory request, the selection circuit 31 outputs the signal 302.
is output, and as the address signal 13, the arithmetic processing unit 3
The signal on the address line 24 from is output.

At that time, the address timing signal 311 for the memory device 1 falls. With the timing signal 311, the IC memory designated by the address signal 13 starts operating. Next, when the signal 14 indicating the data transfer direction is output, the corresponding data transfer timing signal 31
3 falls. The memory receives this signal and executes either a write operation or a read operation depending on the level of the signal 14 indicating the transfer signal at that time.

At time 140 of the signal 14 in FIG. 7, the solid line indicates writing, and the broken line indicates reading. Next, the end signal 314
When falls, two timing signals 311 and 313
stands up. During this period, even if the request 26 is output from the input/output device 4, the selection circuit 31 will output the request signal 26 because the memory interface section is executing the transfer for the previous request from the arithmetic processing device 3. No selection is made.

However, since the address 29 has been sent from the input/output device 4 to the memory control device 2, as can be seen from FIG. 4, the parity check circuit 35 performs a parity check on the requested address. Therefore, as shown in the time chart of FIG. 7, the timing at which the address signal 13 changes from the address 130 from the arithmetic processing device 3 to the address signal 131 from the input/output device 4 is such that the instruction signal 14 indicating the transfer direction is the timing of changing from the transfer direction instruction signal 140 upon request from the arithmetic processing device 3 to the transfer direction instruction signal 141 upon request from the input/output device 4;
almost identical.

As a result, as a matter of course, the signals 311 and 313 instructing the corresponding timing also fall at approximately the same time. From the falling edge of signal 311, signal 314
The time until the rise of the address bus can be defined as the address bus occupancy time.

Therefore, of the two accesses shown in FIG. 7, in the case of a memory request when the memory interface is not used, such as the former, it is possible to notify the memory access as soon as possible. In addition, as in the latter case, when a memory interface is used, the address timing signal 311 that is normally issued earlier
is output slowly, making it possible to shorten the time occupied by the memory interface. As described above, according to the present invention, it is possible to improve the responsiveness of the memory when there is no effect, and it is possible to improve the processing performance.

[Brief explanation of drawings]

Figure 1 is a block diagram of a processing device with a slave asynchronous memory interface, and Figure 2 is its timing diagram.
3 is a block diagram of one embodiment of the present invention, FIG. 4 is a block diagram of a memory request receiving circuit, FIG. 5 is a timing chart of FIG. 3, and FIG. 6 is a diagram of memory interface signals of FIG. 4. FIG. 7, which is a detailed diagram of the line output circuit, is a time chart during continuous transfer. 1...Memory device, 2...Memory control device, 3...
- Arithmetic processing unit, 4... Input/output device, 13... Address signal, 14... Transfer direction instruction signal, 15, 16...
Data signal, 311...address timing signal,
313... Timing signal for transfer direction. Sai 1 figure spear 3 figure Sai 2 figure Shio 4 figure O 5 figure O 6 figure Power 7 figure

Claims (1)

[Claims] 1. In a memory access method for asynchronously accessing a memory device from a memory control device, a timing signal supplied from the memory control device to the memory device is
A memory access method comprising an address timing signal indicating address confirmation and a data transfer timing signal indicating data transfer timing, and each signal is output at independent timing. 2. The memory access method according to claim 1, wherein a signal indicating the data transfer direction is output in accordance with a data transfer timing signal.