JPS6035566A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase both of the integration density of an MOS-RAM memory cell and the accumulated capacitance by a method wherein an aperture the first insulation film has is filled with the first conductive film, further the second insulation film is formed by lamination so that at least part of the surface of the first conductive film may be exposed, thereafter the second conductive film if formed. CONSTITUTION:A thin oxide film 33 is formed on the surface of an Si substrate 30, and thereafter boron ions B<+> are implanted to the Si substrate 30 with a photo resist mask 34 as a mask, resulting in the formation of a p<+> layer 35. Next, the film 34 is removed after etching of the oxide film 33 with the film 34 as a mask, the polycrystalline Si 36 of the first layer doped with a high concentration n type impurity being deposited, and next an insulation film 38 of high dielectric constant being deposited on the polycrystalline Si. Then, the insulation film 38 and the Si 36 are etched by the method of plasma etching at the same time. Thereafter, the polycrystalline Si 39 of the second layer containing a high concentration n type impurity is deposited, and the pattern is formed by photo etching so as to cover the film 38. The oxide film 33 is removed, and a thin gate oxide film 40 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor GLI device having a small interconnect capacitance.

C Background of the Invention There are various forms of MOS-RAM,
The one with the smallest number of transistors is the one-transistor type MO
8-RAM. Conventional 1-transistor type MO3-R
As shown in FIG. 1, AM is a memory cell consisting of an insulated gate field effect transistor (hereinafter referred to as MOS transistor) 1 for switching and a capacitor 2 for storing information, and a memory cell consisting of an AQ electrode 3. Selection is made by a data line consisting of a word line and a diffusion layer 4. Here, 5 is a Si substrate, 6 is an insulating film (SiO
, etc.), 7 is a gate insulating film (S io, etc.).

AI2. o3. 8 is the first layer polycrystalline silicon electrode, 9 is an interlayer insulating film (SiO, etc.)
, 1° is a diffusion layer which becomes a source or drain together with the above diffusion M4, 11 is an inversion layer produced by applying a voltage to the polycrystalline silicon electrode 8, and 12 is a polycrystalline silicon electrode (gate).
-), and the capacitor HL2 is formed between the polycrystalline silicon electrode 8 and the inversion layer 12.

As shown in Figure 1 to 4 above, since the capacitor 2 for storing information is simply arranged two-dimensionally on the same plane as the switching transistor 1, the area of the memory cell is large. . Further, in the IMOS transistor type RAM, the charge stored in the storage capacitor is proportional to the read voltage, and it is desirable that the read voltage is large in terms of the circuit. Therefore, it is desirable that the storage capacitance be large in order to extend the charge retention time and operate the circuit stably.

However, in order to increase the storage capacity, it is necessary to increase the area of the capacitor section, which reduces the degree of integration.

The present inventors previously disclosed in Japanese Patent Application Laid-Open No. 53-4483 that by three-dimensionally stacking capacitor portions that store electric charges, the vertical direction of the device is actively used to increase the integration density.
We proposed a memory cell with a configuration that increases storage capacity. Figure 2 shows this stacked type IMOS transistor RAM (hereinafter referred to as STC).
FIG. As shown in FIG. 2, a diffusion layer 1 that becomes the source or drain of the insulated gate field effect transistor 1
0 and forming a conductivity type opposite to that of the substrate 5 (
Although an opposite conductivity type region may be formed by an impurity layer, an inversion layer is used in this embodiment). An interlayer insulating film 14 for forming a capacitor is provided on the application electrode 8. Then, a counter electrode 1 is placed on top of it.
5, one end of which is connected to the diffusion Wf10.

Thereafter, a glabellar insulating film 9 and an AQ electrode 3 serving as a word line are provided as in the conventional case.

In this way, the electrode 8 and the counter electrode 15 have a capacitance of C! through the interlayer insulating film 14. and its storage capacity is C+
+Cox+Cn. Note that Co has an oxide film 7.
CD is a capacitor formed between the inversion layer 11 and the electrode 8 via a depletion layer, and between the inversion layer 11 and the substrate 5 via a depletion layer.

That is, as shown in FIG.
By adopting a structure in which the electrode 15 is provided on the electrode 8 via the electrode 8, the storage capacity can be increased by the capacity CI compared to the conventional Cow+G o. Therefore, if the same value as the storage capacity of a conventional memory cell is used, the area of the memory cell can be significantly reduced.

This STC memory has the advantage that by stacking the capacitor section on the element, the insulating film 14 forming the capacitor can be arbitrarily selected, and Si, N4 films, etc. having high dielectric constant can be used.

However, in this STC memory, in order to increase the storage capacity, a thin Si3N film is used as the M edge film 14.
When using a membrane, there is a limit to the increase in storage capacity due to problems such as leakage current. Furthermore, since the diffusion layer 10 connected to one electrode of the storage capacitor is in direct contact with the low-density stoppage substrate 5, there is a loss of charge due to external noise including radiation, which contributes to memory malfunction. .

Further, as an improvement of the IMOS transistor type RAM shown in FIG. 1, there is a capacitor-embedded structure proposed in Japanese Patent Laid-Open No. 53-34435. As shown in FIG. 3, this embedded capacitor memory has a storage capacitor of the same conductivity type as a diffusion layer 13 which becomes the source or drain of the M green gate field effect transistor 1 and a substrate 5 provided below it. This utilizes a pn junction between the impurity-dense region 16 and the impurity-dense region 16.

This embedded capacitor type memory has a storage capacitor part embedded in the substrate, and compared to the storage gate structure of the memory shown in Figure 1, it does not use an electrode 8, so it does not require multilayer wiring and has a small area. It is a memory cell.

However, in this capacitive embedded memory, there is a limit to the capacity increase due to the leakage current of the pn junction and the withstand voltage. Furthermore, since the capacitance per m area of the pn junction is smaller than the capacitance of an oxide film or the like, a large amount of serum is required to obtain a large storage capacity, which is disadvantageous in terms of the degree of integration.

Further, conventional semiconductor memories generally have a large capacitance between the substrate and the wiring, which is one of the causes of lowering the signal voltage from the memory cell.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can increase both the integration density and storage capacity of a MOS-RAM memory cell compared to conventional MOS-RAM memory cells.

[Summary of the invention]

In order to achieve the above object, the present invention fills the flowering portion of the first insulating film with a first conductive film, and further provides a second conductive film such that at least a part of the surface of the first conductive film is exposed. After the insulating films are laminated and formed, a second conductive film is formed.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

Embodiment 1 FIGS. 4(A) and 4(B) are a sectional view and an equivalent circuit diagram showing a first embodiment of the IMOS transistor type memory cell of the present invention.

In the memory cell shown in Figure 4, the storage capacitor ice is composed of two capacitors, one of which is a nitride film (Si, N, film) with a high dielectric constant or an alumina film (AQ203 film).
The insulating film capacitor Ca I N is formed by sandwiching an insulating film 21 such as a polycrystalline silicon layer 21 between the first polycrystalline silicon layer 22 and the second Wj polycrystalline silicon layer 23;
This is a depletion layer CJ between the pn junction formed by the n+ type layer 24 formed in the substrate 26 and the p00 film 25. Further, in the memory cell shown in FIG. 4, the address MOS transistor 1
are the n0 type layers 24 and 27 which become the source and drain, the gate insulating film 28, and the gate electrode 2 made of third layer polycrystalline silicon.
Consists of 9. In addition, in FIG. 4, 201 is a data line, 202 is a word line, and 203 is a DC bias potential (positive predetermined voltage V a a or ground potential V11) applied to the electrode 23.
This is the line that gives

The two capacitances Cal N and CJ are MOS shown in Fig. 4 (B).
・As shown in the equivalent circuit of RAM memory cell,
Address MO8) - connected in parallel to transistor 1, and the entire memory cell? ? fff capacity Ca is Ca l
It is the sum of N and Cj. Two volumes 1cat++ and C.

Because they are three-dimensionally formed in the same location, a large storage capacity can be obtained with a small area.

moreover? 9 n that is in contact with the ffl pole 22 on one side of the claw
Since the + diffusion layer 24 is almost covered by the high concentration p-type layer 25, a potential barrier is formed between the n゜ diffusion layer and the low concentration p-type substrate 26. Therefore, even if charges flow into the memory cell section due to external noise such as radiation, the existence of a potential barrier prevents the charges from entering the n'''' diffusion layer of the storage capacitor section, increasing noise resistance. .

If the cell area is 60 .mu.M and the address MOS transistors have the same configuration, the storage capacitance values of the MOS/RAMs shown in FIGS. 1 to 4 are as follows.

■ MOS-RAM in Figure 1 Conditions 1) Thickness of the Sin2 film 7b Tox = 35 nm m1t
) Sheet resistance of polycrystalline S in8 = 40Ω/accumulation capacitance C8”Cox = 100 x 10-'P F/bit
■ MOS-RAM in Figure 2 1), ji) Same as above.

iii) Film thickness T' of the insulating film (S3.N4 film) 14
st*=35 n rn Storage capacity Cax Cai*+ Cox= 250 X IO−
' P F /it ■ MOS-RAM in Figure 3 Conditions i) Impurity concentration of n+ layer 13 = 10" to 10"cm-' it) p" [Impurity concentration of 16 = 8 x 1016 mark-3 Storage capacitance Cs =C4= 50 x 10-'P F/bit■
MOS-RAM (present invention) conditions 1) Film thickness of Si, N4 film 21 in FIG. 4: Tai*, = 35 n
m1f) Impurity concentration of n'''' layer 24 = 10''-1020
an-”in) Impurity concentration of P+ layer 25=8×10”a! 1-
3 W volumetric star Ca=C5t*+C, 1:450 X 10-'P F
/it In each of the above MO8-RAMs, the address MOS transistor 1 has a p-type Si substrate (impurity concentration 5×10"an-'
) with a depth of 0.3 μm and an impurity concentration of 1020 to 1021 CI11-', an n' type source and drain region 24.27 (10,4), and a film thickness of 35 n.
m S j, 02 film (gate insulating film) 28 (7) and sheet resistance 30 Ω/mouth polycrystalline silicosoga-1 to electrode 2
Consists of 9 (12).

Embodiment 2 FIGS. 5(A) and 5(B) show a memory cell cross-sectional view and an equivalent circuit diagram of a second embodiment of the MOS-RAM of the present invention.6 In the embodiment of FIG. 5, FIG. Similar to the example shown in
The storage capacitance ice is the insulating film capacitance Cn i n and the junction capacitance fl
In this embodiment, it is composed of both cc and +.

Polycrystalline layer 22.23 L: Y')
Insulating film capacitor 731 sandwiching S j, 3N 4vA21
C5tN is formed extending over the address M and the gate electrode 29 of the OS transistor 1. Therefore, the area of the insulating film capacitor section becomes large, and the capacitance value Ca I
The ni gets bigger.

The pn junction capacitance, +, between the 03 layer 24 formed in the silicon substrate 26 and the top 5 of the P'' layer 2 is the same as in the embodiment of FIG. Therefore, in the memory cell of this example,
The overall storage capacity C8 can be increased while maintaining a high degree of integration. The same strip as ■ in Example 1, Cm
= 650 x 10-'PF/bit.

In addition, 204 is a bias application full 4M for cord separation.
(Polycrystal 5i) 205 is a terminal for applying a ground potential.

In the memory cell shown in FIG. 5A, the gate electrode 29 is formed by forming the first polycrystalline layer 5iW1, 22, and 23 as the second layer and third layer polycrystalline layer 5IWJ, respectively.

Embodiment 3 FIGS. 6(A) and 6(B) show a memory cell sectional view and an equivalent circuit diagram of a MOS-RAM according to a third embodiment of the present invention.

The storage capacity of this memory cell is implanted from three capacitors, and the first capacitor is a nitride film sandwiched between the polycrystalline silicon 22 of the first layer 11 and the polycrystalline silicon 23 of the second layer. Capacitance Ca I N due to the insulating film 21 such as or alumina film
The second capacitance is the oxide film 28 between the first layer polycrystalline silicon 22 and the 11'' layer 24 in the silicon substrate 26.
′ by Cox.

The third layer is the N4 layer 24 formed on the silicon substrate 26.
is the depletion layer capacitance C4 due to the junction of and P''ff125.

All three capacities are three-dimensionally formed in the same location,
A large storage capacitance C8 can be obtained with a small area, and the value of the storage capacitance C11 can be 3.5 times to 4 times that of the conventional memory cell of FIG. 1, which has the same area and consists of only oxide film capacitance.

Note that 206 is a line for setting the polycrystalline Si electrode 22 to the ground potential.

Example 4 FIGS. 7(A) and 7(B) show the MOF3-RAM of the present invention.
A cross-sectional view of a memory cell and an equivalent circuit diagram of the fourth embodiment are shown.

This memory cell has a structure with the largest storage capacity among the previous embodiments. The major feature of this memory cell that is different from the above-mentioned memory cells is that a plurality of n*-P" junctions formed in the silicon substrate are stacked in multiple stages, and the sum of their depletion layer capacitances becomes the storage capacitance C6. By adding the capacitance due to the insulating film to these capacitances, a very large Wfff capacitance is realized.

The present invention can be applied to all of the various types of memory cells mentioned above. The structure shown in FIG. 7 is obtained by applying the structure of this embodiment to the memory cell shown in FIG. 6, and the storage capacitor Ca is composed of at least five capacitors. That is, the first capacitance is the capacitance Ca due to the insulating film 2 such as a nitride film or alumina film sandwiched between the polycrystalline silicon 22 of the first RyJ and the polycrystalline silicon 23 of the second layer 11.
The second capacitance is the capacitance Jt Co y= due to the oxide film 28' between the first layer polycrystalline silicon 22 and the silicon substrate 26 II'Wj24a, and the third capacitance is is the depletion layer capacitance cJ between n′″WJ24a and p′″WJ25a, and the fourth capacitance is the p+ layer 25a.
The depletion layer capacitance Ca 2 between a and the n3 layer 24 and b is the fifth capacitance, and the fifth capacitance is the depletion layer capacitance 0.5□ between the n"J!!724b and the 24 layer 25b. The depletion layer capacitance can be increased within the range allowed by the manufacturing process.Each n1 layer is connected by the n9 layer 24C having a deep diffusion depth, and each depletion layer capacitance is all connected in parallel.Therefore, the depletion layer capacitance is connected in parallel. Volume of memory cell according to this structure, 5
1 cn is a very large value, which is 5 to 10 times that of the conventional memory cell shown in FIG. 1, which consists of only oxide film capacitance in the same area.

Embodiment 5 Next, a planar structure of a memory cell of M, 08-RAM according to the present invention will be explained. FIG. 8 shows one example of a memory cell according to the present invention, taking the memory cell shown in FIG. 4 as an example. Wf^ This is the shaded area in the capacitance diagram, and this area has high dielectric constant insulating film capacitance and p
N-junction capacitors are stacked three-dimensionally. Therefore, in this design example, the storage capacity of the memory cell, 1lca, is 4.5 times as large as that of a conventional memory cell that has the same surface area and consists of only oxide film capacitance, and is highly effective for the operation of large-capacity MO8-RAM. It is possible to stabilize it.

Example 6 Next, a process for manufacturing a memory cell according to the present invention will be described. The case of an n4-p""" junction stage and the case of a multi-stage junction formed in a silicon substrate will be described. FIG. 9 shows an n""
This is a manufacturing process of a memory cell having one stage of -p4 junctions and having the structure shown in FIG. Low concentration p-type silicon substrate 3
0 was oxidized by a selective oxidation method, and 0.5 to 1μIll of 1
7.Feel 1~rdI film (Sin,) 31 and +
Form layer channels I and brim 32 (FIG. 9(A)
), 30-50 nm thin oxide IF'f (Sin
) 33 is formed on the surface of the silicon substrate 30, and then boron ions B are irradiated using the photoresist film 34 as a mask.
At high energy of 50-400KeV, 1=3X10”
Implant into the silicon substrate 31 about cm-2, p4 layer 35
(Fig. 9(B)). Next, the photoresist film 34
After etching a thin oxide film (SiO,) 33 using as a mask, the resist film 34 is removed and the first layer of polycrystalline silicon 36 doped with high concentration n-type impurities is etched at 6.1°C.
~0.3 μm is deposited, and then a 20-50 nm high dielectric constant insulating film 38, such as a thin nitride film or alumina film 38, is deposited on the polycrystalline silicon. In this case, in the region where the polycrystalline silicon 36 and the silicon substrate 30 are in direct contact, the glue-type impurities in the polycrystalline silicon diffuse into the silicon substrate! A layer 37 is formed (see FIG. 9(C)).
)). Next, the insulating film 38 and the polycrystalline silicon 36 are simultaneously etched using a plasma etching method (see FIG. 9(D).
)). Thereafter, a second layer of polycrystalline silicon 39 containing high concentration rI type impurities is deposited to a thickness of 0.2 to 0.4 μm, and a pattern is formed by photoetching to cover the insulating film 38 (FIG. 9(E)). Next, a thin oxide film (SiO
z ) 33 is removed and oxidized at a temperature of 800 to 1000 DEG C. to form a -thin gate oxide film (Sin, ) 40 of 20-50 nm. In this case, since the second layer of polycrystalline silicon contains a high concentration of n-type impurities,
0-200 nm thick oxidation n% (Sin,)41
is formed. Thereafter, a gate electrode 42 is formed using a third layer of polycrystalline silicon or a metal such as aluminum, molybdenum, or tungsten, and using this as a mask, a highly doped n-type diffusion layer 43 is formed in a self-aligned manner (9th layer).
Figure (F)). Thereafter, four PSG films of 0.5 to 1 μm are stacked, contact holes are made, and finally an aluminum electrode t445 is formed (FIG. 9(G)). Here the 91st s.
The reason for implanting boron ions B'' with high energy in the step (13) is to obtain a large depletion layer capacity6
That is, as shown in FIG. 10, boron ions are implanted into silicon at a high energy of, for example, 300 to 4001 (eV) and heat treated at 100°C for about 20 minutes. Internal 0.6
It comes to have a peak in a region as deep as μIn.

Such p0 layer and n'' layer (unusable material concentration distribution 103)
Compared to the depletion layer capacitance between the p1 layer and n''ff, which has a peak on the silicon surface, as shown in distribution 102, the depletion layer capacitance between The depletion layer capacitance is obtained.
Depletion layer capacitance according to distribution 101 in Figure 0 and distribution 102
The dependence of the depletion layer capacitance on the applied voltage by
, 112.

Embodiment 7 FIG.
This is a manufacturing process of a memory cell having the structure shown in the figure. Partially indented on the surface of the low concentration p-type silicon substrate 46 n+
-p junction is formed by ion implantation or thermal diffusion. In this case, the 24 layers 47 are made of boron and 0
The 0 layer is divided into two regions: a region 48 doped with an impurity having a small diffusion coefficient such as arsenic or antimony, and a region 49 doped with an impurity having a large diffusion coefficient such as phosphorus. Thereafter, a thin oxide film (Sin) 50 with a thickness of 10 to 50 nm is formed on the surface of the silicon substrate 46, and boron ions 52 of 1012 to 1012 are applied to the surface of the 01 layer 48 using the photoresist film 51 as a mask.
Implant 1013G-2 ions (Figure 12 (A))
Next, after removing the oxide film 50 and photoresist film 51 on the surface of the silicon substrate, a low concentration p-type silicon layer 53 having an impurity concentration similar to that of the substrate is formed on the surface of the silicon substrate by approximately 1.
It is grown by μm epitaxial method. In this case, n
The boron impurity ion-implanted into the surface of the I layer 48 is also added into the epitaxial p-type layer to form a p+ layer 54. Furthermore, the n" layer 49 doped with an impurity having a large diffusion coefficient such as phosphorus extends into the epitaxial p-type layer during epitaxial growth, and has a deep diffusion depth.
"W2B5 is formed (Fig. 12(B)). After that,
A 0.5-1 μm field acetylated film (
Sin2) 56 and a p-type layer channel stopper 57 are formed.

Next, a thin oxide film (S102) of 20-50 nm 5
8 is formed on the surface of the epitaxial cell p-type layer, and using the photoresist film 59 as a mask, an n-type impurity 60 such as phosphorus arsenic is added to the surface of the epitaxial cell p-type layer.
13~1014an-'' ion implanted 11 layer layer 61
(Fig. 12(C)). Next, a first layer of polycrystalline silicon 62 is deposited to a thickness of 0.1 to 0.3 μm, and a high dielectric constant insulating film 63 of 20 to 50 nm is formed on top of this, such as a nitride film (sxiN4) or an alumina film (A
Q, 03) is formed. Thereafter, a thin oxide film (Sin-) 64 of 0, 3 to 0, 5 p tn is formed on the side surface of the polycrystalline silicon 62 by an oxidation process (see FIG. 12(D).
)). Next, after partially removing the thin oxide film (Sin2) 58, a 0.2-0.3 m layer of second layer polycrystalline silicon 65 containing a high concentration of n-type impurities is deposited (see Fig. 12). E
)).

Next, after removing the thin oxide film 58, the thin goo 1-oxide 11! i (Sin,) 6 B to 20-50 n
10 m is formed on the second layer polycrystalline silicon 65.
A thick oxide film (Siow) 67 of 0 to 200 nn+ is formed. Next, with the third layer of polycrystalline silicon,
Alternatively, a gate electrode 68 is formed from a metal such as aluminum, molybdenum, or tungsten, and a high concentration n-swelling diffusion layer 69 is formed in a self-aligned manner using this as a mask (12th
Figure (F)). Next, seven PSG films of 0.5 to 1.0 μm are stacked, contact holes are made, and finally aluminum electrodes 71 are formed (FIG. 12(G)).

As described above, the present invention makes it possible to realize a dynamic memory cell with high integration density and large storage capacity.
Stable operation of IMO8-RAM becomes possible.

Is the structure according to the present invention larger? ? Although a memory cell with an M-capacity can be obtained, it is necessary to reduce the parasitic capacitance of the data line in order to further increase the signal voltage.

Embodiment 8 The structure shown in FIG. 13 is obtained by adding a structure that further reduces the data line capacity to the structure according to the present invention described in section 2.6 In other words, the MOS/RAM memory cell shown in FIG. Walk straight ahead, after making a contact hole in the PSG tear 2 of the 1st layer, cover the contact 1 hole with polycrystalline Si or Δl1173, and then add two more layers of PSG film 74 with a thickness of 0.5-1.0 μm. The contact 1 hole was opened again and a data line was formed using AQ75. With this structure, the psal under the AQ wiring 75 can be made about twice as thick as the conventional structure, and accordingly
The parasitic capacitance of the Q wiring is also reduced to 1/2. Therefore, the signal voltage from the memory cell becomes even larger due to the increase in storage capacitance and the decrease in data line capacitance.

〔Effect of the invention〕

As described above, according to the present invention, a dynamic memory cell with high integration density and large storage capacity can be realized, and stable operation of Daikan iM and 03-RAM is possible.

[Brief explanation of the drawing]

FIGS. 1, 2, and 3 are cross-sectional views showing the structure of a conventional MOS-1tA memory cell, and FIGS. 4 and 5. 6 and 7 are diagrams showing the cross-sectional structure and equivalent circuit of an embodiment of the MOS-RAM memory cell of the present invention, and FIG. 8 is a diagram showing an example of the planar pattern of the MOS-RAM memory cell of the present invention. Figure 9 is a cross-sectional view showing an example of the manufacturing process of the MOS/RAM memory cell of the present invention, Figure 10 is a diagram showing the concentration distribution of the impurity layer forming the pn junction capacitance, and Figure 11 is the difference in the impurity concentration distribution. Figure 12 shows the difference in applied voltage dependence of p 1+ junction capacitance due to
FIG. 13 is a sectional view showing another example of the manufacturing process of the AM memory cell, and FIG. 13 is a sectional view showing another embodiment of the MOS-RAM memory cell of the present invention. 20...Field oxidation III (Sin, etc.), 21
... Insulating film for capacitive part (S i, N4. A Q, 03
etc.), 22° 23... Enemy part electric te < polycrystalline silicon layer), 24... n0 type impurity layer, 25... 1++
type impurity layer, 26...p type silicon substrate, 27...n
"type impurity layer, 28... gate insulating film (Sin2 etc.)
, 29...gate electrode (polycrystalline silicon or metal), 2
01...Data line, 202...Word line, 203...
・Bias PIA (ground or VJ 1 No. 2121 VJ3 Figure 4 (A), 8. Le No. 5 (C) Figure 6, f17121 (8) χ δ Figure 9 Figure 10 → Silicon J (Surface size 9-7,! (μm) Figure 12 (Hen (D)) 13th mouth

Claims (1)

[Claims] forming a first insulating film having a flowering portion on a semiconductor substrate; filling the flowering portion with a first conductive material film; and at least a portion of the surface of the first conductive material. forming a second insulating film on the first insulating film so as to expose the second insulating film; and extending the second insulating film from the exposed surface of the first conductive material film onto the second insulating film. A method of manufacturing a semiconductor device, comprising the step of forming a second conductive material film.