JPS6035560A - Manufacture of n-well complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To enable the reduction of processes and cost and the prevention of short-channel effect and punch-through by a method wherein the second impurity layer is formed in adjacency to the source-drain impurity layers of an N-channel transistor. CONSTITUTION:The part other than the source-drain forming regions of the N-channel transistor 200 is covered with a photo resist film 7, and then arsenic ions 8 are implanted. Next, the film 7 is removed and annealing is carried out, resulting in the formation of the source-drain impurity layers 10 of the transistor 200. After BF or BF2 ion implantation 9, the source-drain impurity layers 11 of a P-channel transistor, the source-drain impurity layers 10 of the N-channel transistor, and BF or BF2 impurity layers 11' adjacent thereto are formed by annealing. The impurity concentration is controlled by the conditions of BF or BF2 ion implantation and those of annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for manufacturing an N-well complementary semiconductor device, which is intended to shorten process steps and reduce manufacturing costs.

(Prior art) Conventionally, in semiconductor devices C (for example, EFROM, RAM, CCD) using NMO8 transistors,
The circuit section with high power consumption is converted into a CMO8 circuit, and the NMO
8) It was desired to integrate the transistor and the 0MO8) transistor into one chip on the same semiconductor substrate. By making the 0M08 part a structure with an N-well region, the manufacturing process related to the NMO8IC part can be made relatively simple. It can be done.

Here, a method for forming source/drain regions in a conventional N-well complementary semiconductor device will be described with the process order as side notes.

(1) Cover the entire P-channel transistor with a photoresist film.

(2) Using the photoresist film as a mask, As ions are implanted into the source/drain regions of the N-channel transistor. The conditions for ion implantation at this time are 4
It is performed at an energy of 0 KeV and an impurity density of IE 16 cln-''.

(3) Coat the photoresist film to 0. Remove with plasma.

(4) High-temperature annealing of the entire semiconductor substrate in dry nitrogen at 1000'C for 60 minutes to eliminate arsenic impurities of ~0.5μ
The joining depth is m.

(5) Next, cover the entire N-channel transistor with a photoresist film.

(6) Using the photoresist film as a mask, implant boron ions into the source/drain regions of the P-channel transistor. The ion implantation conditions at this time are:
At an energy of 40 KeV, the impurity density is I Ecm-''.

(7) Remove the photoresist film using 02 plasma.

(8) Next, annealing is performed for 1 time to activate Poron.
The test is carried out for 30 minutes in dry nitrogen at 000°C.

By the above method, the source and
When a drain is formed, there is a drawback that photolithography is required twice in the process of forming a photoresist film for selectively implanting arsenic and poron ions.

Further, problems such as short channel effect and punch-through in fine MOS transistors were also inherent.

(Object of the Invention) The present invention has been made to eliminate the above-mentioned conventional drawbacks, and is to provide an N-well complementary semiconductor device that can shorten the process, reduce manufacturing costs, and prevent short channel effects and punch-through. It is an object of the present invention to provide a manufacturing method for an N-well complementary semiconductor device.
A gate oxide film and gate polysilicon are sequentially formed in an active region of a semiconductor substrate having a well layer and an oxide film in a field region, and the source/drain regions of a P-channel transistor and an N-channel transistor are all formed, and an N-channel transistor is formed. ion implantation of impurity for source/drain formation into the active region of the N-channel transistor, and annealing by implanting ions into the active region of the N-channel transistor to form a source/drain impurity layer of the N-channel transistor;
After forming the source/drain impurity layer of the N-channel transistor, ions are implanted into the active region of the P-channel transistor and annealing is performed to form the source/drain impurity layer of the P-channel transistor.
A second impurity layer is formed adjacent to the source/drain impurity layer of the channel transistor.

(Example) Hereinafter, an example of the method for manufacturing an N-well complementary semiconductor device of the present invention will be described with reference to the drawings.

1 to 4 are process explanatory diagrams of one embodiment of the present invention, in which cross sections of N-channel and P-channel transistors of a complementary semiconductor device having an N-well formed on a P-type semiconductor substrate up to the gate region of the transistor are shown. It shows the structure.

First, as shown in FIG. 1, an N-type impurity layer 2 is formed on a P-type semiconductor substrate 1 of 20 to 30 Ωα with an N-type impurity at a density of ˜I E 16 cm −3 .

Next, Sin with a thickness of 1 μm in the field region.

A film 3 is formed by thermal oxidation, and then a gate oxide film of 500 mm and a gate polysilicon 5 of 4000 mm are sequentially formed in the active region. At this time, at the same time, the source/drain region 6 of the P-channel transistor 100 and the source/drain region 6' of the N-channel transistor 200 are
is also formed.

Next, as shown in FIG. 2, areas other than the source/drain forming regions of the N-channel transistor 200 are covered with a photoresist film 7, and arsenic, which is an impurity for forming the source/drain of the N-channel transistor 2000, is heated at 40 KeV.
Ion 8 is implanted under the condition of "I El 6cy+-".

Next, as shown in the third diagram, the photoresist film 7 (for example, thickness 8000λ) is removed using O plasma, and further annealing is performed to activate arsenic ions and diffuse arsenic into the semiconductor substrate 1. The process was carried out for 10 to 30 minutes in dry nitrogen at 1000°C, and the N-channel transistor 200
Source/drain impurities 1 and 10 are formed.

Next, BF or BF2 ions, which are impurities for forming the source and drain of the P-channel transistor 100, are added to ]0
Ion implantation 9 is performed under the conditions of IE 15crn-'' at i(eV or higher).

Next, as shown in Figure 4, the temperature is further increased to 900-1000°C
Anneal for 30 minutes in dry JgM nitrogen. By this annealing, for example, 1
The source/drain impurity layer 11 with an impurity concentration of 01s to 10"cm-", the source/drain impurity layer 10 of the N-channel transistor, and the BF or BF with an impurity concentration of 10" to 10"cm-" formed adjacent thereto.
2 impurity ill' is formed.

The impurity concentration at this time is controlled by the implantation conditions of BF or BF2 ions and the annealing conditions. The impurity distribution along line AA' in FIG. 4 is shown in FIG.

This Figure 5 shows the depth on the horizontal axis and the impurity concentration on the vertical axis. In the figure, 101 is As (arsenic), 9.102 is BF or BF2.103 is the substrate. Indicates concentration.

As explained above, in the first embodiment, the impurity distribution as shown in FIG. 5 is obtained in the source/drain impurity layer of the N-channel transistor.
Since the BF or B F 2 impurity layer 11' is formed, the spread 9 of the depletion layer from the drain region 10 can be suppressed) and channel through can be prevented.

Furthermore, the number of photolithography steps required to form the sources and drains of the P-channel transistor 100 and the N-channel transistor 200 can be reduced by one.

(Effects of the Invention) As described above, according to the method of manufacturing an N-well complementary semiconductor device of the present invention, a gate oxide film and Gate polysilicon is sequentially formed, and the source/drain regions of the P-channel transistor and N-channel transistor are formed, and impurity ions for forming the source-drain are implanted into the active region of the N-channel transistor. Ions are implanted and annealed to form the source/drain impurity layers of the N-channel transistor. After forming the source/drain impurity layers of the N-channel transistor, ions are implanted into the active region of the P-channel transistor and annealed to form the P-channel transistor. By forming the source/drain impurity layer of the channel transistor and forming the second impurity layer adjacent to the source/drain impurity layer of the N-channel transistor, short channel effect and bunch-through of the fine MOS transistor can be prevented. can.

In addition, the photorin required for forming the source and drain of P-channel transistors and N-channel transistors is
Graphics can be performed in one go, high voltage resistance, high integration,
It can be used to manufacture semiconductor devices aiming at high yield and low power consumption.

[Brief explanation of the drawing]

1 to 4 are process explanatory diagrams of an embodiment of the method for manufacturing an N-shell complementary semiconductor device of the present invention, and FIG.
The figure is a diagram showing the impurity distribution along the line AA' in FIG. 4. 1... P-type semiconductor substrate, 2... N well layer, 3...
・5in2 film, 4... Gate oxide film, 5... Gate polysilicon, 6, 6'... Source/drain region, 7... Photoresist, 8... Ion, 9... Ion implantation , 0゜11...source/drain impurity layer, 11'...BF' or BF2 impurity layer, lOO.
...P channel transistor, 200...N channel transistor. Procedural amendment dated May 23, 1980 Kazuo Wakasugi, Commissioner of the Patent Office 1, Indication of the case 1981 Patent Application No. 143689 2, @ Ming name N-well complementary half-frame body II! 1. Chimei method 3, relationship with the case of the person making the amendment Patent Applicant (029) Okichikari Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (self-motivated) 6,
Specification to be amended: Fraud of Zeto's invention (U1, Explanation A column and brief description of the drawings) Drawing 7, Contents of the amendment As shown in the attached sheet 7 Contents of the amendment 1) Specification, page 2, line 7 Correct ``to change'' to ``to change and improve electrical characteristics.'' 2) On page 2, line 10, ``semiconductor'' is corrected to ``half-height engineering''. 3) Correct the negative ending line ``Ryo no'' to ``1 area''. 4) Page 3, line 11, page 6, line 19, page 6, line 19, page 7, line 3 (
(2 places), each of the 8th and 6th lines is corrected as ``arsenic j gold ``arsenic''. 5) Same 3 negative 19 line r l E cm-2J k [l
Correct it to E 15om-2J. 6) On page 8 of the same page, 6 ministries, ``wotoshi'' is corrected to ``deari''. 7) Giant 18 pages 15 lines [Channel J'(il-r”
"I'm sorry," he corrected. 8) IiffJ1ON line 14 “8...ion, 9...
ion implantation" to "8...As ion implantation, 9...B
"F or BB'z ion implantation".

Claims (1)

[Claims] A gate oxide film and gate polysilicon are sequentially formed in the active region of a semiconductor substrate having an N-well layer and an oxide film in the field region, and the sources and gates of the P-channel transistor and the N-channel transistor are
A step of forming a drain region, a step of implanting impurity ions for forming a source/drain into the active region of the N-channel transistor, and a step of implanting ions into the active region of the N-channel transistor and annealing the N-channel transistor. The step of forming a source/drain impurity layer, and after forming the north drain impurity layer of the N channel transistor, ions are implanted into the active region of the P channel transistor and annealing is performed to form the source/drain impurity layer of the P channel transistor. A method for manufacturing an N-well complementary semiconductor device, comprising the steps of forming a second impurity layer adjacent to the source/drain impurity layer of the N-channel transistor.