JPS6034874B2 - high speed scanning circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed scanning circuit for a color solid-state imaging device.

In a solid-state imaging device (hereinafter referred to as a single-chip color solid-state imaging device) that extracts color signals using a single solid-state bran image element, color outputs corresponding to each of red, green, and blue are
There are things that can be taken out through three busbars.

These two color signals are distributed to three corresponding bus lines and output. Several methods have been proposed for extracting signals from solid-state image sensors.
For example, the charge charges accumulated during one frame period of a television signal are read out to the vertical transfer stage during the vertical blanking period,
There is a method of sequentially transferring one line in the vertical direction during the horizontal blanking period, and reading in the horizontal direction during the horizontal scanning period. At this time, the three color signals of red, green, and blue are distributed to three output buses corresponding to each signal. In this method, when the number of pixels of the solid-state image sensor increases,
Color signals are distributed to three output buses, and the output speed becomes faster as the number of picture elements increases. A shift register is used as a scanning circuit that switches signals transferred in the vertical direction to the horizontal direction and sequentially outputs the signals. In addition to such shift registers for scanning, various types have been devised to meet the required high-speed performance. On the other hand, the color signal transmitted vertically is minute, and the output bus has a large capacity. Therefore, it becomes necessary to drive a large capacitance output bus with a small color signal. One proposal for this purpose is to drive the output bus in advance before reading out the signal to the outside, and then read out the signal when the signal output becomes constant. A timing diagram and a configuration diagram of a signal readout method for this method are shown in sections la and b.

In the figure b, numerals 4, 5, and 6 are vertical signal transfer stages. 7, 8, and 9 are determined by the output signal of the scan register 13.
This is a switch that opens and closes the vertical transfer stages 4, 5, and 6 and the output buses 10, 11, and 12.

The timings of the outputs 14, 15, and 16 of the scanning register 3 are shown at 1, 2, and 3 in FIG. This output 1
4, 15, and 16 are added to switches 7, 8, and 9, respectively, to control them. At timing t, the switch 7 is closed, and the signal from the vertical transfer stage 4 is transmitted to the output bus 12. Similarly, at timings t2 and t3, vertical transfer stage 5,
6 signals are transmitted to each of the output buses 11 and 1 river. At this time, considering the vertical transfer stage 4, the timing at which the switch 7 is closed is t2, et al. If you read it out, you can get a stable signal. Similarly, the signals of the vertical transfer stages 5 and 6 are read out from the output buses 11 and 10 at timings t4 and t5. In such a scheme, the required output of the horizontal scan register 13 is
As shown at 1, 2, and 3 in Figure A, the output is at the "1" level at three timings shifted by one timing. If one timing is one bit, three consecutive bits will output "1".

In a general shift register, for example, the shift register 32 shown in FIG. 2a, the clock lines 20 and 21 have
When the clock signals 27 and 28 shown in FIG.
, 31 are obtained.

In addition, in FIG. 2a, 22 is a power supply line;
4 is a ground line (GND). At this time, the output is 30
, 31 is one period of the clocks 27, 28. This requires a clock that is twice the data rate of the signal, and as the number of picture elements increases, a shift register that operates at extremely high speed must be created. On the other hand, in the scanning register 40 shown in FIGS. 3a and 3b, clock lines 41 and 42 are connected to clocks 48 and 4 shown in FIG.
9 and a start pulse to terminal 44, outputs 51 and 52 can be obtained at terminals 46 and 47.

At this time, the outputs 51 and 52 are shifted by the clocks 48 and 4.
This will be half of the 9th synchronization. This is the same frequency as the data rate of the signal, and is the same as the frequency of the shift register 3 shown in Figure 2a and b.
Compared to 2, the drive frequency is only half. However, the output of this register cannot satisfy the above-mentioned requirement for three consecutive bits to be "1". The present invention was made to satisfy the above-mentioned requirements, and it can be driven at the same driving frequency as the data rate, and can be shifted one bit at a time so that output can be easily obtained even when the number of picture elements increases. This paper proposes a high-speed scanning circuit that can continuously output "1" from the three bits.

The present invention will be described below with reference to embodiments along with drawings.

FIG. 4 shows a circuit configuration diagram of an embodiment of the present invention, and FIG. 5 shows a main signal timing diagram of the embodiment.

Reference numerals 51 and 52 are drive clock lines for the shift register, to which clocks 91 and 92 in FIG. 5 are applied, respectively.

Further, a pulse 93 shown in FIG. 5 is applied to the terminal 54. At this time, the outputs 55, 56, 57, 58 of the shift register 100
In this case, outputs 94, 95, 96, and 97 shown in FIG. 5 are obtained. These outputs 55 and 56, 56 and 57, 57 and 58 are the same. In addition to the bills or gates 63, 64, and 65,
The outputs of Figure 5 are 98, 99, and 59, 60, 61.
Get 100. This is 3 consecutive bits that are "1". As shown in FIG.
Add to 75, 76, 77. At this time, the output bus 67, 6
The states of 8 and 69 correspond to waveforms 101 and 10 in FIG.
It becomes like 2,103. In FIG. 4, reference numerals 78, 79, and 80 are sampling gates for the output buses 69, 68, and 67. In order to perform sampling while the states of the output bus lines 67, 68, 69 are sufficiently stable, sampling is performed at a timing immediately before the output from the solid-state image sensor 86 is switched to the output bus lines 67, 68, 69. Sampling pulse 1 in Figure 5
04, 105, and 106, respectively, to terminals 81 and 82 in FIG.
,83. In FIG. 4, 84 is a video amplifier, and its power is as shown in FIG. 5, 107. Figure 5 9
This frequency is the basic clock of the embodiment of the present invention, and in the conventional method, the shift register had to be driven at this frequency.

However, the high-speed scanning circuit of the present invention can drive the shift register even at half the frequency of the basic clock. As explained above, the high-speed scanning circuit of the present invention uses 3 bits shifted by 1 bit at the same driving frequency as the data rate.
Since it is possible to obtain an output in which the bits become "1" continuously, even if the number of picture elements increases, the output of the image pickup device can be extracted without increasing the driving frequency.

[Brief explanation of the drawing]

Figures 1a and 1b are output take-out timing diagrams and circuit configuration diagrams showing the basics of the output section of a color solid-state imaging device, and Figures 2a and 3a and 3b are respectively diagrams of conventional scanning circuits. Timing diagram and circuit diagram. FIG. 4 is a circuit diagram showing one embodiment of the high speed scanning circuit of the present invention, and FIG. 5 is a timing diagram of the same embodiment. 51, 52... Drive clock supply line of shift register, 55, 56, 57, 58... Output line of shift register, 63, 64, 65, 66...
OR gate, 67, 68, 69... Group image sensor output bus, 74, 75, 76, 77... Changeover switch, 86... Group image sensor, 85...
···amplifier. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1 A shift register that has N output terminals (N is a natural number of 3 or more), whose output is sequentially shifted in half a cycle of a driving clock signal, and outputs a "1" state for one cycle of the clock signal. , N logical sum circuits to which outputs from the adjacent output terminals of the shift register are input;
the (3k-2)-th, (3k-1)-th, and 3k-th (k is a natural number) output terminals of the solid-state image sensor having N output terminals, and having N output terminals; 1. A high-speed scanning circuit, characterized in that the control electrodes are connected to the first, second, and third output buses through N switching elements whose control electrodes are connected to an OR circuit.