JP2689863B2 - Color CCD line sensor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color CCD line sensor, and more particularly to a signal of each color from two CCD shift registers formed along one side of each of two linearly arranged pixel columns. The present invention relates to a color CCD line sensor capable of outputting charges in a dot sequence or a line sequence.

[0002]

2. Description of the Related Art Recently, a CCD line sensor is being colorized in order to obtain a color image.
A color CCD line sensor of 500 to 5000 pixels in which two, two or three are arranged in parallel and red, green, and blue (R, G, B) primary color filters are arranged on each pixel is used. Has been. Especially from 1000 pixels to 200
In a 0-pixel color CCD line sensor, two pixel rows are provided in parallel, one CCD shift register is provided along each pixel row, and the signal charge generated in each pixel is read out to the corresponding CCD shift register. 2 CCs
Color CCD with transfer method by D shift register
Line sensors have been commercialized.

FIG. 5 shows a conventional color CCD line sensor composed of such two pixel columns. In the figure, 11 and 12 are photodiodes (pixels)
Is a pixel array arranged linearly, and these pixel arrays 11
On and 12 are formed color filters of three colors having different spectral transmittances in order to obtain color information. That is, the red filter 21 is arranged on the odd-numbered pixels of the pixel row 11.
However, the green filters 22 are formed on the even-numbered pixels, and the blue filters 23 are formed in a row on the pixel columns 12. Reference numeral 31 denotes a charge transfer gate for a first channel (hereinafter referred to as CH1) provided adjacent to the pixel column 11 for reading out a charge signal generated in the pixel column 11, 32
Is a charge transfer gate for the second channel (hereinafter referred to as CH2) provided adjacent to one side of the other pixel column 12, and 41 and 42 transfer charges from the charge transfer gates 31 and 32 in parallel. And a CCD shift register for CH1 and a CCD shift register for CH2 that transfer these serially.

These two CCD shift registers 41, 4
Reference numeral 2 is for transferring charges in the same direction, and output circuits 71 and 72 for charge / voltage conversion are formed at the tips of the respective charge transfer directions. In the above-mentioned CCD line sensor with two pixel columns, the signal charges photoelectrically converted by the odd-numbered pixel group and the even-numbered pixel group of the pixel column 11 are opened by opening the charge transfer gate 31 for CH1, It is read out to the CCD shift register 41 for use. At the same time, the signal charges photoelectrically converted in the pixel column 12 are read out to the CH2 CCD shift register 42 by opening the CH2 charge transfer gate 32. Then, the two CCD shift registers are driven, the charges transferred to the respective CCD shift registers are transferred to the leading ends of the CCD shift registers in the charge transfer direction, and the output circuits 71 and 72 provided at the leading ends of the CCD shift registers. The signal charge transferred by is converted into a voltage signal and output.

In this color CCD line sensor, CH
From the output circuit 71 for 1 red 1 green 1 red 2 green 2 red 3 green 3 ...
(R1G1R2G2R3G3 ...) signal is obtained, and CH
From the output circuit 72 for 2, blue 1 blue 2 blue 3 ... (B1B2B3
...) signal is obtained. That is, the data output from this color CCD line sensor was neither line sequential nor dot sequential. Thus, the usage pattern of this type of line sensor is line-sequential or dot-sequential.

Next, an image input device (color image scanner) using the above-mentioned color CCD line sensor will be described with reference to FIG. 200 is the color CCD
It is a line sensor, and output circuits 72 and 71 of this sensor
Amplifiers 211 and 212 are respectively connected to
A sample & hold circuit 221 for removing unnecessary noise components from the CCD signal is connected to the output of the amplifier 211, and a sample & hold circuit 222 is connected to the amplifier 212.
223 is connected. This sample and hold circuit 22
R1G1R2 obtained from the amplifier 212 at 2,223
G2R3G3 ... signal to R1R2R3 ... signal and G1G2G
3 ... Separated from the signal.

Sample and hold circuits 221, 222,
A color correction circuit 230 for correcting the color of the captured image is connected to the output of 223. The color correction circuit 230 includes R1R2R3 ... signal trains and G1G2G3.
Of the signal sequence of B1B2B3 ... and R1G1B1
A red / green / blue (R / G / B) changeover switch 240 for connecting to a signal train such as R2G2B2R3G3B3 ... Is connected, and processing at a computer is easy after the R / G / B changeover switch 240. Is connected to an analog-digital conversion circuit 250 for converting an analog signal into a digital signal, and a parallel circuit for converting a plurality of digitized parallel signals into a serial signal convenient for communication is provided at the subsequent stage. -The serial conversion circuit 260 is connected. The parallel-serial conversion circuit 260 is connected via a communication cable to a computer 270 that controls the color scanner, and the brightness data of the image read by the color CCD line sensor is processed by the computer.

Reference numeral 280 is an oscillating circuit for generating a basic clock signal for the image input apparatus, and 290 is an oscillating circuit 28.
Color CCD based on basic clock signal generated at 0
A CCD driving clock signal for driving the line sensor 200, and sample and hold circuits 221, 222,
A control signal for controlling 223 and a changeover switch 240
Is a timing generation circuit that generates a control signal for controlling the. The timing generation circuit 290 is controlled by the computer 270.

In the color image scanner described above, color correction is performed in the color correction circuit 230. This correction is a work of converting color data corresponding to the display color characteristics of the image display device and the ink characteristics of the printing device. However, since the faithful color reproducibility with respect to the hue of the original image cannot be guaranteed without performing this, it is a method that is routinely adopted in the case of performing color printing. In order to perform this color correction, line-sequential color signals are required, but since the conventional image sensor cannot obtain line-sequential data as it is, the sample and hold circuits 222 and 22 are external circuits.
3 is used to convert the two image signals into line-sequential data.

If the image input device is to be constructed at low cost, color correction may be omitted. Next, an image input device (color image scanner) that does not perform color correction using the above color CCD line sensor will be described with reference to FIG. Reference numeral 200 denotes the color CCD line sensor described above. Amplifiers 211 and 212 are connected to the output circuits 71 and 72 of the sensor, respectively, and the outputs of the amplifiers 211 and 212 are R1G1R2G2R3G3 ... The signals B1B2B3 ... Obtained from the amplifier 211 are mixed and R1G1B1R is mixed.
2G2B2R3G3B3 ... A red / green-blue (R / G / B) changeover switch 241 for forming a signal train is connected, and unnecessary noise from the CCD signal is provided at the subsequent stage of the R / G / B changeover switch 241. A sample & hold circuit 220 for removing the component is connected, and a brightness correction circuit 231 for correcting the brightness data of the captured image is connected to the subsequent stage of the sample & hold circuit 220.

The brightness correction circuit 231 is connected to an analog-digital conversion circuit 250 for converting an analog signal into a digital signal so that the processing by a computer is simplified, and a plurality of digitized digital signals are further provided in the subsequent stage. A parallel-serial conversion circuit 260 for converting a parallel signal into a serial signal convenient for communication is connected. The parallel-to-direct conversion circuit 260 is connected via a communication cable to a computer 270 that controls the color scanner, and the brightness data of the image read by the color CCD line sensor is processed by the computer.

Reference numeral 280 is an oscillator circuit for generating a basic clock signal for the image input device, and reference numeral 290 is an oscillator circuit 280.
Timing of generating a CCD driving clock signal for driving the color CCD line sensor 200 and a control signal for controlling the R / G-B changeover switch 241 and the sample & hold circuit 220 based on the basic clock signal generated in It is a generation circuit. Timing generation circuit 29
0 is controlled by the computer 270.

The image input device shown in FIG. 7 requires only dot-sequential data, but the conventional color image sensor cannot directly obtain this data. Therefore, the changeover switch 241 is used to change the color CCD line sensor. Are converted into dot-sequential output. Further, in this image input device, the sample & hold circuit 220 is connected after the changeover switch 241 in order to reduce the number of sample & hold circuits.

[0014]

In the above-mentioned conventional color CCD line sensor, since line-sequential data for performing the color correction necessary for faithful color reproduction cannot be obtained as it is, the color CCD line sensor is external to the color CCD line sensor. sample&
Three hold circuits have been used to perform conversion into a two-output line-sequential read signal. Also, conventional color CCD
When performing color correction using a line sensor, the sample and hold circuit with a relatively low speed shown in FIG.
Since it is necessary to alternately sample the G and B color data, there is a drawback that the R, G, and B brightness data in the sub-scanning direction cannot be read at high speed. Further, in the image input device whose cost is suppressed, dot-sequential reading is required, but since the dot-sequential reading data cannot be obtained as it is in the conventional color CCD line sensor, a changeover switch is used outside the color CCD line sensor. Therefore, the two outputs must be converted into a dot-sequential read signal. As described above, in the conventional image input device, line-sequential reading is required when importance is attached to color reproducibility, and dot-sequential reading is required in order to suppress the price of the image input device. From the user's side, in order to make the image input device compact and inexpensive, it is possible to reduce the number of external circuit parts and switch between line-sequential or dot-sequential line sensor or line-sequential mode or dot-sequential mode There is an increasing demand for line sensors that can be used. However, 2
The current color CCD line sensor using a pixel array of a book cannot meet this demand.

Even at present, one specialized in dot-sequential reading
A color CCD image sensor of a pixel row of three or a color image sensor having three pixel rows specialized for line-sequential reading is provided on the market. Further, even with an image sensor having two pixel columns, it is possible to design an image sensor specialized for any of the reading methods. However, in that case, it is necessary to design and manufacture two types of color CCD line sensors, and it is not possible to meet the user's demand for switching between the two reading methods.

[0016]

In order to solve the above problems, according to the present invention, two color filters (21, 2) out of the three primary color filters of primary color system or complementary color system.
2) arranged in parallel with a first pixel row (11) composed of pixels arranged alternately, and the first pixel row (11) arranged in parallel with the first pixel row.
In addition, the remaining one color filter of the three primary color filters is used.
Is composed of pixels in which a color filter (23) is arranged.
Second pixel row (12) and a first and second CCD shift register (41, which is provided along each pixel row and reads the signal charges of each pixel row in parallel and transfers them in series. 42), a first separation output gate (51) and a first combined input gate (61) provided adjacent to the tip of the first CCD shift register in the charge transfer direction, A second separation output gate (52) and a second composite input gate (62) provided adjacent to the tip end of the second CCD shift register in the charge transfer direction.
And first and second output circuits (71, 71a; 72, 72a) for performing charge / voltage conversion, which are respectively provided at the subsequent stages of the first and second separated output gates, and the first and second output circuits. Two
Third output circuit (80, 90, 70; 8) commonly provided in the subsequent stage of the combined input gate for performing charge / voltage conversion
0, 90, 70a) and a color CCD line sensor is provided.

[0017]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a color CCD line sensor according to a first embodiment of the present invention, and FIG. 2 is a timing diagram of clock pulses applied to respective portions of the line sensor for reading the color CCD line sensor line-sequentially. FIG. 3 is a timing chart of clock pulses applied to each part for reading the color CCD line sensor in a dot-sequential manner.

In FIG. 1, 11 and 12 are pixel columns in which photodiodes (pixels) are linearly arranged,
On these pixel rows 11 and 12, three color filters having different spectral transmittances are formed in order to obtain color information. That is, the red filter 21 is formed on the odd-numbered pixels of the pixel row 11, the green filter 22 is formed on the even-numbered pixels, and the blue filter 23 is formed on the pixel row 12 in one row. 31 is a charge transfer gate for CH1 provided adjacent to the pixel column 11 for reading out a charge signal generated in the pixel column 11, and 32 is provided adjacent to one side of the other pixel column 12. The charge transfer gates for CH2, 41 and 42 are the charge transfer gates 31, 32.
CH that transfers charges in parallel from this and transfers them in series
A CCD shift register for 1 and a CCD shift register for CH2.

These two CCD shift registers 41, 4
Reference numeral 2 is for transferring charges in the same direction, and the separation output gate 5 is provided at the tip of each charge transfer direction.
1 and 52 are formed adjacent to each other, and combined input gates 61 and 62 are formed adjacent to each other. An output circuit 71 for CH1 and an output circuit 72 for CH2 for converting the transferred charge amount into a voltage signal are formed adjacent to the separation output gates 51 and 52,
Further, a charge combining unit 80 is formed in common adjacent to the combined input gates 61 and 62. A combined output gate 90 is formed adjacent to the charge combining unit 80, and a combined output circuit 70 for charge / voltage conversion is formed adjacent to the combined output gate 90.

Next, the line-sequential read operation of this embodiment will be described with reference to FIGS. In this color CCD line sensor, the signal charge photoelectrically converted and accumulated in each pixel of the pixel column 11 is opened by opening the charge transfer gate 31 for CH1 so that the C for CH1 is generated.
The photoelectric conversion charge accumulated in each pixel of the pixel column 12 is read out to the CC for CH2 by reading out to the CD shift register 41 and simultaneously opening the charge transfer gate 32 for CH2.
The data is read out to the D shift register 42. The signal charges read out to the CCD shift register 41 are transferred to the CCD by the shift pulses φ1 and φ2 applied to this shift register.
It is transferred to the tip of the shift register 41. Similarly, CC
The signal charges read to the D shift register 42 are the shift pulses φ3 and φ4 applied to this shift register.
Is transferred to the tip of the CCD shift register 41.

The charges transferred to the tip of the CCD shift register 41 for CH1 are output by the G1 and G3 clock pulses applied to the adjacent separation output gate 51 and combined input gate 61, respectively. Circuit 71
And the charge combining unit 80. That is, when the pulse G1 is H, the output separation gate 51 is opened and the charge corresponding to the brightness of red is injected into the output circuit 71. Further, when the pulse G1 is L, the pulse G3 applied to the combined input gate 61 becomes H, the combined input gate 61 is opened, and charges corresponding to the brightness of green are injected into the charge combining unit 80. The charges injected into the charge combiner 80 are combined output gate 90.
When the pulse G5 applied to is to H, it is injected into the output circuit 70 through this gate.

The signal charges transferred to the tip of the CCD shift register 42 for CH2 are applied to the adjacent separation output gate 52 and composite input gate 62.
It is injected only into the output circuit 71 by the clock pulse of 2, G4. That is, when the pulse G2 is H, the output separation gate 52 is opened and the charge corresponding to the brightness of blue is generated in the output circuit 7.
2 injected. The pulse G4 of the combined input gate 62 is closed. The output circuits 71, 70 and 72 output voltage signals corresponding to the brightness of red, green and blue, respectively, as indicated by Vout1, Vout2 and Vout3. Output circuits 71, 7
0 and 72 are reset pulses RS1 and RS, respectively.
2, RS3 is applied to initialize the output circuit before the signal charge of the next pixel is injected into the output circuit.

Next, the dot-sequential reading operation of the color line sensor of this embodiment will be described with reference to FIGS. The charges photoelectrically converted in the pixel columns 11 and 12 are
It is transferred to the tip of the CCD shift register 41 for CH1 by the shift pulses φ1 and φ2, and to the tip of the CCD shift register 42 for CH2 by the shift pulses φ3 and φ4. Here, the pulses φ1 and φ3 have an opposite phase relationship with each other, and the pulses φ2 and φ4 have an opposite phase relationship with each other. Therefore, the signal charge transferred through the CCD shift register 41 and the signal charge transferred through the CCD shift register 42 are 180 ° out of phase with each other.

Since the pulses G1 and G2 applied to the separation output gates 51 and 52 are always L, the separation output gates 51 and 52 are always closed.
Synthesis input gates 61 and 62 and synthesis output gate 9
Since the pulses G3, G4 and G5 applied to 0 are H, the combined input gate and the combined output gate are always open.

First, when φ1 and φ4 become H and φ2 and φ3 become L, the red signal charge transferred from the CCD shift register 41 passes through the synthesis input gate 61 and the synthesis input unit 8
It is injected into 0, and then into the composite output circuit 70 via the composite output gate 90. Next, when φ1 and φ4 become L and φ2 and φ3 become H, the CCD shift register 4
The blue signal charge transferred from the 2 is the gate 62 for combined input.
Is injected into the synthesis input section 80 via the, and then is injected into the synthesis output circuit 70 via the synthesis output gate 90. Further, when φ1, φ4 are switched to H, φ2, and φ3 are switched to L, the green signal charge transferred from the CCD shift register 41 is injected into the synthesis input section 80 via the synthesis input gate 61, and then the synthesis output is performed. It is injected into the combined output circuit 70 via the gate 90. Then, when φ1 and φ4 become L again and φ2 and φ3 become H again, the CCD shift register 4
The electric charges transferred from No. 2 are injected into the combining input unit 80 via the combining input gate 62, but at this time, since the final wells of the shift register 42 have no charges accumulated, the combining charges are combined. There is no charge injected into the input section 80 or the combined output circuit 70. Thereafter, the same operation is repeated and the dot-sequential output signal indicated by Vout2 is detected by the synthesis output circuit.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the pixel column, the CCD shift register, and the composition / separation are the same as those in the first embodiment of the present invention. Therefore, in FIG. 4, the parts common to those of the first embodiment are shown in FIG. , And the description thereof is omitted, and a combined output circuit 70a and output circuits 71a and 72a different from those in FIG. 1 will be described. As shown in FIG. 4, the output circuit 71a has CH1
Charge storage section 101 formed adjacent to the separate output gate 51 for charge, and a charge detection section 121 formed in the vicinity of the charge storage section 101 (for example, composed of a floating diffusion region)
A barrier gate 111 formed between the charge storage unit 101 and the charge detection unit 121; and the charge detection unit 12
1 and a reset drain region 141 formed in the vicinity of 1,
It comprises a reset gate 131 formed between the charge detector 121 and the reset drain region 141, and a voltage output circuit 151 (for example, a source follower circuit of MOSFET) for detecting the potential of the charge detector 121.

Similarly, the output circuit 72a includes a charge storage section 1 formed adjacent to the separation output gate 52 for CH2.
02, the charge detection unit 122 formed in the vicinity of the charge storage unit 102, the charge storage unit 102 and the charge detection unit 1
22, a barrier gate 112 formed between the charge detection unit 122 and the reset drain region 142, a reset drain region 142 formed near the charge detection unit 122, and a reset gate 132 formed between the charge detection unit 122 and the reset drain region 142.
And a voltage output circuit 152 for detecting the electric potential of the charge detector 122.

The combined output circuit 70a includes a charge storage section 100 formed adjacent to the combined output gate 90,
The charge detection unit 1 formed near the charge storage unit 100
20, a barrier gate 110 formed between the charge storage unit 100 and the charge detection unit 120, and a reset drain region 140 formed near the charge detection unit 120.
And the charge detection unit 120 and the reset drain region 14
It comprises a reset gate 130 formed between 0 and 0, and a voltage output circuit 150 for detecting the potential of the charge detection unit 120.

In the first embodiment shown in FIG. 1, the output circuits 70, 71 and 72 are all the same circuit, but in the output circuits 70a, 71a and 72a of this embodiment shown in FIG. The detectors 120, 121, 122 are formed so that their capacities are different. For example, in order to make the sensitivities of the red, green, and blue sensors equal, the charge detection units 120, 12
The capacitances of 1 and 122 are set to the reciprocal of the sensitivity ratio of the red, green and blue sensors. For example, when the sensitivity ratio of red, green, and blue is G: R: B = 2: 2: 1, the capacitance of the charge detection units 120, 121, 122 is C
If G: CR: CB, then CG: CR: CB = 1: 1: 2, and the sensitivity of red, green, and blue is made equal overall.

While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various changes can be made within the gist of the present invention described in the claims. For example, in the embodiment, the blue filter 23 is formed on the pixel column 12, but instead of the blue filter, a red filter or a green filter is used for the pixel column 1.
2 can be placed on top. Further, in the dot-sequential read operation shown in FIG. 3, G3 and G4, which are always H, can be made into pulses synchronized with the shift pulses φ1 to φ4. Furthermore, the charge combining unit 80 and the combined output gate 9
By omitting 0, the charges of the CCD shift registers 41 and 42 are directly combined and output via the combined input gates 70 and 70.
It can be made to flow into a.

[0031]

As described above, the color CCD of the present invention.
According to the line sensor, two types of reading, that is, line-sequential reading and dot-sequential reading, can be performed by changing the driving method with one color CCD line sensor. Therefore, it is possible for the manufacturer to meet the requirements of both applications by preparing only one device, and it is possible to reduce the number of design and manufacturing processes. Also, on the user side, one color CCD line sensor can be used. Thus, line-sequential reading can be performed to manufacture an image input device with good color reproducibility, and dot-sequential reading can be performed to reduce the price of the image input device. Further, in the image input device, unnecessary peripheral circuits, that is, a sample & hold circuit for separating the color signals of three colors, a switch circuit for synthesizing the color signals of three colors, etc. can be deleted, and the device can be made compact and low cost. Can contribute. In addition, the use of low-speed sample-and-hold circuits can be eliminated,
High-speed color correction is possible.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of clock pulses for driving line-sequential reading according to the first embodiment of the present invention.

FIG. 3 is a timing diagram of clock pulses for driving the first embodiment of the present invention by dot sequential reading.

FIG. 4 is a schematic configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a conventional example.

FIG. 6 is a block diagram of a line-sequential read-out type image input device using a conventional example.

FIG. 7 is a block diagram of an image input device of a dot-sequential reading system using a conventional example.

[Explanation of symbols]

11, 12 Pixel column 21 Red filter 22 Green filter 23 Blue filter 31, 32 Charge transfer gate 41, 42 CCD shift register 51, 52 Separate output gate 61, 62 Combined input gate 70, 70a Combined output circuit 71, 71a, 72, 72a Output circuit 80 Charge combiner 90 Combined output gate 100, 101, 102 Charge accumulator 110, 111, 112 Barrier gate 120, 121, 122 Charge detector 130, 131, 132 Reset gate 140, 141, 142 Reset Drain 150, 151, 152 Voltage output circuit 200 Color CCD line sensor 211, 212 Amplifier 220, 221, 222, 223 Sample & hold circuit 230 Color correction circuit 231 Lightness correction circuit 240 R / G / B changeover switch 24 R · G-B changeover switch 250 analog - digital converter 260 parallel - serial converter 270 Computer 280 oscillation circuit 290 timing circuit

Claims (5)

(57) [Claims] 1. A first pixel column constituted by pixels in which color filters of two colors among color filters of three primary colors of primary colors or complementary colors are alternately arranged ; The three primary color covers are arranged in parallel to the pixel rows.
The remaining one color filter of the color filters is arranged
A second pixel column constituted by divided pixels, and first and second CCD shift registers which are provided along the respective pixel columns and which read the signal charges of the respective pixel columns in parallel and transfer them in series. A first separation output gate and a first composite input gate provided adjacent to the tip of the first CCD shift register in the charge transfer direction; and a charge transfer direction of the second CCD shift register. A second separated output gate and a second combined input gate that are provided adjacent to the tip of each of the first and second separated output gates. A color CCD line sensor comprising: a first and a second output circuit for performing; and a third output circuit for performing charge / voltage conversion, which is provided in common after the first and second combined input gates. 2. The third output circuit comprises a charge combining unit provided adjacent to the first and second combined input gates, and a combined output gate provided adjacent to the charge combiner. When,
The color CCD line sensor according to claim 1, further comprising a combined output circuit for performing charge / voltage conversion, which is provided at a stage subsequent to the combined output gate. 3. The first separated output gate and the first separated output gate
2. The color CCD line sensor according to claim 1, wherein said composite input gate is repeatedly opened and closed at regular intervals, and said second composite input gate is always closed. 4. The first separation output gate and the second separation output gate are always closed, and the first combined input gate and the second combined input gate are always open. The color CCD line sensor according to claim 1, wherein 5. The first, second and third output circuits each have a diffusion layer for charge / voltage conversion,
2. The color CCD line sensor according to claim 1, wherein one of the diffusion layers has an area different from that of the other diffusion layers, or each diffusion layer has an area different from each other.