JPS6034051A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6034051A JPS6034051A JP14335883A JP14335883A JPS6034051A JP S6034051 A JPS6034051 A JP S6034051A JP 14335883 A JP14335883 A JP 14335883A JP 14335883 A JP14335883 A JP 14335883A JP S6034051 A JPS6034051 A JP S6034051A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- input terminal
- surge
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は耐サージ保護回路を有する半導体集積回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a semiconductor integrated circuit having an anti-surge protection circuit.
半導体集積回路（以下、ＩＣという。）の普及とともに
、ＩＣの取扱い中に外部の帯電体１例えば搬送用キャリ
アや人体に触れる事によりＩｃのによるｌＣの破壊が問
題となり、近年のＩＣには種々の耐サージ保護回路が施
されている。With the spread of semiconductor integrated circuits (hereinafter referred to as ICs), destruction of ICs due to ICs due to contact with external charged objects 1, such as transportation carriers or human bodies, during handling of ICs has become a problem. Equipped with anti-surge protection circuit.
一方、ＩＣの発展は目覚ましいものがあり、高密度化と
ともに高速化が進み、Ｉｃの高速スイッチング動作時に
、このＩＣの端子容量の与える影響も大きくなってきて
いる。On the other hand, the development of ICs has been remarkable, with higher densities and higher speeds, and the influence of the terminal capacitance of ICs on high-speed switching operations of ICs has also become greater.
第１図（ａｔは、耐サージ保護回路を有する従来のＩｃ
の一例を示す回路図である。Figure 1 (at is a conventional IC with anti-surge protection circuit)
It is a circuit diagram showing an example.
ＩＣＩは、内部回路２と、入力端子３と電源端子４間に
入力端子を陽極側として接続されたダイオードＤ１と、
入力端子３と接地端子５間に入力端子を陰極側として接
地されたダイオードＤ２を含んで構成される。このＩＣ
１ではダイオードＤ、 、 Ｄ。The ICI includes an internal circuit 2, a diode D1 connected between an input terminal 3 and a power supply terminal 4 with the input terminal on the anode side,
The device includes a diode D2 which is connected between the input terminal 3 and the ground terminal 5 with the input terminal being on the cathode side. This IC
In 1, diodes D, , D.
が保護ダイオードとして動作して、ＩＣに加わった静電
気等のサージを電源端子または接地端子に逃がすもので
ある。acts as a protection diode, allowing surges such as static electricity applied to the IC to escape to the power supply terminal or ground terminal.
第１図ｆａｔはまた、高周波成分に注目すると第１図ｆ
ｂ）の様に現わす事ができる。第１図（ｂｌにおいて。If we pay attention to the high frequency components, Figure 1 fat can also be seen as Figure 1 f.
It can be expressed as b). Figure 1 (in bl.
Ｃ，、Ｃ２は第１図（ａｌに示されるダイ、ｔ −トＤ
、、Ｄ、 〕るインダクタンスである。C, , C2 are the dies shown in FIG.
, ,D, ] is the inductance.
かかる耐サージ保護回路を有するＩｃ１が、高速スイッ
チング動作をすると＠、その人力に印加される立上りの
急峻な入力パルス信号により、パルス電流Δ１１．△１
２が生じ、電源Ｖｃｃ及び接地配線のインダクタンスＬ
、、Ｌ、により誘起サレ７’ｖ ’／ノイズ発生し、Ｉ
ｃＩの内部回路２の誤動作を誘発する。この種類の寄生
容量によるノイズの発生を防ぐため、ＩＣの設計におい
て種々の工夫をしなければならないが、耐サージ保巡回
路に用いているダイオードＤ、、Ｄ２は、その接合面積
を小さくすると、サージ破壊防止の効果がなくなる。一
方、このダイオードＤｓ 、 Ｄｔ （’） Ｗ生８ｆ
ｊｋＣ，Ｃｔ Ｉ′ｉ、 １１／ｆ接合面積に比例して
大きくなるが、所定のサージ破壊防止効果を得るために
はむやみにダイオード病＋ ＩＪ２の接合面積を小さく
できず、寄性容量ｃ、。When Ic1 having such anti-surge protection circuit performs high-speed switching operation, the pulse current Δ11. △1
2 occurs, and the inductance L of the power supply Vcc and ground wiring
, , L causes induced vibration 7'v'/noise, and I
This causes malfunction of the internal circuit 2 of cI. In order to prevent the generation of noise due to this type of parasitic capacitance, various measures must be taken in IC design. The effect of preventing surge damage is lost. On the other hand, this diode Ds, Dt (') W raw 8f
jkC, Ct I'i, 11/f increases in proportion to the junction area, but in order to obtain the desired surge damage prevention effect, the junction area of diode disease + IJ2 cannot be reduced unnecessarily, and the parasitic capacitance c, .
Ｃ７によるノイズ発生を防ぐ上で、この耐サージ保護回
路が障害になるという欠点が生じる。This anti-surge protection circuit has the drawback of becoming an obstacle in preventing noise generation due to C7.
本発明の目的は、上記の欠点を除去することによ勺、サ
ージ破壊防止の効果を損なうことなく。The object of the present invention is to eliminate the above-mentioned drawbacks without impairing the effect of preventing surge damage.
かつ寄生容量によるノイズの発生を防ぐことのできる耐
サージ保護回路を有する半導体集積回路を提供すること
にある。Another object of the present invention is to provide a semiconductor integrated circuit having an anti-surge protection circuit capable of preventing the generation of noise due to parasitic capacitance.
本発明の半導体集積回路は、入力端子と電源端子間及び
入力端子と接地端子間のいずれか一方又は両方に、直列
抵抗を介して接続された耐サージ保護回路を有すること
から構成される。The semiconductor integrated circuit of the present invention includes an anti-surge protection circuit connected to either or both of the input terminal and the power supply terminal and the input terminal and the ground terminal via a series resistor.
「実施例の説明〕
以下１本発明の実施例について図面を参照して説明する
。“Description of Embodiments” An embodiment of the present invention will be described below with reference to the drawings.
第２図は本発明の一実施例の回路図である。FIG. 2 is a circuit diagram of one embodiment of the present invention.
本発明の一実施例のＩｃＩ １ば、入力端子３と電源端
子４間及び入力端子３と接地端子５間の両方に、直列抵
抗風、へを介してそれぞれ接続されたダイオードＤ、、
Ｄ、からなる耐サージ保護回路を有することから構成さ
れる。IcI of one embodiment of the present invention 1. Diodes D are connected both between the input terminal 3 and the power supply terminal 4 and between the input terminal 3 and the ground terminal 5 through series resistors, respectively.
It is constructed by having an anti-surge protection circuit consisting of D.
なお本実施例が第１図に示した従来例と異なる点は、ダ
イオードＤ、 、 Ｄ、に直列に抵抗域、Ｒ，が挿入さ
れている点である。The present embodiment differs from the conventional example shown in FIG. 1 in that a resistance region R is inserted in series with the diodes D, , D,.
従って、本実施例によれば、入力に急峻な立上りや立下
りの入力パルス信号が入った場合−ｃＡＣ１鴇（Ｃｒ、
ＣｔはダイオードＤ、 、 Ｄ２の寄生容量。）の時定
数を入力パルスの立上りや立下り時間より十分大きくす
れば、入力端子３よシミ原端子４又は接地端子５に流れ
る電流を制限する事ができ。Therefore, according to this embodiment, when an input pulse signal with a steep rise or fall is input, -cAC1 (Cr,
Ct is the parasitic capacitance of diodes D, D2. ) by making the time constant sufficiently larger than the rise and fall times of the input pulse, it is possible to limit the current flowing from the input terminal 3 to the stain source terminal 4 or the ground terminal 5.
ノイズ電圧の発生を抑える事ができる。It is possible to suppress the generation of noise voltage.
一方、静電気等のサージ電圧の時定数は、入力パルス信
号の時定数より非常にゆっくりであるので＝ Ｃ＋ｌ（
ｗやＣ，Ｒ２の時定数をこのサージ電圧の時定数よシ小
さくすれば、静電気等のサージ電圧は耐サージ保護回路
内部で吸収されＩＣの内部回路２へ影響を与えない。On the other hand, the time constant of surge voltage such as static electricity is much slower than the time constant of the input pulse signal, so = C + l (
If the time constants of w, C, and R2 are made smaller than the time constant of this surge voltage, surge voltages such as static electricity are absorbed inside the anti-surge protection circuit and do not affect the internal circuit 2 of the IC.
第３図は本発明の他の実施例を示す回路図である。FIG. 3 is a circuit diagram showing another embodiment of the present invention.
本実施例は、 １０１３／ の入力端子３と接地端子５
間に、挿入されたエミッタが接地端子５に接続され、ベ
ースが抵抗■−を介してエミッタに接続さ直列に抵抗曳
を接続したものである。本実施例においても、抵抗域と
トランジスタＱ、の寄生容量Ｃ３と抵抗域とで決まる時
定数の値を、入力信号パルスの立上りや立下り時間よシ
は十分に大きく、かつサージ電圧の時定数よシ小さくと
ることにより、サージ電圧印加による破壊からＩＣを保
護すると共に、寄生容量によるノイズ発生を抑止する。In this embodiment, input terminal 3 and ground terminal 5 of 1013/
In between, the inserted emitter is connected to the ground terminal 5, and the base is connected to the emitter via a resistor (-), which is connected in series with a resistor. In this embodiment as well, the value of the time constant determined by the resistance region, the parasitic capacitance C3 of the transistor Q, and the resistance region is set so that the rise and fall times of the input signal pulse are sufficiently large and the time constant of the surge voltage is By keeping it small, the IC is protected from destruction due to the application of a surge voltage, and noise generation due to parasitic capacitance is suppressed.
なお１本発明は１以上説明してきた保護回路に限定され
ないで、他の保護回路の場合にも１本発明が適用される
ことは言うまでもない。Note that the present invention is not limited to the protection circuits described above, and it goes without saying that the present invention can be applied to other protection circuits as well.
以上、詳細に説明したとおｐ１本発明によれば、本発明
のＩＣは直列抵抗を介して接続された耐サージ保護回路
を有しているので、耐サージ性能を低下させることなく
、耐サージ保護回路の寄生容量に基因するノイズの発生
を抑制できると言う効果耘得られる。As explained in detail above, according to the present invention, since the IC of the present invention has an anti-surge protection circuit connected through a series resistor, anti-surge protection can be achieved without deteriorating the anti-surge performance. The effect of suppressing noise caused by parasitic capacitance of the circuit can be obtained.
回路図、第１図（ｂ）は第１図（ａｌの回路の高周波動
作を説明するため等価回路図、第２図は本発明の一実施
例を示す回路図、第３図は本発明の他の実施例を示す回
路図である。
ｌ・・・・半導体集積回路、２・・・・・・内部回路、
３・・・・・入力端子、４・・・・・電源端子、５・・
・・・・接地端子。
１１．１１’・・・・・半導体集積回路、Ｄ、、Ｄ、・
・・・・・ダイオード、１％、Ｒｔ、Ｒｚ、Ｒ４・・・
・抵抗Ｔｈ Ｑ＋・・・・トランジス、［２
りｓ ＣＩ＋Ｃ１＋ＣＢ ・・・・・・寄生容ｉ、Ｌ、
・・・・・インダクタンス、ΔｉＩ、Δｉ！・・・・パ
ルス電流。
（み）
（ｂ）
第２図
ｔｔ’
［The circuit diagram, FIG. 1(b) is an equivalent circuit diagram to explain the high frequency operation of the circuit in FIG. 1(al), FIG. 2 is a circuit diagram showing one embodiment of the present invention, and FIG. It is a circuit diagram showing another example. 1... Semiconductor integrated circuit, 2... Internal circuit,
3...Input terminal, 4...Power terminal, 5...
...Grounding terminal. 11.11'...Semiconductor integrated circuit, D,,D,...
...Diode, 1%, Rt, Rz, R4...
・Resistance Th Q+...transistor, [2 ris CI+C1+CB...parasitic capacitance i, L,
...Inductance, ΔiI, Δi! ...Pulse current. (mi) (b) Figure 2 tt' [
Claims (1)
れか一方又は両方に、直列抵抗を介して接続された耐サ
ージ保護回路を有することを特徴とする半導体集積回路
。1. A semiconductor integrated circuit comprising an anti-surge protection circuit connected via a series resistor between an input terminal and a power supply terminal, or between an input terminal and a ground terminal, or both.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14335883A JPS6034051A (en) | 1983-08-05 | 1983-08-05 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14335883A JPS6034051A (en) | 1983-08-05 | 1983-08-05 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6034051A true JPS6034051A (en) | 1985-02-21 |
Family
ID=15336925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14335883A Pending JPS6034051A (en) | 1983-08-05 | 1983-08-05 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6034051A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02268460A (en) * | 1989-04-10 | 1990-11-02 | Matsushita Electric Ind Co Ltd | Electrostatic breakdown preventing circuit |
| JPH0327566A (en) * | 1989-03-15 | 1991-02-05 | Matsushita Electric Ind Co Ltd | Surge protecting device |
| US5015200A (en) * | 1990-02-20 | 1991-05-14 | Amp Incorporated | Connector with double acting latch |
| KR100504427B1 (en) * | 1997-12-30 | 2005-10-19 | 주식회사 하이닉스반도체 | Noise Clamping Circuit of Semiconductor Device |
| WO2014058737A1 (en) * | 2012-10-12 | 2014-04-17 | Google Inc. | Crystal oscillator with electrostatic discharge (esd) compliant drive level limiter |
-
1983
- 1983-08-05 JP JP14335883A patent/JPS6034051A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0327566A (en) * | 1989-03-15 | 1991-02-05 | Matsushita Electric Ind Co Ltd | Surge protecting device |
| JPH02268460A (en) * | 1989-04-10 | 1990-11-02 | Matsushita Electric Ind Co Ltd | Electrostatic breakdown preventing circuit |
| US5015200A (en) * | 1990-02-20 | 1991-05-14 | Amp Incorporated | Connector with double acting latch |
| KR100504427B1 (en) * | 1997-12-30 | 2005-10-19 | 주식회사 하이닉스반도체 | Noise Clamping Circuit of Semiconductor Device |
| WO2014058737A1 (en) * | 2012-10-12 | 2014-04-17 | Google Inc. | Crystal oscillator with electrostatic discharge (esd) compliant drive level limiter |
| US8854147B2 (en) | 2012-10-12 | 2014-10-07 | Google Inc. | Crystal oscillator with electrostatic discharge (ESD) compliant drive level limiter |
| CN104854697A (en) * | 2012-10-12 | 2015-08-19 | 谷歌股份有限公司 | Crystal oscillator with electrostatic discharge (esd) compliant drive level limiter |
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