JPS6032419A - Power amplifier - Google Patents
Power amplifierInfo
- Publication number
- JPS6032419A JPS6032419A JP58140834A JP14083483A JPS6032419A JP S6032419 A JPS6032419 A JP S6032419A JP 58140834 A JP58140834 A JP 58140834A JP 14083483 A JP14083483 A JP 14083483A JP S6032419 A JPS6032419 A JP S6032419A
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- Prior art keywords
- amp2
- signal
- output
- amp1
- negative feedback
- Prior art date
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Abstract
Description
【発明の詳細な説明】
本発明は、特に一対の電力増幅器を用いて一つの負荷に
出力を供給する電力増幅装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a power amplifier device that uses a pair of power amplifiers to supply an output to one load.
一般に出カドランスレス方式の直接結合電力増幅器を一
対用いて一つの負荷に出力を供給する構成の回路をBT
、L(バランスド・トランスフォーマレス(BALA、
NCED 、 ’lAN8FORME)tLE8s )
)回路といい、第1図、第2図にその従来例を示す。Generally, a BT circuit is a circuit configured to supply an output to one load using a pair of direct-coupled power amplifiers with no output voltage.
, L (balanced transformerless (BALA,
NCED,'lAN8FORME)tLE8s)
) circuit, and conventional examples thereof are shown in FIGS. 1 and 2.
第1図において、AMPlけ同相のf+帰pp1f4力
増幅器、AMP2は逆相の負帰還電力増幅器、Rgl
+lLg2 およびR1−R5は抵抗、KLけ弁狗(ス
ピーカ)、C1〜C4はコンデンサ、1け入力端子、v
CCはW、圧源そして8Gは信号発生器を示している。In Fig. 1, AMP1 is an in-phase f+feedback pp1f4 power amplifier, AMP2 is an anti-phase negative feedback power amplifier, and Rgl
+lLg2 and R1-R5 are resistors, KL valve dog (speaker), C1 to C4 are capacitors, 1 input terminal, v
CC indicates W, a pressure source, and 8G indicates a signal generator.
第1図でAMPlへの入力係号は直接信号治8(Jから
供給され、AMP2の入力信号はAA+P1の出力信号
を抵抗)15 、 R6の抵抗分割を介して供給されて
いる。ここで、AMPlの出力信号は、信号源8Gから
の基本信号とAMPIで発生した歪成分との合成信号と
して出力され、AMP2の出力信号は、信号源8Gから
の基本信号とAMl’l 、 2各々で発生した歪成分
との合成信号として出力される。In FIG. 1, the input coefficient to AMPl is directly supplied through a signal generator 8 (supplied from J, the input signal of AMP2 is the output signal of AA+P1 through a resistor) 15, and a resistor divider R6. Here, the output signal of AMPl is output as a composite signal of the fundamental signal from the signal source 8G and the distortion component generated by AMPI, and the output signal of AMP2 is a composite signal of the fundamental signal from the signal source 8G and AMl'l, 2 It is output as a composite signal with the distortion components generated in each.
このためAMP2の出力信号での歪率は、AΔ4P1の
各々出力信号相互間での歪率のアンバランスと言う不具
合が生じる。次に入力端子1から回路内部を見た入力イ
ンピーダンスZip、 (1)式で示さ!する。For this reason, the distortion rate of the output signal of AMP2 causes a problem that the distortion rate is unbalanced between the respective output signals of AΔ4P1. Next, the input impedance Zip when looking inside the circuit from input terminal 1 is shown by equation (1)! do.
と々る。ことで、ZioはAMPIの入力インピーダン
ス、πは円周率、fは周波数を示し、■モは(2)式%
式%
(2)式において、C5は抵抗rtB 、 R9、几1
0の交点の交流信号バイパス用コンデンサで1)、(2
)式右辺の第1項
は第2項(几10)に比らべて充分小さい為、(2)式
の几はJOの抵抗値で設定される。さらに、(1)式に
おいてZioは同相負帰還電力増幅器AMPIの入力イ
ンピーダンスであるため、Rに比らべて充分大きい。こ
の結果、0)式に示されるZi はほぼRの抵抗値、す
なわち、抵抗RIOの抵抗値で設定できる。具体的に述
べるとR8=10にΩ、 R9=10kn、C3=47
4F、f=1kHz、R1o=50kO,およびZi
o =5MOトすルト、R=50.0003X103中
50X103中RIOと71、Zi =49.5 X
103103=となる。Totoru. Therefore, Zio is the input impedance of AMPI, π is pi, f is the frequency, and ■mo is the formula (2) %
Formula % In formula (2), C5 is resistance rtB, R9, 几1
1), (2) with the AC signal bypass capacitor at the intersection of 0
Since the first term on the right side of the equation (2) is sufficiently smaller than the second term (10), the value of the equation (2) is set by the resistance value of JO. Furthermore, in equation (1), Zio is the input impedance of the common-mode negative feedback power amplifier AMPI, so it is sufficiently larger than R. As a result, Zi shown in equation 0) can be set approximately at the resistance value of R, that is, the resistance value of the resistor RIO. To be specific, R8=10Ω, R9=10kn, C3=47
4F, f=1kHz, R1o=50kO, and Zi
o = 5MO tort, R = 50.0003X103 in 50X103 in RIO and 71, Zi =49.5X
103103=.
次に第2図に他の従来例を示す。第2図においてAMP
Iは同期の負帰還N1力増幅器、AMP2は逆相の負帰
還電力増幅器、Rg、R1−R9は抵抗、几り杜負荷(
スピーカ)、C1〜C5コンデンザ、1は入力端子、V
CCは電圧源、そしてSGは信号発生器を示している。Next, FIG. 2 shows another conventional example. In Figure 2, AMP
I is a synchronous negative feedback N1 power amplifier, AMP2 is an anti-phase negative feedback power amplifier, Rg, R1-R9 are resistors, and the load (
speaker), C1 to C5 capacitor, 1 is input terminal, V
CC indicates a voltage source, and SG indicates a signal generator.
第2図においてAMPI 、AMP2の入力信号は直接
SGから供給される為、AMPl、AMP2の各々の出
力信号は8Gからの基本信号とAMP l 、 AMP
2各々で発生した歪成分との合成信号で出力される。In Fig. 2, the input signals of AMPI and AMP2 are directly supplied from SG, so the output signals of each of AMPI and AMP2 are the basic signal from 8G and AMPl, AMP.
A composite signal of the distortion components generated in each of the two is output.
ここで、AMPl、AMP2を同一回路で構成した場合
、AMPI、AMP2各々で発生した歪成分はほぼ同等
である。よってAMPI。Here, when AMP1 and AMP2 are configured with the same circuit, the distortion components generated in each of AMPI and AMP2 are approximately the same. Therefore, AMPI.
AMP2各々出力信号相互間での歪率のアンバランスと
いう不具合点は生じない。次に入力端子1から回路内部
を見た入力インピーダンスZi1は(3)式%式%
(3)式におけるRは(4)式で示さ第1る。There is no problem of distortion rate imbalance between the output signals of the AMP2. Next, the input impedance Zi1 when looking inside the circuit from the input terminal 1 is expressed by equation (3).R in equation (3) is expressed by equation (4).
ここでZioは同相の狛帰還”電力増幅部、AMP1の
入力インピーダンス、πは円周率、fは周波数を示す。Here, Zio is the input impedance of the in-phase Koma feedback power amplification section and AMP1, π is pi, and f is the frequency.
ただし入力端子1から逆相の狗帰還重、力増幅器AMP
2を見たインピーダンスは、AMP2が逆相に小さい為
、入力端子1からAMP2を見たインピーダンスけR3
七なる。よって、(3)式が導出される。However, from the input terminal 1, there is a reverse phase dog feedback weight, and the force amplifier AMP
The impedance when looking at AMP2 is small because AMP2 is in reverse phase, so the impedance when looking at AMP2 from input terminal 1 is equal to R3
Seven. Therefore, equation (3) is derived.
(4)式の右辺は(2)式右辺と同等であるだめ、第1
図で説明した様にR中RIOとなる。(3)式において
、Zioは同相の負帰還電力増幅器AMP1の入力イン
ピーダンスであるため、R(中JO)、143に比らべ
て充分に大きい。よって(3)式に示されるZi′はR
(中R10)とR3の並列抵抗値で設定されるが、R3
の抵抗値は一般的に数百Ω〜数にΩの抵抗となる為、入
力端子1から見た入力インピーダンスZixは几3の抵
抗値が支配的となシ、第1し1の入力インピーダンスZ
i (具体例で言うと50にΩ)と比らべで、入力イン
ピーダンスZix(具体例で言うと21′、Ω)@下と
いう不具合点が生じる。共体的に述べるとIも8=10
にΩ、■も9=10にΩ、■+、10=50にΩ、C3
=47μF、 f=1kHz、R3=21cO,Zi。The right-hand side of equation (4) is equivalent to the right-hand side of equation (2), so the first
As explained in the figure, it becomes RIO during R. In equation (3), Zio is the input impedance of the in-phase negative feedback power amplifier AMP1, so it is sufficiently larger than R (middle JO), 143. Therefore, Zi' shown in formula (3) is R
(middle R10) and R3 are set by the parallel resistance value, but R3
Generally, the resistance value is from several hundred ohms to several ohms, so the input impedance Zix seen from input terminal 1 is dominated by the resistance value of 几3, and the first input impedance Z
There is a problem that the input impedance Zix (in a specific example, 21', Ω) is lower than Zix (in a specific example, 50Ω). Speaking communally, I is also 8=10
to Ω, ■ also 9=10 to Ω, ■+, 10=50 to Ω, C3
=47μF, f=1kHz, R3=21cO, Zi.
==5MΩとするとH−50,0003X103=R1
0、Zi’=1.92X103中R3となる。If ==5MΩ, H-50,0003X103=R1
0, Zi'=1.92X103, which becomes R3.
そこで、抵抗l′L3の抵抗値を大きくず扛ばよいと思
うかもしれないか、抵抗R3の抵抗値以下の理由で数げ
Ω〜数にΩに設定されている。すなわち、逆相の負帰還
′11i力増幅器AMP2の11fI電圧利得Ayは、
開孔′圧利得が充分大きければ、一般的にAv =R4
/I(,3で設定される。しだがって閾電圧利得が決ま
ってしまえば、11.3の抵抗値を大きくすれば必然的
にI(4の抵抗値を大きくしなければ々らない。さらに
、抵抗R7の抵抗値も同等に大きくしなければならない
。何故ガらば、抵抗R7はAMP2のe、e入力端子の
直流バイアス電圧一定化の為に一般的に抵抗R4のIh
抗値と同一値に設定されているからである。このように
、AMP2に接続されている抵抗R4、R,7の抵抗値
が大きくなれば、AMPlに接続されCいる抵抗1′L
2.JOの抵抗値とのアンバランスによ!J 、AMP
l、AMP2のの入力端子での直流バイアス重圧の相違
が生じ、このためにAMPl、AMP2の出力端子間に
直流電圧差が生じる。この結果負荷R,L(スピーカ)
に直流電流が流れ、負荷(スピーカ)の焼損等の不具合
が生じる。又、集積回路化した場合、抵抗値の大巾増大
によるペレット面積増大によシ、コストアップ等の不具
合点が生じる。しだがって抵抗R3の抵抗値は上述のご
とく、一般的に数百Ω〜数にΩに設定されている。Therefore, one might think that the resistance value of the resistor l'L3 should not be increased, but it is set to several Ω to several Ω because the resistance value is less than the resistance value of the resistor R3. In other words, the 11fI voltage gain Ay of the negative feedback '11i force amplifier AMP2 of opposite phase is:
If the aperture pressure gain is large enough, generally Av = R4
/I(, 3. Therefore, once the threshold voltage gain is determined, if you increase the resistance value of 11.3, you will inevitably have to increase the resistance value of I(4). .Furthermore, the resistance value of resistor R7 must be made equally large.The reason is that resistor R7 is generally used as Ih of resistor R4 in order to stabilize the DC bias voltage of the e and e input terminals of AMP2.
This is because it is set to the same value as the resistance value. In this way, if the resistance values of the resistors R4, R, and 7 connected to AMP2 increase, the resistance value of the resistor 1'L connected to AMP1 increases.
2. Due to imbalance with JO resistance value! J, A.M.P.
There is a difference in DC bias pressure at the input terminals of AMP1 and AMP2, which causes a DC voltage difference between the output terminals of AMP1 and AMP2. As a result, loads R, L (speaker)
DC current flows through the device, causing problems such as burnout of the load (speaker). In addition, when integrated circuits are formed, disadvantages such as increase in pellet area due to a large increase in resistance value and cost increase occur. Therefore, as described above, the resistance value of the resistor R3 is generally set to several hundred ohms to several ohms.
以上のように、従来例である第1図においては覧
AMPl、AMP2各々出カイi号相互間でのφ率のア
ンバランスが生じ、第2回においては入力インピーダン
スの低下という不具合点が生じてし−まう。As described above, in the conventional example shown in FIG. 1, there is an imbalance in the φ ratio between the outputs of AMP1 and AMP2, and in the second case, the problem of a decrease in input impedance occurs. Shi-mau.
本発明の目的は歪率のアンバランスおよび入力インピー
ダンスの低下を防止したB、T、L4%成回路の電力増
幅器を提供するものである。SUMMARY OF THE INVENTION An object of the present invention is to provide a power amplifier with a 4% B, T, and L circuit, which prevents unbalance of distortion and decrease of input impedance.
本発明は、入力信号を並列負帰還型増幅器を介して一対
の増幅器に供給することを特徴とする。The present invention is characterized in that an input signal is supplied to a pair of amplifiers via parallel negative feedback type amplifiers.
第3図に本発明の一実施例を示す。第3ト1において、
AMPIは同相の負帰還電力増幅器、AMP2は逆相の
負帰還電力増幅器、Aは並列負帰還増幅器、C1〜C4
はトランジスタ、kLg、1も1−JLti は抵抗、
RLけ負荷(スピーカ)、01〜C5はコンデンサ、v
CCは電圧源、1拉入力端子、2は並列負帰還増幅器A
の出力端子、SGは信号発生器、そしてIs、12は定
電流源を示す。信号源SGから供給された入力信号は、
並列負帰還増幅器Aを介してその出力端子2に出力され
、同時にAMPl。FIG. 3 shows an embodiment of the present invention. In the third part 1,
AMPI is an in-phase negative feedback power amplifier, AMP2 is an anti-phase negative feedback power amplifier, A is a parallel negative feedback amplifier, C1 to C4.
is a transistor, kLg, 1 is also 1-JLti is a resistor,
RL load (speaker), 01 to C5 are capacitors, v
CC is a voltage source, 1 is an input terminal, 2 is a parallel negative feedback amplifier A
SG is a signal generator, and Is, 12 is a constant current source. The input signal supplied from the signal source SG is
is outputted to its output terminal 2 via the parallel negative feedback amplifier A, and at the same time, AMP1.
AMP2の入力端子に印加される。故に、AMPl。Applied to the input terminal of AMP2. Therefore, AMPl.
AMP2の入力端子に印加される。故に、AMPI。Applied to the input terminal of AMP2. Therefore, AMPI.
AMP2各々の出力信号は、信号源SGからの卑:本信
号と並列負帰還増幅器Aで発生した歪成分とAMPl、
AMP2各々で発生した歪成分との合成信号で出力され
る。すなわち、AMPIの出力信号け、信号源SGの基
本信号と並列負帰還増幅器Aで発生した歪成分とAMP
Iで発生した歪成分の合成イ菩号であシ、AMP2の出
力信号は、信号源8Gの基本信号と並列f[帰均幅器A
で発生した歪成分とAJ′11P2で発生した歪成分の
合成信号である。ここで、Aム什1.AMP2を同一回
路41)、成でイに:成し/ζ場合、A%1.Pl 、
AMP2で各々発生した歪成分は#宕丁同等であるため
、AMP l 、 AMP 2各々出力伯号相互間での
歪率のアンバランスという不具合点は生じない。The output signal of each AMP2 is the base signal from the signal source SG, the distortion component generated by the parallel negative feedback amplifier A, and AMP1,
A composite signal with distortion components generated in each of AMP2 is output. In other words, the output signal of AMPI, the fundamental signal of signal source SG, the distortion component generated by parallel negative feedback amplifier A, and AMP
The output signal of AMP2 is a combination of the distortion components generated in I, and the output signal of AMP2 is parallel to the fundamental signal of signal source 8G.
This is a composite signal of the distortion component generated in AJ'11P2 and the distortion component generated in AJ'11P2. Here, Amu tithe 1. If AMP2 is the same circuit 41), if it is formed or ζ, then A%1. Pl,
Since the distortion components generated in AMP2 are equivalent to #宕锕, there is no problem of unbalanced distortion rates between the output numbers of AMP l and AMP2.
次に、スカシ1品子1から回h’i’z内部を見/こ入
力1ンピーダンスZ i 21’4−(5)式で水式れ
る。Next, look at the inside of the input h'i'z from the item 1 of the spacer 1 and calculate the impedance Z i 21'4 using the formula (5).
(5)式のRは(6)式で示される。R in formula (5) is represented by formula (6).
ことで、Ziozは、並列負帰還増幅器Aの入力インピ
ーダンス、πけ円周率、fは周波数を示す。Therefore, Zioz is the input impedance of the parallel negative feedback amplifier A, π multiplied by pi, and f is the frequency.
Ziozは、並列負帰還増幅器Aの入力インピーダンス
であるため、一般的数MΩり上と充分大きく、Zioz
中Zio トiA−ラhル。ヨッテ、上記(5) 、
(6)式は前記(1> 、 (2)式と同様と々す、
第1図で説明したごとく、入力インピーダンスZi2は
抵抗RIOの抵抗値で設定でき、詑2図のごとく入力イ
ンピーダンスのイト下という不具合恢は生じない。Since Zioz is the input impedance of the parallel negative feedback amplifier A, it is sufficiently large, more than the general several MΩ, and Zioz
Naka Zio ToiA-Rahr. Yotte, (5) above,
The formula (6) is the same as the formula (1> and (2) above),
As explained with reference to FIG. 1, the input impedance Zi2 can be set by the resistance value of the resistor RIO, and the problem of being below the input impedance as shown in FIG. 2 does not occur.
次に第4図に本発明の他の実施例をボす。第4図におい
て、AMPlは同相の負帰還電力増幅器、AMP2け逆
相の負帰還電力増幅器、Aけ1f・外弁帰還増幅器、C
1〜C16はトランジスタ、R1−R16は抵抗、It
、]−は弁荷(スピーカ)、D1〜])fiはダイオー
ド、C1〜C5けコンデンッ、J3,14は定電流源、
vCCは電圧源、1は入力端子を示す。Next, FIG. 4 shows another embodiment of the present invention. In Fig. 4, AMPI is an in-phase negative feedback power amplifier, AMP2 is an anti-phase negative feedback power amplifier, A is a 1f/outer valve feedback amplifier, and C is an in-phase negative feedback power amplifier.
1 to C16 are transistors, R1 to R16 are resistors, It
,]- is a valve load (speaker), D1~])fi is a diode, C1~C5 is a capacitor, J3 and 14 are constant current sources,
vCC represents a voltage source, and 1 represents an input terminal.
第4図においても、第3図と同様に入力信号は入力端子
1から並列帰還増幅器を介して同相負帰還電力増幅器A
R4P t 、逆相負帰還電力増幅器AMP2の入力端
子に同時に入力している為、AMPl 、 AMP2各
りの出力端子における各々の出力信号相互間での歪率ア
ンバランスという不具合点及び、入力端子1から回路内
部を見た入力インピーダンスの低下という不具合点は生
じない。In FIG. 4, as in FIG. 3, the input signal is passed from the input terminal 1 to the in-phase negative feedback power amplifier A
Since R4P t is simultaneously input to the input terminal of the anti-phase negative feedback power amplifier AMP2, there are problems such as distortion rate imbalance between the output signals at the output terminals of each of AMP1 and AMP2, and input terminal 1. The problem of a drop in input impedance when looking inside the circuit does not occur.
、I’、j上のように、本発明のB、T、L構成回路を
用いること(′r、よって、W来枝術における一対の電
力増幅器を用いZ、B、T、L回路での各)引ηカ信号
相互間での歪率のアンバランス及び、入力インピーダン
スの低下という不具合膚を防止できる。,I',j As above, using the B, T, L configuration circuit of the present invention ('r, Therefore, using a pair of power amplifiers in the W-raider technique, the Z, B, T, L circuit is It is possible to prevent problems such as unbalance of distortion rate between each pulling signal and a decrease in input impedance.
図面のF+枦表些明
第1図、第2図けそれぞれ従来例を示す回路図、第3図
、第4図はそれぞれ本発明の実施例を示す回路図である
。Figures 1 and 2 are circuit diagrams showing conventional examples, and Figures 3 and 4 are circuit diagrams showing embodiments of the present invention.
AMPI・・・・・・同相の負帰還電力増幅器、A M
l)2・・・・逆相のf]帰3!)電力増幅器、A・
・・・・・並列弁帰還増幅器、1・・・・・・入力端子
、2・・・・・・への出力端子、Q1〜Q16・・・・
・・トフンジスタ、Di〜jJ6・・・・・グイえ−ド
、C1〜(25・・・・・・コンデンサ、■もg、Rg
l、lもg2氾」〜J6・・・・・・抵17fi、IL
L・・・・・・負看I(スピーカ)、11〜14 ・・
・・・・定電流汗、〜CC・・・・・・電圧源、8G・
・・・・・信号発生結を七れぞt+示す。AMPI・・・In-phase negative feedback power amplifier, AM
l) 2...f of opposite phase] Return 3! ) Power amplifier, A.
...Parallel valve feedback amplifier, 1...Input terminal, 2...Output terminal to Q1-Q16...
...Tofunjita, Di~jJ6...Guide, C1~(25...Capacitor, ■Mog, Rg
l, l also g2 flood”~J6...Rei 17fi, IL
L... Negative view I (speaker), 11-14...
... Constant current sweat, ~CC... Voltage source, 8G.
...The signal generation results are indicated by t+.
−・ 、゛、
代理人 弁理士 内 原 晋す、’ ””、’、、、1
佑 1図
87図−・ , ゛, Agent Patent Attorney Shinsu Uchihara,'””,',,,1
Yu Figure 1 Figure 87
Claims (1)
列負帰還型増幅器の出力を同相増幅器としての第1の弁
帰還電力増幅器および逆相増幅器としての第2の負帰還
電力増幅器にそれぞれ供給し、前記第1および第2の電
力増幅器の出力端子間に負荷を接続したことを特徴とす
る電力増幅器。The input of the parallel negative feedback type amplifier is used as a signal input terminal, and the output of the parallel negative feedback type amplifier is supplied to a first valve feedback power amplifier as an in-phase amplifier and a second negative feedback power amplifier as an anti-phase amplifier, respectively. , a power amplifier characterized in that a load is connected between the output terminals of the first and second power amplifiers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58140834A JPS6032419A (en) | 1983-08-01 | 1983-08-01 | Power amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58140834A JPS6032419A (en) | 1983-08-01 | 1983-08-01 | Power amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6032419A true JPS6032419A (en) | 1985-02-19 |
JPH056368B2 JPH056368B2 (en) | 1993-01-26 |
Family
ID=15277794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58140834A Granted JPS6032419A (en) | 1983-08-01 | 1983-08-01 | Power amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6032419A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009249916A (en) * | 2008-04-07 | 2009-10-29 | Takamura Sogyo Kk | Protective plate made of rubber for impact resistance |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5622329U (en) * | 1979-07-31 | 1981-02-27 | ||
JPS5633809A (en) * | 1979-08-21 | 1981-04-04 | Bachorz Guenther | Method of manufacturing eeshaped core plate and iishaped returning path forming plate used for reactor or transformer |
JPS56136007A (en) * | 1980-03-26 | 1981-10-23 | Pioneer Electronic Corp | Phase inverting circuit |
JPS57111117U (en) * | 1980-12-26 | 1982-07-09 |
-
1983
- 1983-08-01 JP JP58140834A patent/JPS6032419A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5622329U (en) * | 1979-07-31 | 1981-02-27 | ||
JPS5633809A (en) * | 1979-08-21 | 1981-04-04 | Bachorz Guenther | Method of manufacturing eeshaped core plate and iishaped returning path forming plate used for reactor or transformer |
JPS56136007A (en) * | 1980-03-26 | 1981-10-23 | Pioneer Electronic Corp | Phase inverting circuit |
JPS57111117U (en) * | 1980-12-26 | 1982-07-09 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009249916A (en) * | 2008-04-07 | 2009-10-29 | Takamura Sogyo Kk | Protective plate made of rubber for impact resistance |
Also Published As
Publication number | Publication date |
---|---|
JPH056368B2 (en) | 1993-01-26 |
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