JPS6032346A - Mounting structure of semiconductor device - Google Patents

Mounting structure of semiconductor device

Info

Publication number
JPS6032346A
JPS6032346A JP14166583A JP14166583A JPS6032346A JP S6032346 A JPS6032346 A JP S6032346A JP 14166583 A JP14166583 A JP 14166583A JP 14166583 A JP14166583 A JP 14166583A JP S6032346 A JPS6032346 A JP S6032346A
Authority
JP
Japan
Prior art keywords
package
heat sink
wiring board
solder connection
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14166583A
Other languages
Japanese (ja)
Inventor
Katsuhiko Suzuki
勝彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14166583A priority Critical patent/JPS6032346A/en
Publication of JPS6032346A publication Critical patent/JPS6032346A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/20—Modifications to facilitate cooling, ventilating, or heating
    • H05K7/2039—Modifications to facilitate cooling, ventilating, or heating characterised by the heat transfer by conduction from the heat generating element to a dissipating body
    • H05K7/205—Heat-dissipating body thermally connected to heat generating element via thermal paths through printed circuit board [PCB]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To improve the electrical and thermal conduction by soldering the bottom of a package to the heat sink plate of a printed circuit board side directly without heat sink of the package. CONSTITUTION:When a flat package 12 is mounted on a ceramic circuit board 9, a solder connection unit 14 metallized and Au-plated so as not to shortcircuit to the lead mount 13 of the bottom of the package 12 is provided. A solder connection unit 15 metallized and Au-plated to the opposed ceramic circuit board is provided. For example, low melting point solder is preliminarily soldered to the leads 10 and the solder connection unit 14, a ceramic circuit board 9 is placed on the heater block, the package 12 is then placed, the both solder connection units 14, 15 are bonded to be scrubbed to moisten to each other, the connection unit of the pattern and the leads of the package are positioned, pressed from above and bonded.

Description

【発明の詳細な説明】 本発明は改良された半導体装置の実装構造に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved mounting structure for a semiconductor device.

従来半導体装置（以下パッケージと呼ぶ）をプリント配
線基板又はセラミック配線基板に実装する方法は、該基
板のスルーホールにパッケージのリードをリードストッ
パ一部まで挿入し半田付けしたものであった。この場合
該パッケージは、該基板から浮い状態となっているので
チップから発生する熱の放散はリードからの熱伝導とノ
くツケージ表面からの輻射しか行われないので７・イノ
くワーのパッケージの実装方法としては不適当であった
。A conventional method for mounting a semiconductor device (hereinafter referred to as a package) on a printed wiring board or a ceramic wiring board was to insert the leads of the package into the through holes of the board up to part of the lead stopper and solder them. In this case, since the package is floating from the substrate, the heat generated from the chip can only be dissipated by conduction from the leads and radiation from the cage surface. This was an inappropriate implementation method.

又フラットパッケージの実装はパッケージ底面が該基板
に密着しているけれども機械的なネジ止め又は半田など
で接着してはいないので上記と同様にハイパワーのパッ
ケージの実装方法としては完全ではない。Furthermore, in mounting a flat package, although the bottom surface of the package is in close contact with the substrate, it is not bonded with mechanical screws or solder, so it is not perfect as a method for mounting a high-power package, similar to the above.

従来の実装構造について図面を用いて説明する。A conventional mounting structure will be explained using drawings.

第１図、第２図、第３図、第４図、第５図は各々従来の
実装構造の断面図である。第１図はデュアルインパッケ
ージ（以下ＤＩＰと呼ぶ）のプリント板への実装状態で
ある。第２図は第１図のパッケージ表面にヒートシンク
を取付けたものである。FIG. 1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5 are sectional views of conventional mounting structures, respectively. FIG. 1 shows a state in which a dual-in package (hereinafter referred to as DIP) is mounted on a printed board. FIG. 2 shows a heat sink attached to the surface of the package shown in FIG. 1.

第３図は第１図の側面図である。第４図はフラットパッ
ケージの実装構造、第５図はヒートシンクを取付けたフ
ラットパッケージのプリント板への実装構造である。第
１，３図で示す従来の実装方法では、プリント配線基板
ＩＫＤＩＰ２のリード４が取付けられるスルーホール３
が配線パター７６の端部に設けられ、リード４がスルー
ホールに挿入され半田５により半田付けされる。この半
田付は状態は、プリント板ｌのスルーホール３に挿入さ
れたり一ド４のストッパ一部７の径がスルーホール３の
径よりも大きいのでストッパ一部７で止まる。しかもリ
ードストッパ一部７はパッケージ底面より０．５　、、
位離れているのでパッケージ底面は必ずプリント配線基
板面から浮いた状態にある。この実装方法であると熱放
散は、リード４からの伝導、パッケージ表面からの輻射
しか行われないので比較的発熱量の多いノ・イバワーの
半導体装置の実装方法には不利である。第２図は、第１
図の欠点を補うためにパッケージ表面にヒートシンク８
を取シ付けて熱放散を改良したものである。FIG. 3 is a side view of FIG. 1. FIG. 4 shows a mounting structure of a flat package, and FIG. 5 shows a mounting structure of a flat package with a heat sink attached to a printed board. In the conventional mounting method shown in FIGS. 1 and 3, the through hole 3 to which the lead 4 of the printed wiring board IKDIP2 is attached
is provided at the end of the wiring pattern 76, and the leads 4 are inserted into the through holes and soldered with solder 5. This soldering is done when the soldering is inserted into the through-hole 3 of the printed board 1, and because the diameter of the stopper part 7 of the lead 4 is larger than the diameter of the through-hole 3, it stops at the stopper part 7. Moreover, the lead stopper part 7 is 0.5 from the bottom of the package.
The bottom of the package is always floating above the surface of the printed wiring board. In this mounting method, heat is dissipated only through conduction from the leads 4 and radiation from the package surface, which is disadvantageous for mounting a high-power semiconductor device that generates a relatively large amount of heat. Figure 2 shows the first
Heat sink 8 on the package surface to compensate for the defects in the figure.
The heat dissipation is improved by attaching a

第４図は、フラットパッケージ１２をセラミック配線基
板９の配線パターン６にパッケージのリード１０を半田
付けを行ない熱放散を良くする為に放熱板１１を該セラ
ミック配線基板９の裏面にネジ止め又は半田付は等を行
ったものである。第５図は、第４図に示した実装構造で
はフラットパッケージ１２の底面が基板９に完全に密着
していないために熱伝導が良くないのでこれを改良した
ものである。即ちパッケージ１２の底面に例えばＣｕあ
るいはＡＩなどのヒートシンク８をロウ付けしチップか
らの発生熱をすみやかにヒートシンク８に伝達しさらに
フラットパッケージ１２のヒートシンク８が放熱板１１
にネジ込まれている為にヒートシンク８から放熱板ｉｉ
に速やかに熱伝達が行われ良好な熱放散が行われる。FIG. 4 shows a flat package 12 with the leads 10 of the package soldered to the wiring pattern 6 of the ceramic wiring board 9, and a heat sink 11 screwed or soldered to the back side of the ceramic wiring board 9 to improve heat dissipation. The attached is the one that was done. FIG. 5 is an improved version of the mounting structure shown in FIG. 4, since the bottom surface of the flat package 12 is not in complete contact with the substrate 9, resulting in poor heat conduction. That is, a heat sink 8 made of, for example, Cu or AI is brazed to the bottom of the package 12 so that the heat generated from the chip is quickly transferred to the heat sink 8, and the heat sink 8 of the flat package 12 is also connected to the heat sink 11.
Because it is screwed into the heat sink 8, the heat sink ii
Heat transfer occurs quickly and good heat dissipation occurs.

しかしながら上述した実施例第１図、第２図に示す実装
構造ではパッケージ底面がプリント配線基板に密着して
いない為に良好な熱放散が行われない。また実施例第４
図、第５図は、ノ・イバワーのＩＣの実装に際してセラ
ミック配線基板と放熱板を用いて熱放散を増大させよう
と試みたものであるが第４図は実装溝造上やはり第１図
、第２図と同様にパッケージ底面が密着しない為に期待
した程の熱放散は行われない。第５図は、第４図を改良
したものであシ良好な熱放散が行われるけれどもパッケ
ージにヒートシンクを取付ける為にコスト高になること
と放熱板１１にネジを切りこれにヒートシンクをネジ込
み実装するので実装工数が増大するなどの欠点がおった
。However, in the mounting structure shown in FIGS. 1 and 2 of the above-described embodiments, the bottom surface of the package is not in close contact with the printed wiring board, so that good heat dissipation cannot be achieved. Also, Example 4
Figure 5 shows an attempt to increase heat dissipation by using a ceramic wiring board and a heat sink when mounting a no-power IC, but Figure 4 shows the mounting groove structure, and Figure 1 shows the same. As in FIG. 2, the bottom surface of the package does not come into close contact with each other, so the expected heat dissipation is not achieved. Figure 5 is an improved version of Figure 4. Although good heat dissipation is achieved, the cost is high because the heat sink is attached to the package, and the heat sink is mounted by cutting screws into the heat sink 11. Therefore, there were drawbacks such as increased mounting man-hours.

本発明は上述した従来の欠点を除去した高品質のパッケ
ージ実装方法を提供するものである。The present invention provides a high quality package mounting method that eliminates the above-mentioned conventional drawbacks.

すなわち本発明は、パッケージの内側に接着されたチッ
プからの発熱をパッケージのヒートシンクなしで直接プ
リント配線基板側の放熱板にパッケージ底面を半田付け
することによって電気的。That is, the present invention electrically converts the heat generated from the chip bonded to the inside of the package by directly soldering the bottom of the package to the heat sink on the printed wiring board side, without using a package heat sink.

熱的な伝導を良好にした事を特徴とする。It is characterized by good thermal conduction.

以下本発明の実施例について図を用いて説明する。第６
図、第７図に示す様にフラットパッケージ１２の底面は
セラミック配線基板９又は放熱板１１に直接半田付けし
である。第６図は、第４図を改良した構造の一例であシ
ハイパワーの７ラツトパツケージ１２をセラミック配線
基板９に実装する場合、まずフラットパッケージ１２の
底面のリード取付部１３にショートしない様にメタライ
ズ化させＡｕメッキした半田接続部１４を設ける。Embodiments of the present invention will be described below with reference to the drawings. 6th
As shown in FIG. 7, the bottom surface of the flat package 12 is directly soldered to the ceramic wiring board 9 or the heat sink 11. FIG. 6 shows an example of a structure improved from FIG. 4. When mounting a high-power 7-rat package 12 on a ceramic wiring board 9, first metallize the lead mounting portion 13 on the bottom of the flat package 12 to prevent short circuits. A solder connection portion 14 plated with Au is provided.

又相対するセラミック配線基板にもメタライズ化しＡｕ
メッキした半田接続部１５を設けておく。Also, the opposing ceramic wiring board is also metalized with Au.
A plated solder connection portion 15 is provided.

このパッケージ１２とセラミック配線基板９を接続する
方法は、リード五〇と半田接続部１４にｐｂ−８ｎ又は
Ａｇ−８ｎなどの低融点半田を予備半田しておき、ヒー
ターブロック上にセラミック配線基板をのせ、次にパッ
ケージをのせ、まず両半田接続部１４．１５を合せてお
互いが良く濡れ合うようにスクラブし次にプリント配線
基板のパターンの接続部とパッケージのリードとを位置
合せして上部より圧着してお互いを接着させるとパッケ
ージ１２の底面半田接続部１４とリード１０がセラミッ
ク配線基板９の半田接続部１５とパターンの接続部に正
確に接続される。次にこのセラミック配線基板９と１又
はＣｕなどの放熱板ｊｌにネジ止めをする。The method for connecting this package 12 and the ceramic wiring board 9 is to pre-solder the leads 50 and the solder connection part 14 with low melting point solder such as PB-8N or Ag-8n, and then place the ceramic wiring board on the heater block. Next, place the package, first align both solder joints 14 and 15, and scrub them so that they are well wetted. Next, align the connection parts of the printed wiring board pattern with the leads of the package, and then When they are bonded together by pressure bonding, the bottom solder connection portion 14 of the package 12 and the lead 10 are accurately connected to the solder connection portion 15 of the ceramic wiring board 9 and the connection portion of the pattern. Next, the ceramic wiring boards 9 and 1 or the heat sink jl made of Cu or the like are screwed.

第７図は、従来の方法の第４図を改良した他の一例を示
したものである。セラミック配線基板９は、パッケージ
１２のリード１０の近辺まで配線パターンを施し接続部
とし、パッケージ１２の底面にあたる部分をくシ貫きセ
ラミック配線基板９のパターンとり一ド１０を半田接続
し７’Ｃ６とパッケージ底面が露出するようにする。又
、放熱板１１は、ｋｌ又はＣｕ板のような熱伝導の良い
金属を用い、前記セラミック配線基板の貫通孔１６に入
るように放熱板１１に凸部１７を設は半田接続部１５を
形成する。このような構造の実装方法は、まず１例とし
て、放熱板１１の材質をＣｕ板とし凸部１７にはｐｂ−
ａｎ又はＡ　ｇ　−８ｎ系半田を予備半田し次にセラミ
ック配線基板９の代りにプリント配線基板を該セラミッ
ク配線基板９と同様の形状にしたものと前記放熱板１１
を嵌合・密着させて接着材で一体構造とする。この一体
化構造の放熱板付プリント配線基板にヒート７ンクなし
の７ラントパツケージをまず放熱板１１の凸部１７の半
田接続部１５とパッケージ２の底面半田接続部１４とを
ヒーターブロック上で加熱しながらスクラブして溶融接
着させ、次にリード１０とパターンとを位置合せして圧
着して接続しヒーターブロック上から取り外し、冷却す
ることによって接続が完了する。FIG. 7 shows another example of the conventional method, which is an improvement on the conventional method shown in FIG. The ceramic wiring board 9 is provided with a wiring pattern up to the vicinity of the leads 10 of the package 12 as a connection part, and the bottom surface of the package 12 is pierced and the patterned leads 10 of the ceramic wiring board 9 are soldered and connected to 7'C6. Make sure the bottom of the package is exposed. The heat sink 11 is made of a metal with good thermal conductivity such as a KL or Cu plate, and a convex portion 17 is provided on the heat sink 11 so as to fit into the through hole 16 of the ceramic wiring board, and a solder connection portion 15 is formed. do. As an example of a mounting method for such a structure, the material of the heat dissipation plate 11 is a Cu plate, and the convex portions 17 are made of PB-
An or A g -8n type solder is pre-soldered, and then a printed wiring board with the same shape as the ceramic wiring board 9 is used instead of the ceramic wiring board 9, and the heat sink 11 is used.
The parts are fitted and brought into close contact to form an integral structure using adhesive. A 7 runt package without a heat sink is mounted on this integrated printed wiring board with a heat sink, and first the solder connection part 15 of the convex part 17 of the heat sink 11 and the bottom solder connection part 14 of the package 2 are heated on a heater block. The lead 10 and the pattern are then aligned and connected by pressure bonding, removed from the heater block, and cooled to complete the connection.

以上の様に本発明はパッケージの底面を配線基板又は放
熱板に直接半田接続することによって熱伝導を行わせし
めることによシ良好な熱放散効果が得られると共に第５
図と第７図のパッケージを比較するとわかるようにパッ
ケージへのヒートシンクの取付けが不用となシ実装方法
もネジ込みが不用となり工数減少にもつなが多、実装及
び部品のコストダウンに寄与するものである。As described above, the present invention achieves a good heat dissipation effect by directly soldering the bottom surface of the package to the wiring board or the heat sink, thereby achieving a good heat dissipation effect.
As can be seen by comparing the packages in Figure 7 and Figure 7, there is no need to attach a heat sink to the package, and the mounting method also eliminates the need for screws, which leads to a reduction in man-hours and contributes to lower mounting and component costs. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はＤＩＰの実装状態の断面図、第２図は第１図の
パッケージにヒートシンクを取付けた構造、第３図は第
１図の側面図、第４図はフラットパッケージの実装状態
、第５図はフラットパッケージにヒートシンクを取付け
た実装構造の各々断面状態図である。第６図、第７図は
各々本発明の実施例の断面図である。 なお図において、ｌ・・・・・・プリント配線基板、２
・・・・・・デュアルインラインパッケージ、３・・・
・・・スルーホール、４．１０・・・・・・リード、５
・・−・・・半田、６・・・・・・配線パターン、７・
・・・・・リードストッパ一部、８・・・・・・ヒート
シンク、９・・・・・・セラミック配線基板、１１・・
・・・・放熱板、１２・・・・・・フラットパッケージ
、１３・・・・・・リード取付部、１４．１５・・・・
・・半田接続部、１６・・・・・・貫通孔。 聚１目 半２　回 Ｙ′５回 華左面 第ｆ回Figure 1 is a cross-sectional view of the DIP mounted state, Figure 2 is a structure in which a heat sink is attached to the package in Figure 1, Figure 3 is a side view of Figure 1, and Figure 4 is a flat package mounted state. FIG. 5 is a cross-sectional view of a mounting structure in which a heat sink is attached to a flat package. 6 and 7 are sectional views of embodiments of the present invention, respectively. In the figure, l...printed wiring board, 2
...Dual inline package, 3...
...Through hole, 4.10...Lead, 5
・・・－・・・Solder, 6...Wiring pattern, 7・
... Part of lead stopper, 8 ... Heat sink, 9 ... Ceramic wiring board, 11 ...
... Heat sink, 12 ... Flat package, 13 ... Lead attachment part, 14.15 ...
...Solder connection part, 16...Through hole. Ju 1st and a half 2nd Y'5th Hana left side fth

Claims (2)

【特許請求の範囲】[Claims] （１）　プリント配線基板又はセラミック配線基板と金
属放熱板とから構成される半導体装置の実装構造におい
て、該配線基板の任意部分にパッケージ底面とほぼ等し
い半田接続部を設は該半田接続部とパッケージ底面とが
半田接続されかつ該基板の配線パターンと該パッケージ
のリードとが接続されている事′ｔ−特徴とする半導体
装置の実装構造。(1) In a semiconductor device mounting structure consisting of a printed wiring board or a ceramic wiring board and a metal heat sink, a solder connection part that is approximately equal to the bottom surface of the package is provided on an arbitrary part of the wiring board, and the solder connection part and the package are connected to each other. A mounting structure for a semiconductor device, characterized in that the bottom surface is soldered and the wiring pattern of the substrate is connected to the leads of the package. （２）プリント配線基板又はセラミック配線基板と金属
放熱板とから構成てれる半導体装置の実装構造において
、該金属放熱板と任意部分に貫通孔が設けられた該配線
基板とが接着された該配線基板の金属放熱板部分にパッ
ケージ底面とほぼ等しい半田接続部を設は該半田接続部
とパッケージ底面とが半田接続されかつ該基板の配線パ
ターンと該パッケージのリードとが接続されている事を
特徴とする半導体装置の実装構造。(2) In a semiconductor device mounting structure composed of a printed wiring board or a ceramic wiring board and a metal heat sink, the wiring is bonded to the metal heat sink and the wiring board with through holes provided in arbitrary parts. A solder connection part that is approximately equal to the bottom surface of the package is provided on the metal heat sink part of the board, and the solder connection part and the bottom surface of the package are connected by solder, and the wiring pattern of the board and the lead of the package are connected. Mounting structure of semiconductor device.
JP14166583A 1983-08-02 1983-08-02 Mounting structure of semiconductor device Pending JPS6032346A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14166583A JPS6032346A (en) 1983-08-02 1983-08-02 Mounting structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14166583A JPS6032346A (en) 1983-08-02 1983-08-02 Mounting structure of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6032346A true JPS6032346A (en) 1985-02-19

Family

ID=15297326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14166583A Pending JPS6032346A (en) 1983-08-02 1983-08-02 Mounting structure of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6032346A (en)

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