JPS6031686A - Frequency counter - Google Patents

Abstract

PURPOSE:To attain detection of generation of erroneous counts, by providing a detection circuit which detects and compares polarity of input pulse synchronizing with rise and fall of gate signals. CONSTITUTION:Gate signal 7 is converted into the 1st clock signal 16 through a monostable multivibrator 11a. Then, an FF13a becomes at a rise timing of the signal 16 such that when an input pulse string 6 is logic ''1'', logic ''1'' is obtained, and when it is logic ''0'', logic ''0'' is obtained. This condition is retained until a reset signal 18 arrives. Output of the FF13a becomes the 1st discrimination signal 19. In addition, a signal 7, whose polarity of logic ''1'' and ''0'' is inverted through an inverter 12, turns into an inverted gate signal 15 and into the 2nd clock signal 17 through a monostable multivibrator 11b. Next, an FF13a operates at a rise timing of a signal 17 such that the input pulse string is logic ''1'', logic ''1'' is obtained, and when it is logic ''0'', logic ''0'' is obtained. This condition is retained until the signal 18 arrives. Output of the FF13b a becomes the 2nd discrimination signal 20. An AND circuit 14 compares a signal 19 with 20 and sends a signal of logic ''1'' as a detected signal 21 only when both the signals are logic ''1''.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a frequency counter that counts the frequency of a pulse train by counting the pulse train every unit time, and is characterized by being able to detect the occurrence of erroneous counting. It provides a frequency counter.

First, a conventional frequency counter will be briefly explained with reference to FIG.

In Figure 1, (1) is a gate circuit, (2) is a gate signal generator, (3) is an addition counter, (4) is a latch circuit, (5) is a display, (6) is an input pulse train, and (7) is a latch circuit. ) is the gate signal.

(8) is an output pulse train, (9) is a reset signal, and αα is a latch signal.

In this frequency counter, an input pulse train (6) is compared in a gate circuit (1) with a gate signal (7) generated by a gate signal generator (2), and the gate signal (7) is
passes through the gate circuit (1) only while the signal is at logic 1. The output pulse train (8) of the gate circuit (1) is processed by the addition counter (
3), and the counted value is stored in the latch circuit (4) every time the latch signal αe is generated, and simultaneously displayed on the display (5). Next, the count value of the addition counter (3) is 1.
Generation of the set signal (9) (2) and the count C2 of the output pulse train (8) output from the primary (nigate circuit (1)) are provided.

In this way, the conventional frequency counter described above calculates the zZ, ) of the gate signal (7) every repetition period of the gate signal (7).
Because the input pulse train (6) is counted for the time equal to the response width.

It is possible to count the number of pulses per unit time, that is, the frequency of the input coupler resistor 6).

However, the conventional frequency counter described above controls the counting timing with the gate signal (7), so the input pulse train (
It is not synchronized with the pulse generation timing in step 6), and when it passes through the gate circuit (1), the /clueless signal may be divided, resulting in erroneous counting.

In other words, Figure 2 shows the human coupler train (6) and the gate signal (7).
) and the operation of the output pulse train (8). Since the input pulse train (6) passes through the gate circuit (2) only while the gate signal (7) is logic 1, the input pulse train (6) When the pulse width is wide, depending on the timing of the input pulser 6) of the gate signal (7), a phenomenon occurs in which one pulse is divided into two, and the pulse selected by the previous gate signal is split into two. Since the latter half is also selected by a later gate signal, there is a drawback that one pulse is counted twice.

The present invention aims to improve the above-mentioned drawbacks of the conventional frequency counter, and includes a detection circuit that detects and compares the polarity of the input pulse in synchronization with the rising and falling edges of the gate signal, and detects the occurrence of erroneous counting. It has been made possible.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention,
(lla) (Ilb) is a monostable multivibrator, a is an inverter, (13a) (13b) is a flip-flop, (141 is an AND circuit, (19 is an inverted gate signal, +161 is a first clock signal, <171
is the second clock signal, Q81 is the second reset signal, αω
is the first discrimination signal, (201 is the second discrimination signal, c! ■ is the detection output. (2211 is the detection circuit, and two monostable multivibrators (lla) (llb).

Inverter α, two flip-flops (13a)
(13b) and an AND circuit (141).

In FIG. 3, the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and the operations thereof are also the same, so redundant explanation will be omitted.

Further, FIG. 4 is a time chart showing the operation of each part of the detection circuit @, and the operation of FIG. 3 will be explained with reference to FIG.

As explained above with reference to FIG. 2, the disadvantages of the conventional frequency counter are as follows: When the input pulse and the pZ response width are wide, one input pulse may span two measurement gates next to each other. This was causing erroneous counting. Therefore, by detecting this state, it is possible to know the occurrence of erroneous counting. Figure 3 shows whether the input/crux string (6) is logic 1 or 0 in synchronization with the rise and fall of the gate signal (7).
The system detects the occurrence of erroneous counting by detecting whether or not the number of counts is the same. First, the gate signal (7) is shaped by the monostable altivibrator (lla) into a narrow pulse of 9 width, and this is set as the first clock signal +119. In other words, the first clock signal is the rising edge of the gate signal (7). The next (=flip-flop (Qa) is a logic 1 if the input pulse train (6) is a logic 1 at the rising timing of the first clock signal αυ.If it is a logic 0, it is a logic 0. become.

This state is maintained until the second reset signal (181) arrives.The output of this flip-flop (13a) becomes the first discrimination signal.

On the other hand, the gate signal (7) has its logic 1.0 polarity inverted by the inverter Q2) and becomes a 9 inverted gate signal (151), which is further inverted by the monostable multivibrator (Ilb) (
= Therefore, it is shaped into a narrow pulse and becomes the second clock signal 0'71. In other words, the second clock signal 0η is a pulse indicating the falling timing of the gate signal (7).

Next, if the input pulse train (6) is logic 1 at the rising edge of the second clock signal (171), it becomes logic 1. If it is logic 0, it becomes O. Hold until α second comes.

The output of this flip-flop Q3b) is the second discrimination signal (
company).

A'nd circuit α→ compares the first discrimination signal aω and the second discrimination signal (A), and only when both are 6 two-wheel logic l, the logic is 1.
The signal is output as the detection output Qυ. The operations of each section described above are as shown in the time chart of FIG.

In this way, the detection circuit (2) detects that the input pulse train (6) is a logic 1 in synchronization with the rise and fall of the gate signal (7).
When both are logic 1, a logic 1 output signal indicating that an erroneous count has occurred is outputted as a detection output (211) to detect an erroneous count.

As described above, the frequency counter according to the present invention has the advantage of being able to detect the occurrence of erroneous counts.

Since the occurrence of miscounting is at most one pulse per gate, various correction methods can be considered, such as using a subtractor or the like to correct the count value before it is displayed on the display (5). This invention is not limited to a correction method, but is meaningful in detecting miscounts.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional frequency counter. FIG. 2 is a time chart for explaining the operation of a conventional frequency counter, FIG. 3 is a block diagram showing an embodiment of the frequency counter of the present invention, and FIG. 4 is for explaining the operation of the frequency counter of the present invention. This is a time chart for In the figure, (1) is a gate circuit, and (2) is a gate signal generator. (3) is an addition counter, (4) is a launch circuit, and (5) is a display. (6) is an input pulse train, (7) is a gate signal, (8) is an output pulse train, (9) is a beam set signal, and flo+ is a latch signal. (1ta) (nb) is a monostable multivibrator, a
Inverter, (13a) (13b) Lt7! J
Block 707, tta hand and circuit, +151 is the inverted gate signal, (161 is the first clock signal, 0 is the second clock signal, (1 (to) is the second reset signal,
+191 is the first discrimination signal, (a) is the second discrimination signal,
(21+ is the detection output, @ is the detection circuit. In Figure 9, the same or equivalent parts are indicated with the same symbols. Agent Masuo Oiwa

Claims (1)

[Claims] A gate signal generator that generates a gate signal with a constant pulse width at a constant (repetition period), a gate circuit that is controlled by the gate signal and passes an input pulse train for a time equal to the pulse width of the gate signal, and an output of the gate circuit. In a frequency counter that counts the number of pulses of the input pulse train every time the gate signal is repeated, the frequency counter is equipped with an addition counter that counts the pulse train every repetition period of the gate signal, and the frequency counter counts the number of pulses of the input pulse train every time the gate signal is repeated. It determines whether the input pulse train is logical 1 or 0 in synchronization with the timing of each, and when both are logical 1, one pulse of the input pulse train is divided into two by two gate signals that are adjacent to each other. 1. A frequency counter comprising a detection circuit that detects when each of the divided sections is counted redundantly and is capable of notifying the occurrence of erroneous counting.