JPS603026A - Information processor - Google Patents

Abstract

PURPOSE:To perform fast process switching by performing conversion from a virtual process number to an actual process number through a group of registers corresponding to plural actual processes. CONSTITUTION:An information processor includes a process control part 10, actual process register group 20, virtual process identifier information register 30, register specifying register 40, registered virtual process identifier information holding register 50, comparing circuit 60, and communicating circuit 70. The process control circuit 10 uses said holding circuit 50 and comparing circuit 60 to convert a virtual process number into an actual process number, which is used as a part of an address to the actual process register group 20.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device capable of multiple programming.

In conventional multi-programmable information processing devices, when a process is running and a process with a higher priority than that process becomes executable,
The currently running process [7] is the main culprit, and the registers in the information processing device are saved to the upper process control block, and the information is stored in the main memory corresponding to the higher-ranked process. The LJJ change of the process is performed by storing the register I and the register in the processing device.

However, this process switch is impossible! 'l/t'
3 Since the number of registers to be stored is large, it takes a lot of time, resulting in a large performance drop, and it has the disadvantage that it cannot be applied to applications that require real-time performance (immediate response). Therefore, an object of the present invention is to provide an information processing apparatus that eliminates the above-mentioned drawbacks and is capable of high-speed process switching.

According to the present invention, in an information processing device capable of multiple programming, a group of registers corresponding to a plurality of real processes, a means for holding virtual process identification information, and a means for holding this virtual process identification information are provided. a process identification conversion means that receives an output from the virtual process and converts the identification information of the virtual process into real process identification information, and converts the real process identification information converted by the process identification conversion means into one of the address information to the register group. There is obtained an information processing device characterized in that it has a means for making a part.

The invention will now be described in detail with reference to FIG. 1m.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. First, let me explain the outline of the (11J).

The information processing apparatus of the present invention shown in FIG.
0. Real process register group 20. Virtual process identification information register 30. Register specification register 40. Registered virtual process identification information holding circuit 50. It includes a comparison circuit 60 and a connection circuit 70. Note that signal lines through which the output of the process control circuit 10 is sent to other circuits are omitted.

Next, to explain the detailed configuration and operation of the device shown in FIG. 1, the actual process register T20 has register sub-registers if 21.22. -23. Register subgroup 21.22.・26 is the real process number 0, 1.
...n-1 (n is a positive integer), respectively, and
It includes general purpose registers (OR), base registers (BR), italic operation registers (SR), instruction cucumbers (■C), etc. of executable processes. Each register width rrt
21.

22, . . . 26 correspond to all of the software-visible registers of the prior art. In other words, in the prior art, this corresponds to registers in n information processing apparatuses. However, other parts of the information processing device (for example, arithmetic control circuit, MKM
Since there is only one access control circuit, etc., one of these registers is actually the sub-I! Only the process corresponding to the process is in the execution state pl.

Although there may be a maximum of n real processes in the information processing device as described above, there are many more virtual processes created by software, and only some of these are mapped to real processes. Information identifying this virtual process exists in the temporary process identification register 60. The contents of the virtual process identification register 30 are divided into two fields, a first field 61 and a second field 62.

The first field 31 is connected on one side to the registered virtual process identification information holding circuit 50 as write data via the data line a, and is also connected to one input of the comparison circuit 60 as comparison data to be explained later.

The registered virtual process identification information holding circuit 50 has the same number of entries as the number n of register subgroups.

Each entry contains a validity bit. The entry of the registered virtual process identification information holding circuit selected via the data line by the second field 62 of the virtual process identification register 30 is.

It is connected to the other input of the comparison circuit 60 by the data line C, and is also sent to the connection circuit 70 at the same time.

The comparison circuit 60 compares the write data sent from the first field 31 of the process identification register via the data line a and the selected write data sent from the registered virtual process identification information holding circuit 50 via the data line C. 2, and when the comparison does not match, that is, when the process set in the virtual process identification register 3o is not included in the real process register I20, the process control circuit 1 is sent via the output signal line d.
Interrupt to 0. It will be explained later that when the comparison results match, the process set in the virtual process identification information register 60 is included in the register 7FT20.

The process control circuit 10 includes register subgroups 21, 22 .・Determine one of 26 by a replacement algorithm, save the contents of the register subgroup in the process control block in the main memory (not shown) of the corresponding process 1'', and save the contents of the register subgroup 3 to the virtual process identification information register 3.
Read from the process control block within t= above corresponding to the process specified by o, and register sub-register ffY21.
~26. Thereafter, the process control circuit 10 registers the process in the virtual process identification information register 30 in the registered virtual process identification information holding circuit 50 by writing the contents of the first field 61 and the contents of the second field 62 as an address. do.

The process control circuit 10 also includes: When a running process is lost due to termination of the process, the lost virtual process information is stored in the virtual process identification information register 6D, and the registered virtual process identification information holding circuit 50 and comparison circuit 60
The output of the signal line d, which is the result of the comparison circuit 60, is indexed using 111M, and this output is the actual process register group 2
When indicating that 0 includes a terminated process, another virtual process information is read from the main memory and stored in the 1) real process register i20.

Next, information processing device 6. This section explains how to specify the registers needed during the execution of a process consisting of a process.

The virtual process number is stored in the information register 30 for each virtual process 8j1. This is done by the process control circuit 10 when putting a certain virtual process into an execution state. Further, information specifying the required register is set in the register specification register 40. Process identification register 30
The first field 31 of
0 connected to one human power A1゜second field 62)
Registered as entry address information (7) sent to virtual process identification information holding circuit 50 via one data line.
” will be done. The output of the registered virtual IJ SENU identification information holding circuit 50 is connected to another input of the comparison circuit 60 via a signal line C. The comparison result of the comparison circuit 60 is sent to the signal line 3 via the signal line d.
-l Senu control circuit 10 3, comparison result is invalid.
.

In other words, when the process set in the virtual process identification information register 30 does not exist in the real process register group 20, register successive writing is interrupted, and the process control circuit 10 reads out the process information from the main memory as described above. Real process register 1! After setting τ20, the above operation is repeated.

If the comparison result is a match, the process identification regime virtual block [I
The second f- field 32 of the SENU identification information register 60 and the register designation register 40 are sent to the connection circuit 70 via the husband/l data line 1) and e. The address information for the connected real process registers ff120 is sent to the real process register group 20 via the data line f, and the value of a desired register is sold from the real process registers /il', 20. In this way, in this embodiment, register sub-1 corresponds to n processes! has τ.

This L')J4'''re is performed instantly by simply setting the process identification information in the virtual process identification information register.

As explained above, the present invention requires a plurality of actual processes.
High-speed process switching is possible using the corresponding register group, a means for converting the virtual process number into a real process number, and Nr, which makes the real process number part of the address to the register group.

4 remaining days below: Drawing I! i'i ii'I Explanation FIG. 1 is a block diagram showing the configuration of an information processing device that is an embodiment of the present invention. 3. Explanation of symbols. 10 is a process: Real process register 1!□''1, 21-2 (J register sub 1jT, 30 contains virtual process identification information '1φ and 7 stars.

40 is a register specification register, 50 is a registration (1v-;u
,'! 60 is a comparison circuit.

Claims (1)

[Claims] 1. In an information processing device capable of multiple block programming,
A register 1 corresponding to a plurality of real processes, and a means for keeping virtual process identification information. A process identification conversion means for converting the identification information of the virtual process into real process identification information using the output from the means for holding the virtual process identification information, and a process identification conversion means for converting the identification information of the virtual process into real process identification information; An information processing apparatus characterized by comprising: means for making address information to the register IIT a part of address information.