JPS603001A - Input data processor - Google Patents

Input data processor

Info

Publication number
JPS603001A
JPS603001A JP58112183A JP11218383A JPS603001A JP S603001 A JPS603001 A JP S603001A JP 58112183 A JP58112183 A JP 58112183A JP 11218383 A JP11218383 A JP 11218383A JP S603001 A JPS603001 A JP S603001A
Authority
JP
Japan
Prior art keywords
signal
analog
converter
digital
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58112183A
Other languages
Japanese (ja)
Inventor
Takashi Kususe
楠瀬 喬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58112183A priority Critical patent/JPS603001A/en
Publication of JPS603001A publication Critical patent/JPS603001A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/1608Error detection by comparing the output signals of redundant hardware

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Alarm Systems (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To obtain a data processor which decides on which signal is normal automatically when input data is abnormal and supplies the normal signal to a proper system by adding a self-monitoring function to a mutual monitoring function between two systems. CONSTITUTION:The self-monitoring function is added to the mutual monitoring function between the two systems. For example, a signal 10 indicating a physical quantity is inputted to the 1st converter 11 and the 2nd converter 12 and converted into analog signals 1a and 2a proportional to the amplitude of the input signal. Then, the analog signal 1a is converted into a digital signal 2a through an analog/digital converter ADC21, and this signal is converted into an analog signal 4a through a digital/analog converter DAC41 to detect whether the analog signals 1a and 4a coincide with each other within a permissible error range through the comparison of a comparator 51. Further, a comparator 52 compares analog signals 1b and 4b with each other similarly. A comparator 3 sends out a normal signal to an A system 61, etc., on the basis of the detection results of the comparators 51 and 52 when the dissidence between the signals 2a and 2b is detected.

Description

【発明の詳細な説明】 この発明は2重化された人力データ処理装置に関し、!
1芋に人力データに異常が発生した場合の処理に関する
ものである。
[Detailed Description of the Invention] The present invention relates to a dual human-powered data processing device!
This relates to processing when an abnormality occurs in the human data for one potato.

第1図に従来の装置を示すブロック図て、図において(
1旧よ第1の変換器、α力は第2の変換器、(2りは第
1のアナログディジクル変榔器(以下Al)Cと略記す
る)、(22)U @2 ノADC、+31 t+、j
比軸器、(61)はAシステム、(1)4はBシステム
である。また!Ifll 。
Figure 1 is a block diagram showing a conventional device.
1 The old is the first converter, the α force is the second converter, (2 is the first analog digital converter (hereinafter abbreviated as Al)C), (22) U @2 No ADC, +31 t+,j
The ratio axis device (61) is the A system, and (1) 4 is the B system. Also! Ifll.

(Ia)、(1b)、(2a)、(2りはそれぞれの信
号を示す。
(Ia), (1b), (2a), (2 indicates each signal.

信号量)は、たとえば電力系統の計器用変圧器、N1器
用変流器から得た信号交流電圧でろって、この信号交流
電圧の振幅が測定すべき電圧、′混流の振幅に比例して
いるような信号であり、この明細書では一般的に物理量
を表す信号という、信号(10)はディジタル信号の形
に変換されて諸種の処理や制御に用いられるのであるが
、ディジクル信号に変換される前に、夏換器旧)、α陣
によってそれぞれADCの入力に適した形の直流電圧に
変換されるっ信号(10)がたとえば商用周波数の交流
電圧である場合、変換器U、(6)は全波整流回路全含
み、入力交流電圧の振幅に比例する直流電圧全出力する
っしたがって信号(la)、(lb)はこのような直流
アナログ電圧で、それぞれADC(21)、 (22)
によってディジタル信号(2a)、(2b)に変換され
る。信号(2a)。
The signal amount) is, for example, the signal AC voltage obtained from the voltage transformer or N1 current transformer in the power system, and the amplitude of this signal AC voltage is proportional to the voltage to be measured, the amplitude of the mixed current. In this specification, the signal (10), which is generally referred to as a signal representing a physical quantity, is converted into a digital signal and used for various processing and control, but it is converted into a digital signal. If the signal (10) is, for example, a commercial frequency AC voltage, the converter U, (6) is converted into a DC voltage suitable for input to the ADC by the α group. contains all the full-wave rectifier circuits and outputs all the DC voltage proportional to the amplitude of the input AC voltage. Therefore, the signals (la) and (lb) are such DC analog voltages, and the ADCs (21) and (22) respectively
are converted into digital signals (2a) and (2b) by. Signal (2a).

(2りは同一の信号(lO)から変換した信号であるの
で、信号(2a)と信号(2b)は一致する筈である。
(Since signal 2 is a signal converted from the same signal (lO), signal (2a) and signal (2b) should match.

比較器(3)はこの一致を検出し、一致しておれば信号
(2a)、(2b)はそれぞれ正常であるとし、不一致
の場合は異常であるとして、信号(2a)、(2b)共
にその使用が禁止されろう 従来の入力データ処理装置は以上の如く動作し、比較器
(3)において信号(2a ) 、 (2b )の不一
致が検出された場合に(1、いずれか一方の信号が正常
である確率が大きいのにかかわらず、どちらの信号が正
常であるが全確認する手段がないため、これを人間が判
断するか、又は信号(2a、)、(2b)を共に棄てる
かしなければならぬという欠点があった。
Comparator (3) detects this coincidence, and if they match, signals (2a) and (2b) are determined to be normal, and if they do not match, it is determined to be abnormal, and both signals (2a) and (2b) are determined to be normal. The conventional input data processing device whose use would be prohibited operates as described above, and when a mismatch between the signals (2a) and (2b) is detected in the comparator (3), (1) Even though there is a high probability that the signal is normal, there is no way to fully confirm which signal is normal, so either humans should judge this, or both signals (2a,) and (2b) should be discarded. There was a drawback that it had to be done.

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、信号(2a)、(2b)の間に差
異を生じた場合は、いずれの信号が正常であるかを自動
的に判定し、正常な信号をこれら信号全入力すべきシス
テムに供給する入力データ処理装置;4 ’、(提供す
ることを目的として゛いる。
This invention was made to eliminate the drawbacks of the conventional ones as described above, and when a difference occurs between signals (2a) and (2b), it is automatically determined which signal is normal. The purpose of the present invention is to provide an input data processing device;

以下この発明の実施例を図面について説明する。Embodiments of the present invention will be described below with reference to the drawings.

第2図(ハ)」、この発明の一実施例を示すブロック図
で、第1図と同一?ご1号は同−又は相当部分全示し、
(41ハ(42)はぞれぞれディジタルアナログ変(興
器(以下1)ACと略記する)、(51)、(5幻はそ
れぞれ比軸器、−(4a、)、(4b)はぞれぞれiθ
流アナログ電圧である。
Fig. 2 (c) is a block diagram showing an embodiment of the present invention, and is it the same as Fig. 1? No. 1 shows the same or the corresponding part in full,
(41c and 42 are respectively digital analog transformers (hereinafter abbreviated as 1 AC), (51), (5gens are ratio scalers, -(4a,) and (4b) are respectively each iθ
current analog voltage.

直流アナログ′…、圧(1a)f ADC(21)、D
AC(41,) で処理した直流アナログ電圧(4a)
はもとの直流アナログ電圧(1a)と等しくなる筈であ
るっ したがって比較器(51)の比較によ5 (la
)と(4a)が許容誤差範囲内で一致していることを検
出すれば、変換器けり、ADC(21)は正常に動作し
ていること全確認することができるっ同様に、(1b)
と(4b)が許容誤差範囲内で一致していること全検出
すれば、変換器θ2、ADC<、22)は正常に動作し
ていることを確認することができる。
DC analog '..., pressure (1a) f ADC (21), D
DC analog voltage (4a) processed by AC (41,)
should be equal to the original DC analog voltage (1a). Therefore, by comparison with the comparator (51), 5 (la
) and (4a) match within the tolerance range, it is possible to confirm that the converter and ADC (21) are operating normally.Similarly, (1b)
If it is completely detected that (4b) and (4b) match within the allowable error range, it can be confirmed that the converter θ2, ADC<, 22) is operating normally.

第3図はこの発明による入力データの切換えを示す接続
図で、第2図と同一符号は同一部分を示し、(3−a)
は比較器(3)の出力が2人力不一致を示すとき閉接さ
れる各接点、(3−b)は比較器(3;の出力が2人カ
一致を示すときに閉接される各接点、(51−b)は比
軟器(5υが2人カ一致を示すときに閉接される接点、
(52−b)は比較器(!j2)が2人カ一致を示すと
きに閉接される接点である。
FIG. 3 is a connection diagram showing switching of input data according to the present invention, where the same reference numerals as in FIG. 2 indicate the same parts, and (3-a)
(3-b) is each contact that is closed when the output of the comparator (3) indicates a disagreement between the two operators, and (3-b) is each contact that is closed when the output of the comparator (3) indicates a match between the two operators. , (51-b) is a contact point that is closed when 5υ indicates a match between two people,
(52-b) is a contact that is closed when the comparator (!j2) indicates a match between the two.

比較器(3)が2人カ一致を示しているときは、信号(
2a)、 (2b)ともに正常な信号でめるので信号(
2a)に接点(3−り全経てAシステム(61)に供給
され、信号(2b)は接点(3−b)k経てBシステム
(6りに供給される。比較器(3)が2人力不一致を示
すと@は、信号(2a)、(2b)のうちのいずれか一
方又は双方が外宮信号であること治:;(j味するので
接改(3−b)6ヨ開放きれ、接点(3−a)がrll
接さJξ私、このとき、比較器(51)が2人カ一致G
二示し−こあ・れば、信号(2+りが正常である0と?
意味し、信号(2a)が接点(3−a)、接点(51−
b)’i経てBシステム(li2)に供給され、史に接
点(:3−a)k 酵てAシステム((iυに供給され
るっ反対に、比V、器(!姿が2人カ〜致を示しておれ
ば、信号(2b)が止′帛であることを意味し、信号(
2b)が接点(3−aL (52−10を経てAシステ
ム(61)に供給され、更に接点(3−a)’;c経て
Bシステム(62)に伊、給される。信号(,2a)も
信号(2b)も共に異常であって、かつ信号(2a)が
信号(2b)と一致してないときは接点(51−b)、
(乏j2−b)が共に開放されていて、Aシステム(f
jl)へもBシステム(62)へも信号は入力されない
、上記実施例ではAシステム(Jil)及びBシステム
(02)のいずれかの入力信号の異常全自動的V(、判
Mし−C1正常な人力信号を各システムに供給できるよ
うにした入力データ処理装置について説明したが、2系
列で相互監視金している装置に対しては、いずれもこの
発明の装置’i”i”e適用することによってシステム
停止の時間全減少することができるっ以上のようにこの
発明eζよれに、2重系間の11〕互監視機能に自己監
視機能を付方[]シたことにより、人間の判断に頼らず
に、正常のデータ音システムに(+仁給することができ
るため、入力データの異常時にシステム停止を必委とす
る時間を短縮することができるっ
When the comparator (3) indicates a match between the two persons, the signal (
Since both 2a) and (2b) are normal signals, the signal (
The signal (2b) is supplied to the A system (61) through the contact (3-b) to the contact (3-b), and the signal (2b) is supplied to the B system (61) through the contact (3-b). If a discrepancy is indicated, @ indicates that one or both of signals (2a) and (2b) are Geku signals. (3-a) is rll
At this time, the comparator (51) matches G
If it shows 2, then the signal (2+ is normal and 0?
This means that the signal (2a) is the contact (3-a), the contact (51-
b) It is supplied to the B system (li2) through 'i, and it contacts the history (:3-a)k. If it shows ~, it means that the signal (2b) is a stop, and the signal (2b) is a stop sign.
2b) is supplied to the A system (61) via the contact (3-aL (52-10), and is further supplied to the B system (62) via the contact (3-a)';c. ) and signal (2b) are both abnormal, and when signal (2a) does not match signal (2b), contact (51-b),
(f j2-b) are both open and the A system (f
In the above embodiment, no signal is input to either the A system (Jil) or the B system (62). Although we have described an input data processing device that can supply normal human input signals to each system, the device of this invention can be applied to any device that performs mutual monitoring in two systems. By adding a self-monitoring function to the 11] mutual monitoring function between dual systems, this invention can reduce the total system stoppage time. Since it is possible to feed normal data sound systems without relying on judgment, it is possible to reduce the time required to stop the system when input data is abnormal.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の装置を示すブロック図、第2図はこの発
明の一実施例を示すブロック図、第3図はこの発明にお
ける入力データの切換を示す接続図である。 (Ill 、 (12・・・それぞれ変換器、(21J
 、 (22)・・・それぞれADC、+31・・・比
較器、(41,1、(42)・・それぞれDAC。 (bυ、 (gl)・・・それぞれ比fj、器。 尚、各図中同一符号は同−又は相当部分を示す。 代理人 大岩増雄
FIG. 1 is a block diagram showing a conventional device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a connection diagram showing switching of input data in the present invention. (Ill, (12...respectively converter, (21J
, (22)...ADC respectively, +31...Comparator, (41, 1, (42)...Respectively DAC. (bυ, (gl)...Respectively ratio fj, device. Note that in each figure The same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] 物理量を表す信号全入力してその人カイ3号の振幅を表
すアナログ電圧値を出力する第1の変換器と、この第1
の変換器の入力信号と同一の信号を入力してその入力信
号の振幅を表すアナログ電圧値を出力する第2の変換器
と、上記第1の変換器の出力のアナログ′山:圧1直全
入力して入力アナログ′電圧値を表すディジタル信号を
出力するaへ1のアナログディジタル変換器と、この第
1のアナログディジタル変換器の出力全人力して入力し
たディジタル信号の衣すアナログ′電圧値を出力する第
1のディジクルアナログ変成器と、上記第2の変換);
にの出力のアナログ電圧値全人力して入力アナログ′1
1L圧fi/j k表すディジタル1を号を出力する第
2のアナログディジタル変換器と、この第2のアナログ
ディジタル変換器の出力を人力して入力したディジタル
信号の表すアナログ′電圧値を出力する第2のディジタ
ルアナログ変換器と、上記第1の変(灸器の出力と上記
第1のディジタルアナログ変換器の出力と全比較する第
1の比較器と、−上記第2の変換?:’6の出力と上記
第2のディジタルアナログ変換器の出力とを比較する第
2の比較器と、上記第1のアナログディジタル変換器の
出力と上nT2第2のアナログディジクル変換器の出力
と全比較する第3の比較器と全備えた人力データ処理装
置。
a first converter that inputs all signals representing physical quantities and outputs an analog voltage value representing the amplitude of the human chi No. 3;
a second converter inputting the same signal as the input signal of the converter and outputting an analog voltage value representing the amplitude of the input signal; The first analog-to-digital converter outputs a digital signal representing the input analog voltage value, and the output of this first analog-to-digital converter outputs the analog voltage corresponding to the input digital signal. a first digital analog transformer outputting a value; and the second conversion);
The output analog voltage value of the input analog '1
A second analog-to-digital converter outputs a digital 1 representing 1L voltage fi/jk, and the output of the second analog-to-digital converter is manually input to output an analog voltage value represented by the input digital signal. a second digital-to-analog converter; a first comparator for fully comparing the output of the first converter (moxibustion device) with the output of the first digital-to-analog converter; -the second conversion?:' a second comparator that compares the output of the first analog-to-digital converter with the output of the second digital-to-digital converter; A third comparator for comparison and a complete manual data processing device.
JP58112183A 1983-06-20 1983-06-20 Input data processor Pending JPS603001A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58112183A JPS603001A (en) 1983-06-20 1983-06-20 Input data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58112183A JPS603001A (en) 1983-06-20 1983-06-20 Input data processor

Publications (1)

Publication Number Publication Date
JPS603001A true JPS603001A (en) 1985-01-09

Family

ID=14580329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58112183A Pending JPS603001A (en) 1983-06-20 1983-06-20 Input data processor

Country Status (1)

Country Link
JP (1) JPS603001A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03286340A (en) * 1990-04-03 1991-12-17 Japan Electron Control Syst Co Ltd Diagnostic device for cpu abnormality
JP2011107807A (en) * 2009-11-13 2011-06-02 Hitachi Ltd Process control device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03286340A (en) * 1990-04-03 1991-12-17 Japan Electron Control Syst Co Ltd Diagnostic device for cpu abnormality
JP2011107807A (en) * 2009-11-13 2011-06-02 Hitachi Ltd Process control device

Similar Documents

Publication Publication Date Title
WO1997050170A9 (en) Independent load sharing of ac power systems connected in parallel
EP0908001A1 (en) Independent load sharing of ac power systems connected in parallel
JPS603001A (en) Input data processor
JPH04229396A (en) Apparatus for generating current corresponding to supplied quantity
JPS5827202A (en) Digital controlling device
JPS60191327A (en) Analog-to-digital converter
JPS6095329A (en) Analog input device
JPS6138366Y2 (en)
JP3724261B2 (en) Abnormality monitoring device for analog input part of digital protective relay
JPH08101235A (en) Method for digital system for measuring ac voltage,ac current and phase angle of measuring signal and measuring device
JPH11178219A (en) Battery monitoring unit
JPH04266A (en) Direct current controller of rectification device
JPH01292265A (en) Input voltage detection circuit
JPS5740659A (en) Testing burden setting device for current transformer
JPS58101519A (en) Failure detector for analog-to-digital converter
JP2000155614A (en) Fault detection system
JPH03128626A (en) Parallel operation controller for voltage instantaneous value control type inverter
Wayne Finding the Needle in a Haystack
JPS61280577A (en) Digital type frequency detecting method
JPS6343926B2 (en)
JPH02159824A (en) Inspection device for digital/analog converter
JPS58207871A (en) Full wave rectifying circuit
JPH0729934U (en) Analog signal generator
JPS6258209B2 (en)
JPH03143220A (en) Digital type protective controller