JPS6343926B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a level conversion device for converting the level of information input to a ternary information processing circuit or the like.

In a fail-safe ternary logic circuit that processes an input signal containing binary information "1" and "0" and failure information "ψ", generally, the input signal corresponds to the binary information "1" and "0" in the input signal, respectively. The relationship between each electrical level and the electrical level corresponding to the failure information "ψ" is "0", "ψ", "1" or "1", "ψ", "0".
One of the conditions is that the electrical level corresponding to the failure information "ψ" is between the electrical levels corresponding to the binary information "1" and "0".

However, the output signals of various sensors used in object detectors, fire detectors, vehicle detectors, etc.
Generally, failure information “ψ” and binary information “1” “0”
The relationship between each electrical level that individually corresponds to "ψ", "1", "0" or "ψ", "0", "1"
As in the order, the electrical level corresponding to the failure information "ψ" is outside the electrical level corresponding to the binary information "1" and "0".

That is, for example, a sensor that outputs a voltage corresponding to a change in impedance has an output voltage V ₀
When changes positively with respect to the reference value Vs (Vs + △
Vs), and when the output voltage changes negatively (Vs−△Vs), and when the output voltage changes positively, (Vs+△
When Vs) is set to binary information “1”, the reference value Vs becomes 2.
When the value information becomes “0” and the output voltage V ₀ is zero, the sensor failure information becomes “ψ”, so the output voltage
If the order of the levels of V ₀ is from low to high, “ψ”,
“0”, “1”, and “1” in the highest order,
"0" and "ψ", and the electrical level corresponding to the failure information "ψ" is outside the electrical level corresponding to the binary information "1" and "0". In addition, in the sensor, when the output voltage changes negatively, (Vs
−△Vs) is set to binary information “1”, the reference value Vs
becomes binary information “0”, and when the output voltage V ₀ is zero, it becomes failure information “ψ”, and the electrical level corresponding to failure information “ψ” corresponds to binary information “1” and “0”. It becomes outside the electrical level.

In this way, sensors in which the electrical level corresponding to the failure information "ψ" is outside the electrical level corresponding to the binary information "1" and "0" include not only sensors that utilize changes in impedance. Sensors that use ultrasonic waves or light beams, train detectors that use railway track circuits, and even sensors that apply a bias voltage Vv to the output signal and use this voltage Vv as an electrical level that corresponds to the failure information "ψ". be.

As described above, the above-described fail-safe ternary logic circuit processes ternary information in which the electrical level corresponding to the failure information "ψ" is outside the electrical level corresponding to the binary information "1" and "0". To do this, it is necessary to convert the order of the electrical levels of the three-value information output from the sensor.

The present invention has been made in view of the above points, and an object of the present invention is to provide a fail-safe level conversion device that can reliably convert the order of electrical levels of input ternary information using a simple device. do.

The embodiments shown in the drawings will be described below.

In FIG. 1, 1 is an input terminal for three-value information output from a sensor (not shown) or the like. Said 3
In this example, the value information is 0 for the voltage corresponding to the failure information “ψ”, V ₁ for the voltage corresponding to the binary information “0”,
Assume that the voltage corresponding to binary information "1" is _V2 , which is higher than the voltage _V1 . 2 is a first generating circuit that outputs an alternating current signal when the voltage of the input signal is V ₂ or higher; 3 is a first generating circuit that outputs an AC signal when the voltage of the input signal is V ₁ and the voltage V ₂
A second generator circuit 4 outputs an AC signal when V′ ₀ is lower, a first rectifier circuit 4 rectifies the output signal of the first generator circuit 2 and outputs a positive DC signal, 5
6 is a second rectifier circuit that rectifies the output signal of the second generation circuit 3 and outputs a negative DC signal; 6 is a rectifier circuit 4;
This is a synthesis circuit that synthesizes the output signals of 5.

In this example, the first generation circuit 2 includes three directly connected transistors T ₁ , T ₂ , T ₃ and six resistors R ₁ ,
_This is _a threshold _{oscillation circuit} using R ₂ . A voltage V ₂ is applied to _the terminal ₇ , and each resistor R ₁ , R ₂ . It is set. The basic configuration of such a circuit is
For example, it is described in Japanese Patent Publication No. 45-29054.

In this example, the second generating circuit 3 is
The window comparator proposed in No. 147589,
Three directly connected transistors t ₁ , t ₂ , t ₃ and 10
resistors r ₁ , r ₂ … r ₁₀ and Zener diode ZD
The collectors of the transistors t ₁ , t ₂ , and t ₃ are commonly connected to the input terminal 1, and the emitters are connected to the terminal 8. A voltage V ₁ is applied to _the terminal ₈ , and each resistor r _{1 ,} r ₂ . It is set to the value to be output. Said
V′ ₁ may be a value that does not overlap the input signal area where the first generation circuit 2 outputs an AC signal and the input signal area where the second generation circuit 3 outputs an AC signal, and in this example, It is higher than V ₁ and lower than V ₂ . This voltage V′ ₁ can be arbitrarily set by adjusting the values of resistors r ₃ and r ₁₀ .

The first rectifier circuit 4 includes a voltage doubler rectifier circuit using diodes D ₁ , D ₂ and capacitors C ₁ , C ₂ , a switching transistor TR, and a load resistor RE. Also, diode
It consists of d ₁ , d ₂ , capacitors c ₁ , C ₂ , transistor tr, and resistor re. Such a circuit is described, for example, in Japanese Patent Publication No. 51-38211.

In this example, the synthesis circuit 6 is a so-called wired-OR circuit in which the output terminals of the rectifier circuits 4 and 5 are simply connected.

In this device, the output signal of the combining circuit 6 is
When the input signal to the terminal 1 is equal to or higher than the voltage V ₂ , the first generator circuit 2 operates but the second generator circuit 3 does not operate. Therefore, the AC signal output from the first generator circuit 2 is It becomes a positive DC signal (+V) rectified by the rectifier circuit 4, and when the voltage is between V ₁ and V' ₁ , the second generator circuit 3 operates but the first generator circuit 2 does not operate, so the second generator The AC signal output from the circuit 3 is rectified by the second rectifier circuit 5 to become a negative DC signal (-V), and when the voltage is between V' ₁ and V ₂ , and when it is lower than the voltage V ₁ , both generation Since both circuits 2 and 3 do not operate, it is zero (0).

That is, in the above-mentioned device, if the input signal to the terminal 1 changes as shown in FIG. 2A, the output signal of the first rectifier circuit 4 becomes the signal shown in FIG. Since the output signal becomes the signal shown in FIG. 2C, the output signal of the combining circuit 6 becomes the second signal.
The signal shown in Figure D is obtained. Therefore, binary information “1”
The order of each electrical level corresponding to “0” and failure information “ψ” is “1”, “0”, and “ψ” in descending order on the input side to this device, but on the output side, it is “1”. “ψ” becomes “0”.

FIG. 3 shows a level conversion device in which the AC signal generated by the AC signal generation circuit 10 is superimposed on the input signal to the terminal 1 and then supplied to the first and second generation circuits 2' and 3'. An example is shown. The first and second generating circuits 2' and 3' used in this device can be switching circuits such as Schmitt circuits, and the first and second rectifying circuits 4' and 5' and the combining circuit 6' are The circuit used in the device of FIG. 1 can be used.

In this device, first and second generating circuits 2',
Let the threshold voltages for the input of 3' be V ₂ and V ₁ , respectively,
Assuming that the peak value of the AC signal is VAc, and that the signal shown in FIG. 2A is input to terminal 1,
The input signals to the first and second generation circuits 2' and 3' are:
As shown in FIG. 4A, the AC signal VAc generated by the AC signal generator 10 is superimposed on the input signal V to the terminal 1. Therefore, the input signal V
When the level of is (V ₂ ±VAc), the first generating circuit 2' outputs the AC signal shown in FIG. 4B, and the first
When the generation circuit reaches a level V ₁ ±VAc lower than the level at which the AC signal is generated, the second generation circuit 3' outputs the AC signal shown in FIG. 4C, and as a result, the AC signals shown in FIGS. 4B and C are generated. are individually rectified by rectifying circuits 4' and 5', and each output signal is combined by combining circuit 6', we get
The output signal of the combining circuit 6' becomes the signal shown in FIG. 4D. This composite signal has an input signal that is fault information (V
=0), it becomes ±0, and the failure information ψ becomes a signal that exists between the binary information “1” and “0”.

In the embodiments of FIGS. 1 and 4, the minimum essential function is that the second generating circuits 3, 3' have a similar function to a window comparator. Otherwise, for example, in the device shown in FIG. 1, if the second generating circuit 3 generates an output "0" (-V) when the input voltage is above V ₁ , both 3 and 2 will output "0" (-V) when the input voltage is above V ₂ . 1" (+V) and "0" (-V), and the combined output produces the same "zero" as the fault signal ψ.

In this device, the output signal of the combining circuit 6 is
Similarly to the configuration shown in Fig. 1, if the voltage of the input signal to terminal 1 is V ₂ , the first generating circuit 2' operates, resulting in a positive DC signal, and if the input signal is V ₁ , the second
Since the generating circuit 3' operates, it becomes a negative DC signal,
At other times it is zero. In addition, due to a failure, the output of the information transmission system (including the input signal) of either the first or second generating circuit 2', 3', i.e., 2', 3'
If the AC output of is "zero" or the outputs of rectifier circuits 4' and 5' are "zero", the output signal of combining circuit 6 will be zero. Therefore, in this device as well, if the electrical levels corresponding to each information “1”, “0”, and “ψ” are shown in descending order, the input side of this device is “1”.
“0” “ψ”, but “1” “ψ” on the output side
It becomes “0”.

The present invention is not limited to the above-mentioned embodiment, and for example, the electrical levels corresponding to the binary information "1""0" and the failure information "ψ" are set in descending order of "0", "ψ", "1". The conversion may be performed in the following order.
It can also be used as a general level conversion device that converts the order of the electrical levels of the input signal so that the electrical level corresponding to the failure information "ψ" in the output signal of the synthesis circuit becomes a value other than zero. It's okay.

As described above, the present invention includes two generating means that output an AC signal according to the electrical level of an input signal, and rectifying the AC output of each generating means individually to generate DC signals having different electrical levels. generates 2
Since the present invention is composed of three rectifying means and a means for synthesizing the output signals of the respective rectifying means, the order of input ternary information can be reliably converted, and the apparatus is simple. Furthermore, since the electrical levels of the output signals of the respective rectifying means are different from each other, if the generating means and/or the rectifying means fail, the electrical level of the output signal of the combining means becomes the average value of the output signals of the respective rectifying means. It can be used as a fail-safe level conversion device.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of the electric circuit of the level converter, Fig. 2 is an operation explanatory diagram, Fig. 3 is a block diagram of an electric circuit showing another example, and Fig. 4 is a diagram of the apparatus of Fig. 3. It is an operation explanatory diagram. 1: input terminal, 2, 2': first generation circuit, 3,
3': second generation circuit, 4, 5: rectifier circuit, 6: synthesis circuit.

Claims (1)

[Claims] 1 a first generating circuit 2, 2' that outputs an alternating current signal when the electrical level of the input signal is a first value; a second generating circuit 3, 3' which sometimes outputs an alternating current signal and does not output an alternating current signal when the first generating circuit 2, 2' outputs an alternating current signal; and an output signal of the first generating circuit 2, 2'. a first rectifier circuit 4, 4' that rectifies the signal and outputs a positive first DC signal;
second rectifier circuits 5, 5' that rectify the output signals of the generator circuits 3, 3' and output a negative second DC signal having an electrical level different from the first DC signal; and first and second rectifiers. A level conversion device comprising synthesis circuits 6 and 6' for synthesizing respective output signals of circuits 4, 4', 5 and 5'.