GB2095439A

GB2095439A - Twin transformer inverter

Info

Publication number: GB2095439A
Application number: GB8121597A
Authority: GB
Original assignee: Singer Co
Current assignee: Singer Co
Priority date: 1980-08-18
Filing date: 1981-07-14
Publication date: 1982-09-29
Also published as: SE8104843L; SE452826B; NO159568B; IL63326A0; AU542899B2; IT1139128B; IT8123513A0; DE3131729A1; FR2488752B1; FR2488752A1; NO159568C; IL63326A; CA1179015A; AU7369581A; NO812682L; GB2095439B; JPS5755777A

Abstract

A power inverter utilizing twin transformers 56,57 converts an unregulated DC input voltage on lines 43,60 to a regulated DC output voltage while providing input-to-output isolation. A pulse width modulation control unit 16, dependent on output voltage and current, controls switching transistors 40,46 to feed the twin transformers, said to reduce output ripple. The secondary voltages are combined and smoothed to provide a stabilised output. <IMAGE>

Description

SPECIFICATION Twin transformer inverter Description The present invention relates to power supply regulators and more particularly to a DC regulator.

Frequently, a DC output voltage requires regulation due to the fact that it is subject to overvoltage and undervoltage transients of relatively high value.

Circuits have been developed to convert an unregulated DC input voltage to a regulated DC output voltage while providing input-to-output isolation.

These circuits are well known to those in the art and include push-pull converters, boost-buck regulators, and bridge inverters. The prior art circuits suffer from several disadvantages. In general, large voltage excursions of the input create large voltage and current stress levels in the semiconductors used in the regulator circuits. Further, large currents are experienced by filter capacitors used in such regulator circuits. Historically, this problem has been handled in two ways. The first involves the use of costly semiconductors or, in some case, parallel connected semiconductors have been used. In an alternative solution, input power is preconditioned, thereby increasing cost and complexity of the circuit while decreasing the efficiency thereof.

The present twin transformer inverter alleviates many of the problems previously encountered. A control unit provides a pulse width modulated square wave having a duty cycle which is a function of output voltage. The square wave is transformer coupled to power switching transistors which operate 180 degrees out of phase with each other. By filtering the output of the power switches, a regulated DC output voltage is derived.

As will be explained hereinafter, by interconnecting transformers in a twin configuration, output ripple current is significantly reduced. Further, there is a marked reduction in voltage and current stress on semiconductor devices in the circuit, as compared with those in conventional regulators. Previous regulation techniques produced ripple currents that were equal to the output load current and caused the output filter to be excessively large. The present circuit reduces the ripple current to 1/3 of the output load current and, consequently, one-third of the filtering is all that is required. Further, the use of twin connected transformers provides for a simple and effective paralleling of the switching transistors and output rectifiers, thereby reducing the electrical stress on each.

The above-mentioned objects and advantages of the present invention will be more clearly understood when considered in conjunction with the accompanying drawings, in which: Figure lisa basic block diagram of the present invention.

Figure 2 is an electrical schematic diagram of the present invention illustrating a pulse width modulation control unit in block form.

Figure 3 is a logic circuit illustrating the pulse width modulation control unit in detail.

Figure 4 is a composite timing diagram showing signal flow at various points of the inventive inverter.

Referring to the figures in detail, and Figure 1 in particular, a basic block diagram of the present inverter is illustrated. A pulse width modulation control unit 16 provides a pulse width modulated (PWM) square wave having a duty cycle which is a function of output voltage derived at terminal 12. A transformer 18 couples the PWM square wave to power switches 20 which operate upon the unregulated DC input voltage indicated at 10. The output of the power switches is fed to a filter 22 which accomplishes final DC voltage regulation. A feedback connection between the output voltage and the PWM control unit 16 occurs along lead 14.

Figure 2 illustrates the system in greater detail.

The PWM control unit 16 briefly mentioned in connection with Figure 1 is seen to include an input 24 connected to a B+ source. A current sense line 26 furnishes an additional input to the control unit and senses current at the output of the inverter, as will be explained hereinafter. Similarly, lead 27 provides a further input to the control unit 16 and serves to sense voltage at the output of the inverter. A common return for the control unit 16 and the inverter output occurs along return lead 28.

The primary winding of transformer 18 is connected to the control unit output and includes upper and lower terminals 30 and 34, respectively, as well as a center tap 32. The secondary winding of the transformer includes upper and lower terminals 36 and 48, respectively, along with a center tap 42 which is connected to a return potential of the input voltage, along connecting lead 43. The PWM square waves from the control unit 16 are transformer coupled through transformer 18 to a common emitter power switch configuration including transistors 40 and 46. The emitters 45 and 44, of transistors 40 and 46, respectively, are connected to the center tap 42 of transformer 18 which is connected to the return potential of the input voltage.

The base 38 of transistor 40 is connected to the upper secondary winding terminal 36 while the base 50 of transistor 46 is connected to the lower terminal 48 of the secondary winding of transformer 18 thereby completing the input to the power switching transistors. The output of the power switching transistors is coupled to the primary windings of twin connected transformers 56 and 57. Specifically, the collector 52 of transistor 40 is connected to the upperterminal of transformer primary winding 54 while the lower terminal 59 of the primary winding 54 is connected to the positive potential of the input voltage, along connecting lead 60. The input voltage is stabilized by capacitor 64 appearing across the input.It will be noted that the lower terminal of primary winding 54 (transformer 56) is directly connected to the upper terminal of primary winding 61 (transformer 57) so that the previously mentioned positive potential is likewise provided the upper terminal of primary winding 61. The collector of transistor 46 is connected to the lower terminal of primary winding 61,via connecting lead 58. In operation of the circuit, the PWM square waves from transformer 18 are fed to the power switching transistors 40 and 46 which operate as saturated switches 180 degrees out of phase with each other.

While transistor 40 is conducting, current is built up in transformer 56 and when transistor 40 is turned off, transistor 46 turns on and operates 180 degrees out of phase with transistor 40. The upper terminal of the secondary winding 66 (transformer 56) is connected to the anode of a diode 68 while the lower terminal of the secondary winding 72 (transformer 57) is connected to the anode of diode 74. The cathodes of the diodes 68 and 74 are connected in parallel to lead 76. With transistor 40 conducting, polarity is such that diode 68 is reversed biased.

When transistor 40 turns off, diode 68 becomes forward biased and load current is supplied until transistor 40 turns on again. Operation of diode 74 similarly utilizes the switching of transistor 46 and coupling through transformer 57. However, diode 74 operates 180 degrees out of phase with diode 68.

The cathode of diode 68 is connected, via lead 76, as the positive potential point 77 for the output voltage. The junction point 70 between the lower terminal of secondary winding 66 (transformer 56) and the upper terminal of secondary winding 72 (transformer 57) is connected as a common terminal 28 for the output voltage. In order to sense current flowing through the output section of the inverter, a resistor 80 is connected between the common terminal 28 and the junction point 70 of the secon darywindings of transformers 56 and 57. The previously mentioned current sense line 26 performs its current sensing function by monitoring a small voltage across the resistor 80 thereby providing overcurrent protection. Capacitors 82 and 84 are connected across the output voltage terminals to filter the output voltage thus providing a well regulated supply.

PWM control unit Referring now to Figure 3, the PWM control unit 16 is seen to include an operational amplifier 86 which serves as an error voltage amplifier. A first input to the amplifier is provided along lead 88 which is connected to the B+ supply at 24, via resistor 90. The negative potential of the output voltage, along lead 28, is connected in parallel with the input 88 of amplifier 86, Zenor diode 94. The second input 96 to amplifier 86 carries the positive potential of the output voltage along lead 77. The output 98 of amplifier 86 produces an error signal between the reference B+ voltage and the output voltage.A second operational amplifier 100, serving as a current error amplifier has a first input connected along lead 104 to the common terminal 28 of the output voltage while a second input, appearing along lead 26, carried the output current flowing through resistor 80 (Figure 2) so that amplifier 100 is a current sensing device for achieving overcurrent protection. The output of amplifier 100 is connected, via lead 102, to the output of the amplifier 86 at a node 106 which, in turn, is connected as a first input 108 to comparator 110. The comparator is a high gain operational amplifier.In order to understand the nature of a second input 115 to comparator 110, reference is made to oscillator 112 which generates clock signals at the output thereof which are fed to integrator 114 which integrates the trigger pulse signals to form a triangular wave as shown at the output of integrator 114. The superposition of the DC level input to the comparator 110 and the triangular signal input to the comparator is illustrated along lead 126 at the output of comparator 110. A pulse width modulated signal occurs and as shown along lead 126, it has zero crossovers at the point of intersection between the triangular and DC signals.

The PWM signal on lead 126 is fed in parallel to NAND gates 120 and 124. A second input 118 to NAND gate 120 is derived as an output from flip-flop 117 while a complementary output 122 from the flip-flop 117 drives a second input of NAND gate 124.

The purpose of flip-flop 117 is to enable gates 120 and 124 in synchronism with the clock input pulses to flip-flop 117 as they occur along oscillator output lead 116. The gates 120 and 124 are enabled 180 degrees out of phase with each other. This difference of phase conduction is conveyed at respective output terminals 128 and 129 to the upper and lower primary winding terminals 30 and 34. A reference voltage, namely B+, is connected to the center tap 32 of the primary winding of transformer 56 via a semiconductor current source 130. The PWM pulses appearing at the primary winding of transformer 56 are coupled to the subsequent inverter circuitry as previously explained in connection with Figure 2.

Figure 4 is a composite timing diagram showing signal waveforms at various points in the circuitry of the inverter, as indicated on the figure.

It should be understood that the invention is not limited to the exact details of construction shown and described herein for obvious modifications will occur to persons skilled in the art.

Amendments to claims filed on 22 January 1982 Claims 6 to 10 and 12 deleted.

Claims

1. A power inverter for providing a DC regulated output voltage, the inverter comprising: means connected at the input thereof to the output voltage for generating apulse signal having a duty cycle which is a function of the output voltage; power switching means biased by an unregulated DC input voltage; means connecting an output of the generating means to an input of the power switching means for driving the switching means; and means for filtering an output of the switching means and producing the regulated output voltage.

2. The subject matter set forth in Claim 1 wherein the generating means comprises a triangular wave generator and means for comparing the amplitude of the triangular wave from the generating means with the amplitude of the output voltage and produc ing a square wave as a result thereof.

3. The subject matter set forth in Claim 1 wherein the power switching means comprises first and second transistors having inputs and outputs; first and second transformer primary windings having å common terminal and further connected at free terminals thereof to the outputs of the transistors; means for connecting the unregulated DC input voltage to the common terminal of the windings; secondary windings of the first and second transformers having a common terminal; and rectifier means connected in circuit to the free terminals of the secondary windings.

4. The subject matter set forth in Claim 2 wherein the power switching means comprises: first and second transistors each having first and second output terminals; means interconnecting the first output terminals of the transistors; first and second transformer primary windings each of which have first and second terminals; means connecting the first terminals of the windings; means connecting each of the second terminals of the windings to a respective second output terminal of the transistors; means connecting the unregulated DC input voltage to the connected first terminals of the windings; first and second transformer secondary windings, each of which have first and second terminals; means interconnecting the first terminal of each secondary winding; and a plurality of rectifier means each connected to a respective second terminal of the secondary windings.

5. The subject matter set forth in Claim 3 wherein the filtering means is connected to outputs of the rectifier means.

6. In a power inverterfor providing a DC regulted output voltage and having a power switching means biased by an unregulated input voltage, an improved control means connected at an input thereof to the output voltage and at the output thereof to the power switching means for turning the latter on, the control means comprising: amplifier means connected at its inputs to a reference voltage and the output voltage, respectively, thereby generating a DC level which is a function of the output voltage; means for generating a triangular signal; and comparator means connected at respective inputs to the output of the amplifier means and an output of the generating means for producing a pulse width modulated signal having a duty cycle dependent upon the output voltage.

7. The subject matter set forth in Claim 6 together with gating means connected at respective inputs thereof to means for synchronizing the pulse width modulated signal with a clock signal.

8. The subject matter set forth in Claim 7 together with transformer means connected to the output of the gating means for coupling the pulse width modulated signal to the power switching means.

9. The subject matter set forth in Claim 8 together with transformer means connected to an output of the power switching means for coupling signals from the power switching means to mean for rectifying the coupled signals.

10. The subject matter set forth in Claim 9 together with means connected between an output of the rectifying means and the comparator means for sensing current flow therethrough in excess of a predetermined level and protecting the control unit from overcurrent damage.

11. A power inverter substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

12. A control means for use in a power inverter substantially as hereinbefore described with reference to and as shown in the accompanying drawings.