CA1179015A - Twin transformer inverter - Google Patents
Twin transformer inverterInfo
- Publication number
- CA1179015A CA1179015A CA000383549A CA383549A CA1179015A CA 1179015 A CA1179015 A CA 1179015A CA 000383549 A CA000383549 A CA 000383549A CA 383549 A CA383549 A CA 383549A CA 1179015 A CA1179015 A CA 1179015A
- Authority
- CA
- Canada
- Prior art keywords
- output
- input
- terminals
- output voltage
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
- H02M3/3376—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current
- H02M3/3378—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current in a push-pull configuration of the parallel type
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
Abstract
Title of the Invention: TWIN TRANSFORMER INVERTER
Inventors: Rudolph Boetticher and William Tombs ABSTRACT OF THE DISCLOSURE
A power inverter utilizing twin transformers converts an unregulated DC input voltage to a regulated DC output voltage while providing input-to-output isolation. The twin transformers are driven by a pulse width modulation control unit providing square waves having a duty cycle which is a function of output voltage. The square waves drive power switches, the outputs of which are filtered to provide the regulated DC output voltage.
Inventors: Rudolph Boetticher and William Tombs ABSTRACT OF THE DISCLOSURE
A power inverter utilizing twin transformers converts an unregulated DC input voltage to a regulated DC output voltage while providing input-to-output isolation. The twin transformers are driven by a pulse width modulation control unit providing square waves having a duty cycle which is a function of output voltage. The square waves drive power switches, the outputs of which are filtered to provide the regulated DC output voltage.
Description
~7~
FIELD OF TIIE INVENTION
The present invention relates to power supply regulators and more particularly to a DC regulator.
BRIEF DESCRIPTION OF ~HE PRIOR ART
Frequently, a DC output voltage requires regulation due to the fact that it is subject to overvoltage and undervoltage transients of relatively high value. Circuits have been developed to convert an unregulated DC input ~ voltage to a regulated DC output voltage while providing input-to-output isolation. These circuits are well known to those in the art and include push-pull converters, boost-buck regulators, and bridge inverters. The prior art circuits suffer from several disadvantages. In general, large voltage excursions of the input create large voltage and current lS stress leve;s in the semiconductor~s used in the regulator circuits. Further, large currents are experienced by ilter capacitors used in such regulator circuits. Historically, this problem has been handled in two ways. The flrst involves the use of costly semiconductors or, in some cases, parallel connected semiconductors have been used. In an alternative solution, input power is preconditioned, thereby increasing cost and complexity of the circuit while decreasing the efficiency thereof.
!, . . . .... . ... .... . .. .. .
I j BRIEF DESCRIPTION OF THE PRESENT IN~IENTION
The present twin transformer inverter alleviates many of the problems previously encountered. A control unit provides a pulse width modulated square wave having ,, ~
!.
FIELD OF TIIE INVENTION
The present invention relates to power supply regulators and more particularly to a DC regulator.
BRIEF DESCRIPTION OF ~HE PRIOR ART
Frequently, a DC output voltage requires regulation due to the fact that it is subject to overvoltage and undervoltage transients of relatively high value. Circuits have been developed to convert an unregulated DC input ~ voltage to a regulated DC output voltage while providing input-to-output isolation. These circuits are well known to those in the art and include push-pull converters, boost-buck regulators, and bridge inverters. The prior art circuits suffer from several disadvantages. In general, large voltage excursions of the input create large voltage and current lS stress leve;s in the semiconductor~s used in the regulator circuits. Further, large currents are experienced by ilter capacitors used in such regulator circuits. Historically, this problem has been handled in two ways. The flrst involves the use of costly semiconductors or, in some cases, parallel connected semiconductors have been used. In an alternative solution, input power is preconditioned, thereby increasing cost and complexity of the circuit while decreasing the efficiency thereof.
!, . . . .... . ... .... . .. .. .
I j BRIEF DESCRIPTION OF THE PRESENT IN~IENTION
The present twin transformer inverter alleviates many of the problems previously encountered. A control unit provides a pulse width modulated square wave having ,, ~
!.
- 2 - ~ I
3~5 i, .
a duty cycle ~hich is a ~unc~ion of output voltage. The square wave is transforrner coupled to power switching tran-sistors which operate 180 degrees out of phase with each ~ other. By filtering the outpu~ of the power switches, a regulated DC output voltage is derived.
As will be explained hereinafter, by interconnec-ting transformers in a twin configuration,~output ripple current ~i is significantly reduced. Further~ there is a marked reduction in voltage and current stress on semiconductor devices in the circuit, as compared with those in conventional !j ;
; regulators. Previous regulation techniques produced ripple currents that were equal to the output load current and ', caused the output filter to be excessiveIy large. The i present circuit reduces the ripple current to 1~3 of the 15, output load current and, consequently, one-third of the filtering is all that is required. Further, the use of twin connected transformers provides for a simple and effective paralleling of the switching transistors and I output rectifiers, thereby reducing the electrical stress 20on each.
,I The above-mentioned objects and advantages of the present invention will be more clearly understood when l considered in conjunction with the accompanying drawings, in which:
I BRIEF DESCRIPTION OF THE FIGURES
¦ FIG. ] is a basic block diagr~m of the present invention.
I
Il 3 !
~ 3~ ~
FIG. 2 is an electrical schematic diayram of the present invention illustrating a pulse width modulation control unit in block form~
` FIG, 3 is a logic circuit illus-trating the pulse width modulation control unit in detail.
FIG. 4 is a composite timing diagram showing signal flow at various points of the inventive inverter.
DETAILED DESCRIPTION OF THE IN~ENTION
Referring to the figures in detail, and FIG. 1 in particular, a basic block diagram of the present inverter is , .
:illustrated. A pulse width modulation control unit 16 provides a pulse width modulated (PWM) square wave having a duty cycle which is a funct1on of output voltage derived at terminal 12 A transformer 18 couples the PWM square wave to power switches 20 whlch operate upon the unregulated DC input voltage indicated at lOo The output of the power switches i9 fed to a filter 22 which accomplishes final DC
voltag~ regulation. A feedback connection between the output voltage and the PWM control unit 16 occurs along lead 14.
` FIG. 2 illustrates the system in greater detail.
The PWM control unit 16 briefly mentioned in connection i with FIG. l is seen to include an input 24 connected t.o I a B+ source. A current sense line 26 furnishes an additional Ii input to the control unit and senses current at the output of the inverter, as will be explained hereinafter. Similarly, j lead 27 provides a further input to the control unit 16 and serves to sense voltage at the output of the inverter.
I' A common return for the control unit 16 and the inVerter output occurs along retuxn lead 28~
The primary winding of transformer 18 is connected to the control unit output and includes upper and lower terminals 30 and 34, respectively, as well as a center tap 32. The secondary winding of the transformer includes upper and lower terminals 36 and 48, respec~ively, along with a center tap 42 which is connected to a return potential of the input voltage, along connecting lead 43. The PWM
square waves from the control unit 16 are transformer coupled through transformer 18 to a common emitter power switch configuration including transistors 40 and-46. The emitters 45 and 44, of transistors 40 and 46, respectively, are con-nected to the center tap 42 of transformer 18 which is connected to the return potential of the input voltage.
The base 38 of transistor 40 is connected to the upper secondary winding terminal 36 while the base 50 of tran-sistor 46 is connected to the lower terminal 48 of the ~ seconda~ry winding of transformer 18 thereby completing the input to the power switching transistors. The output of the power switching transistors is coupled to the primary windings of twin connected transformers 56 and 57. Specifically, the collector 52 of transistor 40 is connected to the upper jj terminal of transformer primary winding 54 while the lower terminal 59 of the primary winding 54 is connected to the ,` positive potential of the input voltage, along connecting lead 60. The input voltage is stabilized by capacitor 64 appearing across the input. It will be noted that the lower !~
i, I
~ 3~ ~
terminal of primary winding 54 (transformer 56) is directly connected to the upper -terminal of primary winding 61 (trans-former 57) so that the previously mentioned positive potential is likewise provided the upper terminal of primary winding 61.
The collector of transistor 46 is connected to the lower terminal of primary winding 61, via connecting lead 58.
In operation of the circuit, the PWM square waves from transformer 18 are fed to the power switching transistors 40 and 46 whlch operate as saturated switches 180 degrees out of phase with each other. While transistor 40 is con-ducting, current is built up in transformer 56 and when transistor 40 is turned of, transistor 46 turns on and operates 180 degrees out of phase with transistor 40. The upper terminal of the secondary winding 66 (transformer 56) is connected to the anode of a diode 68 while the lower terminal of the secondary winding 72 (transformer 57) is connected to the anode of diode 74. The cathodes of the ; diodes 68 and 74 are connected in parallel to lead 76.
With transistor 40 conducting, polarity is such that diode 68 is reversed biased. When transistor 40 turns off, diode 68 becomes forward biased and load current is supplied until transistor 40 turns on again. Operation of diode 74 similarly utilizes the switching of transistor 46 and coupling -throu~h ; transformer 57. However, diode 74 operates 180 degrees out of phase with diode 68.
The cathode of diode 68 is connected~ via lead 76, as the positive potential point 77 for the output voltage.
The junction point 70 between the lower terminal of secondary ~1 .
!!
i! - 6 -.~
~ ~ 7~
winding 66 (transformer 56) and the upper terminal of sccondary winding 72 (transformer 57) is connected as a common terminal 28 for the output voltage. In order to sense current flowing through the output section of the inverter, a resistor 80 is connected between the common terminal 28 and the junction point 70 of the secondary windings of transformers 56 and 57. The previously mentioned current sense line 26 performs its current sensing function by monitoring a small voltage across the resistor 80 thereby providing overcurrent protec-tion. Capacitors 82 and 84 are connected across the output voltage terminals to filter the output voltage thus providing a well regulated supply.
.~.
PWM CONTROL UN _ Referring now to FIG, 3, the PWM control unit 16 is seen to ;nclude an operational amplifier 86 which serves as an error voltage amplifier. A first input to the amplifier is provided along lead 88 which is connected to the B-~ supply at 24, via resistor 90. The negative potential of the output voltage, along lead 28, is connected in parallel with the input 88 of amplifier 86, via Zener diode 94. The second input 96 to amplifier 86 carries the positive potential of the output voltage along lead 77. The output 98 of amplifier 86 produces an error signal between the reference B+ voltage and the output voltage. A second operational amplifier 100, serving as a current error amplifier has a first input connected along lead 104 to the common terminal 28 of the output voltage while a second input, appearing ,i .
.. . .
,i !
! I 7 .1 . .
~7 ~ 3 along lcad 26, carries the output current flowing through ~ resistor 80 (FIG~ 2) so that amplifier 100 is a current ; sensing device for achieving overcurrent protection. The output of amplifier 100 is connected, via lead 102, to the output of the amplifier 86 at a node 106 which, in turn, is connected as a first input 108 to comparator 110. The comparator is a high gain operational amplifier. In order to understand the nature of a second input 115 to comparator 110, reference is made to oscillator 112 which generates clock signals at the output thereof which are fed to integrator 114 which integrates the trigger pulse signals to form a triangular wave as shown at the output of integrator 114.
The superposition of the DC level input to comparator 110 and the triangular signal input to the comparator is illustrated along lead 126 at the output of comparator 110.
A pulse width modulated signal occurs and as shown along lead 126, it has zero crossovers at the point of intersection between the triangular and DC signals. The PWM signal on ` lead 126 is fed in parallel to NAND gates 120 and 124.
A second input 118 to NAND gate 120 is derived as an output from flip-flop 117 while a complem~ntary output 122 from . the flip-flop 117 drives a second input of N~ND gate 12~. !
The purpose of flip-flop 117 is to enable gates 120 and ' 124 in synchronism with the clock input pulses to flip-flop 117 as they occur along oscillator output lead 116. The gates 120 and 124 are enabled 180 degrees out of phase with ~i each other. This difference of phase conduction is conveyed 1, at respective output terminals 128 and 129 to the upper li '' '' ~ 8 -_.
~L~'7~3~
and lower primary winding terminals 30 and 34. A reference voltage, namely B+, is connected to ~he center tap 3Z of the primary winding of transformer 56 via a semiconductor current source 130. The PWM pulses appearing at the primary winding of transformer 56 are coupled to the subsequent inverter circuitry as previously explained in connection with FIG. 2.
FIG. 4 is a composite timing diagram showing signal waveforms at various points in the circuitry of the inverter, as indicated on the Figure.
; It should be understood that the invention is not limited to the exact details of construction shown and described herein for obvious modifications will occur to persons skilled in the art.
- g _
a duty cycle ~hich is a ~unc~ion of output voltage. The square wave is transforrner coupled to power switching tran-sistors which operate 180 degrees out of phase with each ~ other. By filtering the outpu~ of the power switches, a regulated DC output voltage is derived.
As will be explained hereinafter, by interconnec-ting transformers in a twin configuration,~output ripple current ~i is significantly reduced. Further~ there is a marked reduction in voltage and current stress on semiconductor devices in the circuit, as compared with those in conventional !j ;
; regulators. Previous regulation techniques produced ripple currents that were equal to the output load current and ', caused the output filter to be excessiveIy large. The i present circuit reduces the ripple current to 1~3 of the 15, output load current and, consequently, one-third of the filtering is all that is required. Further, the use of twin connected transformers provides for a simple and effective paralleling of the switching transistors and I output rectifiers, thereby reducing the electrical stress 20on each.
,I The above-mentioned objects and advantages of the present invention will be more clearly understood when l considered in conjunction with the accompanying drawings, in which:
I BRIEF DESCRIPTION OF THE FIGURES
¦ FIG. ] is a basic block diagr~m of the present invention.
I
Il 3 !
~ 3~ ~
FIG. 2 is an electrical schematic diayram of the present invention illustrating a pulse width modulation control unit in block form~
` FIG, 3 is a logic circuit illus-trating the pulse width modulation control unit in detail.
FIG. 4 is a composite timing diagram showing signal flow at various points of the inventive inverter.
DETAILED DESCRIPTION OF THE IN~ENTION
Referring to the figures in detail, and FIG. 1 in particular, a basic block diagram of the present inverter is , .
:illustrated. A pulse width modulation control unit 16 provides a pulse width modulated (PWM) square wave having a duty cycle which is a funct1on of output voltage derived at terminal 12 A transformer 18 couples the PWM square wave to power switches 20 whlch operate upon the unregulated DC input voltage indicated at lOo The output of the power switches i9 fed to a filter 22 which accomplishes final DC
voltag~ regulation. A feedback connection between the output voltage and the PWM control unit 16 occurs along lead 14.
` FIG. 2 illustrates the system in greater detail.
The PWM control unit 16 briefly mentioned in connection i with FIG. l is seen to include an input 24 connected t.o I a B+ source. A current sense line 26 furnishes an additional Ii input to the control unit and senses current at the output of the inverter, as will be explained hereinafter. Similarly, j lead 27 provides a further input to the control unit 16 and serves to sense voltage at the output of the inverter.
I' A common return for the control unit 16 and the inVerter output occurs along retuxn lead 28~
The primary winding of transformer 18 is connected to the control unit output and includes upper and lower terminals 30 and 34, respectively, as well as a center tap 32. The secondary winding of the transformer includes upper and lower terminals 36 and 48, respec~ively, along with a center tap 42 which is connected to a return potential of the input voltage, along connecting lead 43. The PWM
square waves from the control unit 16 are transformer coupled through transformer 18 to a common emitter power switch configuration including transistors 40 and-46. The emitters 45 and 44, of transistors 40 and 46, respectively, are con-nected to the center tap 42 of transformer 18 which is connected to the return potential of the input voltage.
The base 38 of transistor 40 is connected to the upper secondary winding terminal 36 while the base 50 of tran-sistor 46 is connected to the lower terminal 48 of the ~ seconda~ry winding of transformer 18 thereby completing the input to the power switching transistors. The output of the power switching transistors is coupled to the primary windings of twin connected transformers 56 and 57. Specifically, the collector 52 of transistor 40 is connected to the upper jj terminal of transformer primary winding 54 while the lower terminal 59 of the primary winding 54 is connected to the ,` positive potential of the input voltage, along connecting lead 60. The input voltage is stabilized by capacitor 64 appearing across the input. It will be noted that the lower !~
i, I
~ 3~ ~
terminal of primary winding 54 (transformer 56) is directly connected to the upper -terminal of primary winding 61 (trans-former 57) so that the previously mentioned positive potential is likewise provided the upper terminal of primary winding 61.
The collector of transistor 46 is connected to the lower terminal of primary winding 61, via connecting lead 58.
In operation of the circuit, the PWM square waves from transformer 18 are fed to the power switching transistors 40 and 46 whlch operate as saturated switches 180 degrees out of phase with each other. While transistor 40 is con-ducting, current is built up in transformer 56 and when transistor 40 is turned of, transistor 46 turns on and operates 180 degrees out of phase with transistor 40. The upper terminal of the secondary winding 66 (transformer 56) is connected to the anode of a diode 68 while the lower terminal of the secondary winding 72 (transformer 57) is connected to the anode of diode 74. The cathodes of the ; diodes 68 and 74 are connected in parallel to lead 76.
With transistor 40 conducting, polarity is such that diode 68 is reversed biased. When transistor 40 turns off, diode 68 becomes forward biased and load current is supplied until transistor 40 turns on again. Operation of diode 74 similarly utilizes the switching of transistor 46 and coupling -throu~h ; transformer 57. However, diode 74 operates 180 degrees out of phase with diode 68.
The cathode of diode 68 is connected~ via lead 76, as the positive potential point 77 for the output voltage.
The junction point 70 between the lower terminal of secondary ~1 .
!!
i! - 6 -.~
~ ~ 7~
winding 66 (transformer 56) and the upper terminal of sccondary winding 72 (transformer 57) is connected as a common terminal 28 for the output voltage. In order to sense current flowing through the output section of the inverter, a resistor 80 is connected between the common terminal 28 and the junction point 70 of the secondary windings of transformers 56 and 57. The previously mentioned current sense line 26 performs its current sensing function by monitoring a small voltage across the resistor 80 thereby providing overcurrent protec-tion. Capacitors 82 and 84 are connected across the output voltage terminals to filter the output voltage thus providing a well regulated supply.
.~.
PWM CONTROL UN _ Referring now to FIG, 3, the PWM control unit 16 is seen to ;nclude an operational amplifier 86 which serves as an error voltage amplifier. A first input to the amplifier is provided along lead 88 which is connected to the B-~ supply at 24, via resistor 90. The negative potential of the output voltage, along lead 28, is connected in parallel with the input 88 of amplifier 86, via Zener diode 94. The second input 96 to amplifier 86 carries the positive potential of the output voltage along lead 77. The output 98 of amplifier 86 produces an error signal between the reference B+ voltage and the output voltage. A second operational amplifier 100, serving as a current error amplifier has a first input connected along lead 104 to the common terminal 28 of the output voltage while a second input, appearing ,i .
.. . .
,i !
! I 7 .1 . .
~7 ~ 3 along lcad 26, carries the output current flowing through ~ resistor 80 (FIG~ 2) so that amplifier 100 is a current ; sensing device for achieving overcurrent protection. The output of amplifier 100 is connected, via lead 102, to the output of the amplifier 86 at a node 106 which, in turn, is connected as a first input 108 to comparator 110. The comparator is a high gain operational amplifier. In order to understand the nature of a second input 115 to comparator 110, reference is made to oscillator 112 which generates clock signals at the output thereof which are fed to integrator 114 which integrates the trigger pulse signals to form a triangular wave as shown at the output of integrator 114.
The superposition of the DC level input to comparator 110 and the triangular signal input to the comparator is illustrated along lead 126 at the output of comparator 110.
A pulse width modulated signal occurs and as shown along lead 126, it has zero crossovers at the point of intersection between the triangular and DC signals. The PWM signal on ` lead 126 is fed in parallel to NAND gates 120 and 124.
A second input 118 to NAND gate 120 is derived as an output from flip-flop 117 while a complem~ntary output 122 from . the flip-flop 117 drives a second input of N~ND gate 12~. !
The purpose of flip-flop 117 is to enable gates 120 and ' 124 in synchronism with the clock input pulses to flip-flop 117 as they occur along oscillator output lead 116. The gates 120 and 124 are enabled 180 degrees out of phase with ~i each other. This difference of phase conduction is conveyed 1, at respective output terminals 128 and 129 to the upper li '' '' ~ 8 -_.
~L~'7~3~
and lower primary winding terminals 30 and 34. A reference voltage, namely B+, is connected to ~he center tap 3Z of the primary winding of transformer 56 via a semiconductor current source 130. The PWM pulses appearing at the primary winding of transformer 56 are coupled to the subsequent inverter circuitry as previously explained in connection with FIG. 2.
FIG. 4 is a composite timing diagram showing signal waveforms at various points in the circuitry of the inverter, as indicated on the Figure.
; It should be understood that the invention is not limited to the exact details of construction shown and described herein for obvious modifications will occur to persons skilled in the art.
- g _
Claims (2)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A power inverter for providing a DC regulated output voltage, the inverter comprising:
means connected at the input thereof to the output voltage for generating a pulse signal having a duty cycle which is a function of the output voltage;
power switching means biased by an unregulated DC
input voltage;
means connecting an output of the generating means to an input of the power switching means for driving the switch-ing means; and means for filtering an output of the switching means and producing the regulated output voltage, the switching means further including:
(a) first and second transistors each having first and second output terminals;
(b) means interconnecting the first output terminals of the transistors;
(c) first and second transformer primary windings each of which have first and second terminals;
(d) means connecting the first terminals of the wind-ings;
(e) means connecting each of the second terminals of the windings to a respective second output terminal of the transistors;
(f) means connecting the unregulated DC input voltage to the connected first terminals of the windings;
(g) first and second transformer secondary windings, each of which have first and second terminals;
(h) means interconnecting the first -terminal of each secondary winding; and (i) a plurality of rectifier means each connected to a respective second terminal of the secondary windings.
means connected at the input thereof to the output voltage for generating a pulse signal having a duty cycle which is a function of the output voltage;
power switching means biased by an unregulated DC
input voltage;
means connecting an output of the generating means to an input of the power switching means for driving the switch-ing means; and means for filtering an output of the switching means and producing the regulated output voltage, the switching means further including:
(a) first and second transistors each having first and second output terminals;
(b) means interconnecting the first output terminals of the transistors;
(c) first and second transformer primary windings each of which have first and second terminals;
(d) means connecting the first terminals of the wind-ings;
(e) means connecting each of the second terminals of the windings to a respective second output terminal of the transistors;
(f) means connecting the unregulated DC input voltage to the connected first terminals of the windings;
(g) first and second transformer secondary windings, each of which have first and second terminals;
(h) means interconnecting the first -terminal of each secondary winding; and (i) a plurality of rectifier means each connected to a respective second terminal of the secondary windings.
2. The subject matter set forth in claim 1 wherein the filtering means is connected to outputs of the rectifier means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17934980A | 1980-08-18 | 1980-08-18 | |
| US179,349 | 1980-08-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1179015A true CA1179015A (en) | 1984-12-04 |
Family
ID=22656214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000383549A Expired CA1179015A (en) | 1980-08-18 | 1981-08-10 | Twin transformer inverter |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS5755777A (en) |
| AU (1) | AU542899B2 (en) |
| CA (1) | CA1179015A (en) |
| DE (1) | DE3131729A1 (en) |
| FR (1) | FR2488752A1 (en) |
| GB (1) | GB2095439B (en) |
| IL (1) | IL63326A (en) |
| IT (1) | IT1139128B (en) |
| NO (1) | NO159568C (en) |
| SE (1) | SE452826B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943903A (en) * | 1989-03-14 | 1990-07-24 | Cardwell Jr Gilbert I | Power supply in which regulation is achieved by processing a small portion of applied power through a switching regulator |
| GB2320342A (en) * | 1996-12-14 | 1998-06-17 | Jonathan Hugh Lambert Copus | Voltage supply circuit with stabilised output control |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2058856A5 (en) * | 1969-09-30 | 1971-05-28 | Labo Cent Telecommunicat | |
| US3670234A (en) * | 1970-06-30 | 1972-06-13 | Ibm | Pulse width modulated voltage regulator |
| FR2260892A1 (en) * | 1974-02-13 | 1975-09-05 | Scient Electric | DC to DC converter with power amplifier - has output isolated from input by means of transformers |
| FR2288413A1 (en) * | 1974-10-17 | 1976-05-14 | Telemecanique Electrique | Stabilised DC power supply unit for computer - uses two regulation control loops in chopping circuits |
| US4062057A (en) * | 1977-04-15 | 1977-12-06 | The United States Of America As Represented By The Secretary Of The Navy | Regulated power supply having a series arrangement of inverters |
| US4195333A (en) * | 1978-05-30 | 1980-03-25 | General Electric Company | DC to DC voltage converter |
-
1981
- 1981-07-14 GB GB8121597A patent/GB2095439B/en not_active Expired
- 1981-07-15 IL IL63326A patent/IL63326A/en unknown
- 1981-08-05 AU AU73695/81A patent/AU542899B2/en not_active Ceased
- 1981-08-07 JP JP56123976A patent/JPS5755777A/en active Pending
- 1981-08-07 NO NO812682A patent/NO159568C/en unknown
- 1981-08-10 CA CA000383549A patent/CA1179015A/en not_active Expired
- 1981-08-11 DE DE19813131729 patent/DE3131729A1/en not_active Ceased
- 1981-08-12 FR FR8115648A patent/FR2488752A1/en active Granted
- 1981-08-13 IT IT23513/81A patent/IT1139128B/en active
- 1981-08-14 SE SE8104843A patent/SE452826B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| IL63326A (en) | 1983-11-30 |
| SE8104843L (en) | 1982-02-19 |
| NO159568C (en) | 1989-01-11 |
| NO812682L (en) | 1982-02-19 |
| SE452826B (en) | 1987-12-14 |
| GB2095439A (en) | 1982-09-29 |
| GB2095439B (en) | 1984-01-11 |
| NO159568B (en) | 1988-10-03 |
| AU7369581A (en) | 1982-02-25 |
| AU542899B2 (en) | 1985-03-21 |
| IL63326A0 (en) | 1981-10-30 |
| FR2488752B1 (en) | 1985-04-12 |
| IT8123513A0 (en) | 1981-08-13 |
| DE3131729A1 (en) | 1982-05-27 |
| IT1139128B (en) | 1986-09-17 |
| FR2488752A1 (en) | 1982-02-19 |
| JPS5755777A (en) | 1982-04-02 |
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