JPS6029894A - Led driving circuit - Google Patents
Led driving circuitInfo
- Publication number
- JPS6029894A JPS6029894A JP13879783A JP13879783A JPS6029894A JP S6029894 A JPS6029894 A JP S6029894A JP 13879783 A JP13879783 A JP 13879783A JP 13879783 A JP13879783 A JP 13879783A JP S6029894 A JPS6029894 A JP S6029894A
- Authority
- JP
- Japan
- Prior art keywords
- input
- led
- transistor
- flip
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Audible And Visible Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明はLFiDの駆動回路に関し、Dフリップフロッ
プと遅延回路を使用し、遅延回路の遅延時間をLBDの
点灯周期時間とする1、EID駆動回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an LFiD drive circuit, and more particularly to an EID drive circuit that uses a D flip-flop and a delay circuit and uses the delay time of the delay circuit as the lighting cycle time of the LBD.
従来この種のLED駆動回路にはスタチック駆動方式と
ダイナミック駆動方式があシ、スタチック駆動方式はL
ED保膿を特に心安としないが。Conventionally, this type of LED drive circuit has a static drive method and a dynamic drive method, and the static drive method is L.
I don't particularly feel safe about ED infection.
消費電力がダイナミック駆動方式にくらべて太きいとい
う欠点があり、ダイナミック駆動方式は消費電力をスタ
チック駆動方式より少く出来るが。The disadvantage is that the power consumption is higher than that of the dynamic drive method, although the dynamic drive method can consume less power than the static drive method.
駆動回路入力信号の状態によってはLEDを損傷する可
能性があるといった欠点があった。There is a drawback that the LED may be damaged depending on the state of the drive circuit input signal.
本発明はLEDの点灯時間をLEDに電流が流れたこと
をトリガーとする遅延回路の遅延時間となるように制御
し1点灯時間を入力信号から切り離すことにより上記欠
点を解決し、入力側の動作停止によるLEDの損傷を防
止できるようにしたLBD駆動回路を提供するものであ
る。The present invention solves the above drawbacks by controlling the lighting time of the LED so that it becomes the delay time of a delay circuit triggered by current flowing through the LED, and separating one lighting time from the input signal, thereby improving the operation of the input side. An object of the present invention is to provide an LBD drive circuit that can prevent damage to LEDs due to stoppage.
本発明の構成について述べると1本発明は、D端子にL
ED点灯要求信号が入力し、C端子にLIDD点灯周期
タイミング信号が入力するDフリップフロップと、この
Dノリツブ70ツブのQ出力によシ導通するトランク2
、夕と、このトランジスタの導通により点灯するLBD
と、前記トランジスタの出力を入力とし一定時間遅らせ
て発生した出力を前記DフリップフロップのR端子に入
力する遅延回路とよりなるLED駆動回路である。Describing the configuration of the present invention, 1. the present invention has an L terminal connected to the D terminal.
Trunk 2 is connected to the D flip-flop to which the ED lighting request signal is input and the LIDD lighting cycle timing signal is input to the C terminal, and the Q output of this D knob 70.
, and the LBD lights up due to the conduction of this transistor.
and a delay circuit which inputs the output of the transistor and inputs the output generated after a certain time delay to the R terminal of the D flip-flop.
上述の構成とすることによシ1本発明によれば、LI1
3D点灯袈求信号およびLED点灯周期タイミング信号
がいかなる状態で停止しても、LEDを損傷しないよう
に保護することができる。According to the present invention, by having the above-mentioned configuration, LI1
Even if the 3D lighting request signal and the LED lighting cycle timing signal stop under any condition, the LED can be protected from being damaged.
以下本発明を実施例により図面を参照して説明する。The present invention will be explained below by way of examples with reference to the drawings.
第1図は本発明実施例の回路図を示し、第2図はその動
作波形図を示している。FIG. 1 shows a circuit diagram of an embodiment of the present invention, and FIG. 2 shows its operating waveform diagram.
第1図において、1はD 71Jツブフロツプ、2はト
ランジスタ、3はLED、4は遅延回路であり、DAT
Aは点灯非求償号、、 CYCIJは1.llliD点
灯周期タイミング信号である。In Figure 1, 1 is a D71J block flop, 2 is a transistor, 3 is an LED, and 4 is a delay circuit.
A is a lighting non-compensation number, CYCIJ is 1. lliD lighting cycle timing signal.
いま第2図に示すように、 DATAが論理値l1l(
LBD点灯安求)の時CYCI、Eが01から“11に
立上ると、Dフリップ70ツブ1は出力Qに11“を出
力してトランジスタ2をオンにし、 l、EliD3に
電流が流れ%1JD3が点灯する。遅延回路4はLED
の電流有シ、無しをflZlO″、Th判断しており、
ある一定時間tdだけ遅れて発生した出力をDフリップ
70ツブlのリセット端子Rに入力するため、Dフリッ
プフロップ1のQ出力は101となシ、トランジスタ2
けメツとなる。したがってLBD3はDフリップフロッ
プがCYCLEの立上シでセットされてから一定時間t
d経過後の遅延回路4の出力でリセットされるまでの間
点灯するため、DATA 、 CYCI、E の入力信
号がいかなる状態で停止しても、その状態に関係な(L
BD−z損傷から保護することが可能である。Now, as shown in Figure 2, DATA has the logical value l1l (
When CYCI, E rises from 01 to "11" when LBD is turned on), D flip 70 knob 1 outputs 11 to output Q, turns on transistor 2, and current flows through l and EliD3.%1JD3 lights up. Delay circuit 4 is LED
The presence or absence of current is determined by flZlO'', Th,
Since the output generated after a certain period of time td is input to the reset terminal R of the D flip-flop 70, the Q output of the D flip-flop 1 is 101, and the transistor 2
Becomes depressed. Therefore, LBD3 is set for a certain period of time t after the D flip-flop is set at the rising edge of CYCLE.
Since it remains lit until it is reset by the output of the delay circuit 4 after d has elapsed, no matter what state the input signals of DATA, CYCI, and E stop, the (L
It is possible to protect against BD-z damage.
以上に説明したように、本発明によれば、 IJDの点
灯時間をl、FliDに流れる・電流の有無を入力とす
る遅延回路の遅延時間で制御する構成とすることによシ
、入力信号のいかなる状態での停止に対しても、LED
に連続して電流が流れ1.[BDを損傷するという障害
を防止でさる効果がある。As explained above, according to the present invention, the lighting time of the IJD is controlled by the delay time of the delay circuit whose input is the presence or absence of current flowing through the FliD. LED for stoppage in any condition
Current flows continuously through 1. [This has a great effect in preventing the trouble of damaging the BD.
第1図は本発明実施例の回路図、第2図は集1図回路の
動作波形図である。
1・・・・Dフリップ70ツブ、2・・・・・・トラン
ジスタ、3・・・・・・LII)、4・・・・・・遅延
回路、 DATA・・・・・・1.1点灯安求伯号、
CYCIJ・・・・・・LED点灯周期タイミング信号
、td・・・・・・遅延時間。
箔/図
(F入力)
第?図
手続補正書
86オ。58年t!N’A12% F3特許庁長官殿
1、事件の表示
昭和58年特許願第138797号
2、発明の名称
LED駆動回路
3 補正をする者
事件との関係 特許出願人
東京都港区芝五丁目33番1号
(423)日本電気株式会社
代表者 関本忠弘
4代理人
東京都大田区上池台4丁目101q、6−号。
明細書の発明の詳細な説明の欄および図面の第1図
7 補正の内容
(1)明細舎弟1項第17行の1に関する。」を1に関
するものである。」に訂正する。
(2)図面の第1図を添付図面のとおシ訂正する。
代理人 弁理士 栗 1)春 雄FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is an operational waveform diagram of the circuit shown in FIG. 1...D flip 70 tube, 2...transistor, 3...LII), 4...delay circuit, DATA...1.1 lights up Yasu Hakugo,
CYCIJ...LED lighting cycle timing signal, td...Delay time. Foil/Figure (F input) No.? Illustration procedure amendment 86o. 58 years t! N'A12% F3 Mr. Commissioner of the Japan Patent Office 1, Indication of the case Patent Application No. 138797 of 1982, 2 Name of the invention LED drive circuit 3 Person making the amendment Relationship to the case Patent applicant 33 Shiba 5-chome, Minato-ku, Tokyo No. 1 (423) NEC Corporation Representative Tadahiro Sekimoto 4 Agent No. 6-101Q, Kamiikedai 4-chome, Ota-ku, Tokyo. Detailed Description of the Invention in the Specification and Figure 1 in the Drawings 7 Contents of Amendment (1) Regarding 1 in Section 1, Line 17 of the Specification. ” is related to 1. ” is corrected. (2) Figure 1 of the drawings is corrected to match the attached drawings. Agent Patent Attorney Kuri 1) Yu Haru
Claims (1)
点灯周期タイミング信号が入力するDフリップ70ツブ
と、このD7リツプ70ツブのQ出力により導通するト
ランジスタと、このトランジスタの導通により点灯する
LEDと、前記トランジスタの出力を入力とし一定時間
遅らせて発生した出力を前記Dフリップ70ツブのR端
子に入力する遅延回路とよりなるLED駆動回路。An LED lighting request signal is input to the C terminal, and an LED lighting request signal is input to the C terminal.
A D-flip 70 block to which the lighting cycle timing signal is input, a transistor that is turned on by the Q output of this D7-lip 70 block, an LED that lights up due to the conduction of this transistor, and a signal that is generated after a certain period of time with the output of the transistor as input. An LED drive circuit comprising a delay circuit whose output is input to the R terminal of the D flip 70 tube.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13879783A JPS6029894A (en) | 1983-07-29 | 1983-07-29 | Led driving circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13879783A JPS6029894A (en) | 1983-07-29 | 1983-07-29 | Led driving circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6029894A true JPS6029894A (en) | 1985-02-15 |
Family
ID=15230448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13879783A Pending JPS6029894A (en) | 1983-07-29 | 1983-07-29 | Led driving circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029894A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61205225U (en) * | 1985-06-11 | 1986-12-24 |
-
1983
- 1983-07-29 JP JP13879783A patent/JPS6029894A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61205225U (en) * | 1985-06-11 | 1986-12-24 |
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