JPS6029859A - Data buffer device - Google Patents

Abstract

PURPOSE:To facilitate high-speed, multiplexing operation by selecting and inputting a series of data from a memory to a multichannel type data buffer in a period, and outputting them, one by one, selectively; in the same period. CONSTITUTION:The buffer memory 40 consists of (n) units of memory elements 41-1-41-n in a matrix of longitudinally (m) by laterally (n/m) (m and n; integer). The respective elements are selected independently and have >=n pieces address. Then, (m) data D1 of the same channel are transferred to the buffer 40 under the command of a control circuit 20 in an input mode period by (n/m) times to store (n) pieces data, and an input selector 42 designates the addresses for the data D1. An output selector 43 selects output data D2, one by one. Input and output address counters 44 and 46 drive themselves to report the addresses of the data D1 and D2 to the control circuit 20 through an address selector 45. Then, data of all channels are replaced at intervals of nXT data (repetitive period of data D2) to perform high-speed multiplexing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multiplexed channel type data buffer device.

[Technical background of the invention and its problems]

Generally, a data buffer device used in an audio output device or the like is configured as shown in FIG. 1, for example. That is, a series of data strings DJ are stored in the output buffer 11 (= stored) from the data memory 1G, and data D2, which is a time-series version of the data string DI, is output from the output buffer 11 at a predetermined timing.
is configured to be transmitted to an output device (not shown).

Incidentally, in FIG. 1, the transmission speed of the data D2 from the output sofa 11 is usually low, although it varies depending on the content of the data D2 and the performance of the output device. On the other hand, the transfer speed of the data string D1 from the data memory 10 is
Can be accelerated within hardware limitations. In this case, if the output device has a data decoding method, the effect of data compression by encoding is added to the delta memory 10 (=), and the actual amount of data transferred to the output device of the data string D1 is The ratio N is normally "Nx1". Therefore, if the multiplicity is n, multiplexing of the data expansion device can be realized within the range of "n<NJ".

The multiplexing type data buffer device as described above has a configuration as shown in FIG. 2, for example.

That is, the data string D1 from the data memory 10 is sent to the buffer memory 21 in response to the timing signal TI from the control circuit 20. The buffer memory 21 stores the data string DI based on the address A given from the address counter (n-ary self-running type) 21. The buffer memory 2 then transmits the data D2 to an output device (not shown) in response to the input/output mode switching command signal M from the control circuit 20. At this time, the control circuit 20 sends a synchronization signal T2.
is supplied to the output device and cured.

The data transfer timing in such a multiplexing data buffer device is, for example, as shown in Fig. 3(a), (
b) where 0 as shown in Figure 3(a).

In (b), Ch1 to Chn are data '9D1 or data D2 corresponding to n channel NOs for each output device. In addition, IM and OM are each control circuit 2
This is the input mode section and output mode section according to the signal M of 0, and T is the output data D from the buffer memory 2.
It has a repetition period of 2.

By the way, in the data buffer device that transmits data at the above-mentioned timing, when transferring the data string D1 from the data memory 10 to the backup memory 21, the data of each channel forming a different sequence is switched sequentially for a short time ζ. It will be transferred. Therefore, processing such as address access to the data memory 10 becomes complicated, and data transfer becomes difficult as the degree of multiplicity increases.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to reliably access a series of data strings stored in a data memory with simple control, and to output data for each channel to an output device having multiplexed channels. An object of the present invention is to provide a multiplexing type data buffer device that can reliably transfer data.

[Summary of the invention]

According to the present invention, in a data buffer device that transfers a series of data strings output from a data memory to an output device as data for each channel, a multilayer memory is provided that includes a plurality of memory elements corresponding to the number of channels. Each memory element of this buffer memory has an address corresponding to the number of channels. The memory element for storing input data to the buffer memory is selected by an input data memory select circuit that performs a stepping operation according to the number of channels during a data output period of the buffer memory. Further, the memory element to which data is output from the buffer memory is selected by an output data memory select circuit that performs a stepping operation every data output period of the backup memory. The addresses of the memory elements selected by the input data memory select circuit x9 are set by the input data memory address counter circuit which performs a step operation every data output cycle of the buffer memory. In addition, the memory element selected by the output data memory select circuit is set by the output data memory address counter circuit, which performs step operation according to the number of channels during the data output period of the buffer memory. configured to be carried out.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a block diagram showing the configuration of a data buffer device according to an embodiment.

In Figure 4, 40 is a buffer memory with m vertical and n horizontal
/n1 (where m and n are integers) are provided with n memory elements (RAM elements) 41-1 to 41-n. Each of the memory elements 41-1 to 41-n can be independently selected, and at least n
It has more than one address. 42 is an input data chip select circuit (hereinafter referred to as an input chip selector) which transfers data D1 from the data memory 10 to the buffer memory 40.
Storage destination memory elements 41-1 to 41-n when inputted
Select. Reference numeral 43 denotes an output data memory select circuit (hereinafter referred to as an output chip selector) which selects memory elements 41-1 to 41-n when data D2 is transferred from the banker memory 4θ to an output device (not shown). . The input data memory address counter circuit (hereinafter referred to as the input address sector) 44 is a self-running address counter, and is configured to input eight addresses of each memory element 41-1 to 41-n when the input data D1 is stored. 1 is output to the address selector 45. The output data memory address counter circuit (hereinafter referred to as output address sector) 46 is a self-running address counter circuit similar to the input address counter 44, and is a self-running address counter circuit similar to the input address counter 44. Each memory element 4no1~41-
The address A2 of n is output to the address selector 45.

This address selector 45 selects either address A1 or address A2 in response to input/output mode switching command signal M from control circuit 2o, and outputs the selected address to each memory element 41-1 to 41-n of buffer memory 4o.

The operation of the Gator buffer device having the above-described complicated configuration will be explained. First, data D1 from data memory 1θ
is input to the pack memory 4θ, the control circuit 2o
Input mode (Write mode) according to the command signal M of
The same channel (cbi) every m in synchronization with the period IM
data D1 is transferred to the buffer memory 4o. At this time, the input chip selector 42 as shown in FIG. 5 simultaneously selects memory elements (m pieces) for each column, and T
Transferred n 7m times in a period to n memory elements 41-
n pieces of data are stored in 1 to 41-n. At this time, the address A1 from the input address counter 44 is given to the buffer memory 4o through the address selector 45, so that each memory element 41-1 to 4 node n
Data of the same channel is stored at the same address i. Next, the data stored in each memory element 4NO1 to 4NON is transferred to data D2 for each channel during a period T in synchronization with an output mode (Read mode) period OM according to a command signal M of the control circuit 120. They are output one by one as follows, and all are output after nT time. At this time, as shown in FIG. 5, each memory element K is selected by the output chip selector 43 during the T period, and the address A2 from the output address counter 46 is given to the memory element K. As a result, the n-channel data stored in memory element K is output during period T and transferred to an output device (not shown).

In this way, the input chip selector 42 is set to n /
m, keeping the output chip selector 43 and input address counter 44 constant, advancing the output address sector 46 by n, and switching the input/output mode switching signal M 2n times. Data input/output control as shown in Figure (a) can be performed.

Furthermore, the chip selector 43 and input address sector 44 increments one current to n every T period, so that all channel data is stored in the buffer memory 40 every time during the nT waiting time, and Afterwards, all channel data will be output from the buffer memory 40. That is, since the input and output data flows to and from the buffer memory 40 are orthogonal, the input data channel can be kept the same for T periods or n 7m consecutive transfers. Furthermore, in data input/output control as shown in FIG. 6(b), the operation is similar to that shown in FIG. It will be realized.

〔Effect of the invention〕

As described in detail above, according to the present invention, in a multiplexed channel type data buffer device, the data memory The data output of the data memory can be easily controlled when data is transferred from the data memory to the buffer memory. Therefore, a series of data strings stored in the data memory can be accessed with simple control, and an output having multiplexed channels can be easily controlled. Data for each channel can be reliably transferred to the device. moreover,
Since it is not necessary to change the access address of the data memory in a complicated manner, it is easy to use DMA transmission etc. between the data memory and the buffer, and it is possible to increase the speed and multiplexing of data transmission. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a conventional data buffer device, FIG. 2 is a block diagram showing a configuration of a conventional multiplexing type data buffer device, and FIG. 3(a),
(b) is a timing chart for explaining the operation of the data buffer device shown in FIG. 2, FIG. 4 is a block diagram showing the configuration of the data buffer device according to an embodiment of the present invention, and FIGS. Figures (a) and (b) are timing charts for explaining the operation of the data buffer device shown in FIG. 4, respectively. 10... Data memory, 20... Control circuit, 40.
. . . Buffer memory, 41-1 to 41-n mountain memory element, 42. Chip selector for input, 43. Chip selector for output, 44. Address counter for input, 45. Address senfter. 46...Output address counter. Patent attorney representing applicant Takehiko Suzue

Claims (1)

[Claims] A buffer memory configured to include a plurality of memory elements corresponding to the number of channels, each memory element having an address corresponding to the number of channels, and a stepping operation according to the number of channels during the data output period of this buffer memory. And the buffer memory mentioned above? an input data memory select circuit that selects the memory element for storing input data for two pairs; and a memory select circuit for input data that selects the memory element for storing input data; an output data memory select circuit that selects a memory element; and an input data memory that performs a stepwise operation every data output cycle of the backup memory to generate an address for the memory element selected by the input data memory select circuit. an address counter circuit; and an output data memory address counter that performs stepwise operation according to the number of channels during the data output period of the buffer memory to generate an address for the memory element selected by the output data memory select circuit. A data buffer device comprising a circuit.