JPS6029041A - Counting type a/d conversion circuit - Google Patents

Abstract

PURPOSE:To improve A/D conversion accuracy without changing a using clock and A/D conversion speed by providing a counting-type A/D conversion circuit with a storage circuit consisting of an FF circuit and invertor. CONSTITUTION:An analog input signal, staring signal and clock pulse are inputted to a voltage and time converting circuit of a counting-type A/D conversion circuit. This input signal is converted to a pulse signal corresponding to time width, and outputted. The counting circuit 5 to which this pulse signal is inputted counts clocks in a pulse signal period. The AND gates 21 and 22 and memory circuit consisting of SR type FF circuit 23 and invertor 24 are provided to circuits 5 and 6. When terminating a pulse signal output of the circuit 5, clock logic or inversion logical level is stored in the storage circuit. The output obtained by adding a counting output of the circuit 5 and a bit output, which is 1-bit lower bit than the most significant bit, is issued, thereby enhancing conversion accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an A/D (analog/digital) conversion circuit construction, and particularly to a counting type A/1) conversion circuit.

[Technical background of the invention]

Conventionally, a counting type conversion circuit which performs counting for a time corresponding to an analog input voltage and uses the counted value as a digital output has been constructed as shown in FIG. That is, the voltage/time conversion circuit 1 starts converting the analog input voltage from the analog input terminal 2 according to the start signal from the control terminal 3, and converts the voltage/time conversion circuit 1 into a base pulse with a time width T corresponding to the voltage level. It is a device that converts the output of signals, and operates based on the clock, clock, and loop signals from the clock terminal 4. A counter (counting circuit) 5Fi receives the pulse output from the conversion circuit 1 as a dirt pulse, counts the clock pulses from the clock terminal 4 during this pulse input period, and calculates the output from the output terminal 6.
Generates how to count parallel bits. Therefore, this count output corresponds to the analog input voltage.

[Problems with background technology]

In the counting type A/D conversion circuit h as described above, if the voltage/time conversion circuit I has high accuracy, the A/D conversion accuracy depends on the resolution of the counter 5. counter 5
has a resolution of 1 clock time.In order to improve the A/D conversion accuracy, it is necessary to know the clock period, but this is usually due to other constraints. There are limits. Therefore, as another method for improving the horizontal conversion accuracy, it may be possible to lengthen the time width of the voltage/time conversion output pulse, but this would reduce the conversion speed.

[Purpose of the invention]

The present invention was made in view of the above circumstances, and allows A/'D conversion without changing the clock used or the line conversion speed.
The present invention provides a counting type conversion circuit that can improve conversion accuracy.

[Summary of the Invention] That is, the clock pattern embroidery conversion circuit of the present invention converts an analog input signal into a pulse signal with a time width corresponding to its level,
The blacks and pulses are counted only during the output period of this conversion signal, and the black pulses are counted at the end timing of the conversion signal.

The logic level of the signal or its inverted level is memorized,
The present invention is characterized in that the stored signal is added as a signal one bit lower than the least significant bit to the counted output obtained by the counting, and a converted output is extracted.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be explained in detail with reference to the drawings.

The conversion circuit shown in FIG. 2 is different from the conventional conversion circuit described above with reference to FIG.
22.1 set-reset (SR) type flip-flop,
The difference is that a storage circuit 2θ consisting of an F/F circuit 23 and one inverter 24 is added, but the other parts are the same, so the same reference numerals as in FIG. 1 are given, and the explanation thereof will be omitted. The specific parts will be described below.

That is, the first AND gate 21 operated by two people receives the output signal of the voltage/time conversion circuit 1 as one input, and
Black, Ri, and +Rus are introduced as the other inputs, and the AND output thereof is introduced as the set input S of the FOP circuit 23. Also, the second and of two people? ”-1-22/d
-1 The output pulse of the voltage/time conversion circuit 1 is introduced as one input; , its AND output is led as the reset power R of the Fβ circuit 23.Then, the set output S of the F/'F' circuit 230 is outputted through the output terminal 25, and the least significant bit (LSB) of the count output of the counter 5 is output. The addition is added as a bit output one bit lower.

Next, the operation of the above-mentioned AA conversion circuit will be explained with reference to FIG. After inputting the start signal, the voltage/time conversion circuit 1 starts the conversion operation at the falling edge of the first clock pulse input, and at the same time as this start, the output/start pulse occurs, and the time corresponding to the analog input voltage is calculated. After that, the above-mentioned appearance/yarus ends. During the period of this output i'f pulse, the counter 5 counts the clock pulses, and the first 7:/t)f-t 22 and the second AND/dart 23 correspond to clock pulses, pulses, and inversions, respectively. Pass the clock pulse.

The F/F circuit 23 responds to, for example, the rising edge of the input clock, and outputs the clocks and clocks from each of the ANDGs 1-27 and 22, for example.
The set output Q is set and reset by the clock, and the set output Q is inverted every time a clock input is applied. In this case, if the logic level of the clock pulse is 60" at the time t1 when the output pulse of the voltage/time conversion circuit 1 ends, then the F/
Set output of F' circuit 23. If the logic level of the output pulse is 0 high at the time t2 when the output pulse ends, the F/F circuit 2
30 set output Q is also at 1 high" level. That is, set output QI'i of f circuit 23, voltage/time r#!1
This means that the end timing of the variable grinding output/yarus is detected with a resolution of 1 chrome or 1/2 of the time. And this F
The set output Q of the /F circuit 23 is the counting output of the counter 5 (
The resolution of this is 1 chromatography (the resolution is 1 chronograph), and by adding it as 1-bit lower data, it is converted compared to the A/D f-min output (corresponding to the conventional example) consisting only of the counting output of the counter 5. A highly accurate A/D conversion output can be obtained. In this case, the comparison is made assuming that the frequency and number of clocks used and the voltage/time conversion speed are the same as in the conventional example.

Note that if the duty ratio of the clock pulse is 50, it is possible to determine whether the end timing of the voltage-time conversion output pulse is before or after the position exactly half of one clock time. Therefore, the conversion accuracy is the best. If the duty ratio of the clock pulse deviates from 50%, the above conversion accuracy will deteriorate, but the conversion accuracy will still be improved compared to the conventional example by 1 bit more than the count output of the counter 5. The present invention is not limited to the above embodiment, and instead of the combination of the AND gates 2 Z, 22, the F/F circuit 23, and the inverter 24, the main point is to change the voltage/time conversion output method and the signal termination timing. A storage circuit that stores the logic level (or its inverted level) of the clock pulse may be provided.

〔Effect of the invention〕

As described above, according to the counting type A/D conversion circuit of the present invention, the conversion accuracy can be improved without changing the clock used and the A/D conversion speed.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing a conventional counting type A/D converter circuit, FIG. 2 is a configuration explanatory diagram showing an embodiment of a counting type A/D conversion circuit according to the present invention, and FIG. FIG. 3 is a timing diagram shown for explaining the operation of FIG. 2; 1... Voltage/time conversion circuit, 5... Counting circuit, 20
...Memory circuit.

Claims (2)

[Claims] (1) A voltage/time conversion circuit that converts an analog input signal into a /4' pulse signal with a time width corresponding to the signal level and outputs the signal, and a 4' pulse signal output of this voltage/time conversion circuit is input, During this period of pulse signal input, black, ri/4'
and a memory circuit that stores the logic level of the clock/f pulse or its inverted level at the end timing of the output of the /4' pulse signal of the voltage/time conversion circuit, and the counting circuit A counting type A/D conversion circuit, characterized in that the memory output of a memory circuit is added to the counting output of the memory circuit as a signal of i bits lower than the least significant bit of the count output, and the output is taken out as an A/D conversion output. . (2) The counting type A/D conversion circuit according to item 1 of the patent scope, characterized in that the duty ratio of the clock pulse AfJ is approximately 50%.