JPS6029039A - Analog/digital conversion system - Google Patents

Abstract

PURPOSE:To output a digital signal conforming to a desired conversion law with simple constitution by inverting one specified bit or plural bits of output in a sequential resistor until output timing of digital output into the outside after completion of sequential comparison. CONSTITUTION:The analog signal from the analog signal input terminal 1 is sampled and held in the input sample holding circuit 2. During holding this signal, polarity of this analog signal is judged by using a comparator 3, porarity switching signal generation circuit 4, sequential approximate resistor 5 and D/A converter 6, and this polarity is converted into the BCD code by the sequential comparison system, and stored in the resistor 5. The bit inversion signal generation circuit 7 is connected to the converter 5. Until the digital signal output terminal 8 outputs the digital signal after completion of sequential comparison, the resistor 5 inverts the specified one bit or plural bits of its output, and outputs the digital signal according to the desired conversion law.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital conversion method, and particularly to a method using a successive approximation method for converting into a digital output signal according to a conversion law compressed based on the A-law. This relates to an analog-to-digital conversion method.

Among the analog-to-digital conversion methods, there are those that directly convert an analog signal into a digital signal, and those that convert non-linearly by compressing or expanding the signal according to a function such as a logarithmic function. Among these, it is used for audio pulse code modulation (PCM) signals in conversion rules that nonlinearly convert analog signals to digital signals.

The μ-law and A-law are well known.

The present invention particularly relates to an analog-to-digital conversion method that performs conversion according to the A-law among the above-mentioned non-reduced analog-to-digital conversion methods.

In analog-to-digital conversion according to the A-law, the digital output signal consists of the 9th, 3rd, and 5th bits, excluding the inertia pit (1st bit), as shown on the left side of Figure 2. , and the 7th bit is inverted from the normal binary coded decimal (BCD) code (μ-law digital output code) without the polarity bit as shown on the right side of Figure 2. It has become. In addition,
FIG. 2 shows a digital output signal in positive polarity, and in negative polarity, the first bit may be replaced with φ.

When performing analog-to-digital conversion according to the A-law, the characteristics of the digital-to-analog converter included in the analog-to-digital converter should be configured to compressed characteristics according to the A-law. An analog-to-digital conversion operation is performed using the successive approximation method according to the BCD code and according to the Tsumushima μ law.
Analog-to-digital signal conversion according to the A-law can be easily realized by inverting the odd-numbered bit digital signal of the CD digital output signal, excluding the polarity bit, in a successive approximation register after successive approximation.

In addition, by using this method, if the compression characteristics of the digital-to-analog converter included in the analog-to-digital converter are configured according to the μ law, the successive approximation register By outputting the odd-numbered bits of the digital output signal, excluding the polarity bit, without inverting the obtained digital output signal, the converter operates as an analog-to-digital converter according to the μ law. Tip 9: Use an analog-to-digital conversion system with such a configuration.If you switch the compression of the digital-to-analog converter included in the analog-to-digital converter, you can easily obtain the μ-law. and analog according to A-law.
This has the effect of overcoming digital conversion.

The present invention will be explained in detail below using the drawings.

FIG. 1 shows an explanation of one embodiment of the invention. Although FIG. 1 is a block diagram of an analog-to-digital converter employing the successive approximation method, it does not show the signal system for timing control used in the normal successive approximation method. Here, l
ll1. Analog signal input terminal, 2 is input sample/hold circuit, 3 is general control device, 4 is polarity switching signal generation circuit, 5 is successive approximation register, 6 is digital/analog converter, 7-wire bit inversion signal generation circuit, and 8
is a digital output signal terminal.

In the analog-to-digital converter configured as described above, an analog signal is sampled at the analog signal input terminal 1, held in the input sample/hold circuit 2, and held in the input sample/hold circuit. Comparator 3, polarity switching signal generation l&11wt4,
Using the successive approximation register 5 and the digital-to-analog converter 6, first the polarity of the input analog signal is determined, and then the input analog signal is converted into a BCD code using the successive approximation method bit by bit.・Save it up and go. After this successive approximation has reduced all the pits, a predetermined bit out of each bit stored in the successive approximation register 5 is converted to the third bit, 5th Pict, and 1g7
Until the timing of outputting the digital output signal from the digital output signal terminal 8 to the outside, the successive approximation register 5 receives a signal from the bit inversion signal generation circuit 7, and the output pit is lQH. In the case of Vt1
If ri is 1'', it is inverted to ``Q''.

For example, if the contents of the successive approximation register after the completion of the successive approximation are "1'X QQI I Ql", the contents after bit inversion become 'IIIQQIII'.

The data with predetermined bits inverted in this way is stored in the successive approximation register 5 until the output timing, and when the timing to output the digital output signal is reached, the digital output signal terminal 8 is correctly converted. Outputs the digital output signal.

As described above, by using the analog-to-digital conversion method that performs bit inversion in the present invention,
For example, when constructing an analog-to-digital converter on a semiconductor integrated circuit according to the μ law or the human law described above, the configuration shown in Figure 1 is created on the semiconductor substrate, and aluminum wiring patterns are Noyo Cidigital
The compression characteristics of the analog converter 6 are configured to be based on the μ-law or the A-law, respectively, and the bit inversion signal generation circuit 7 and the successive approximation register 5 are configured as follows in the case of the A-law.
In the same way as above, it is connected using an aluminum wiring pattern and configured so that a predetermined bit is inverted.On the other hand, in the case of μ law,
If the above two circuits are configured to be successively compared and output nine digital values as a digital output signal without interconnecting them, it is possible to easily use two types of conversion laws and the μ law in the same semiconductor integrated circuit. An analog-to-digital converter that follows A-law can be constructed. Furthermore, by adding a circuit to the bit inversion signal generation circuit 7 to selectively control whether or not to invert a predetermined bit, it is possible to freely control the inversion of a predetermined bit regardless of the conversion rule. For example, if the configuration is configured so that μ-law and A-law can be selected, various conversions can be made freely according to external signals using one circuit configuration, μ-law, A-law, μ It has the advantage that bits that are inverted according to the law and bits that are not inverted according to the A law can be easily obtained.

A system for inverting and outputting a predetermined bit of the digital signal stored in the successive approximation register of the present invention before the timing at which the digital output signal is output is the conversion described in this embodiment. isn't it.

[Brief explanation of the drawing]

Figure 1 is a line, a bootstrap diagram of an embodiment of the present invention, and Figure 2 is A.
An eye is drawn showing the corresponding sign of the anastomosis of the μ-law and μ-law. In addition, in the figure, l...analog 4? No. I power terminal, 2...Taito sample/hold circuit,
3... Comparator, 4... Signal generation circuit for polarity switching, 5... Successive approximation register, 6...
Digital/analog converter for..., 7... signal generation circuit for bit inversion, digital output signal terminal for..., output. %/ Senno 2 Sen procedure amendment (voluntary) Director General of the Patent Office 1, Indication of the case 1982 Patent Application No. 136105
No. 2, Title of invention Analog-digital conversion method 3,
Relationship with the case of the person making the amendment Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative: Tadahiro Sekimoto 4, Agent: 5-37-8 Shiba, Minato-ku, Tokyo 108 Sumitomo Sanda Building NEC Corporation (6591) Patent Attorney Susumu Uchihara Telephone Tokyo (03) 456-3111 (Main Representative) (Contact: NEC Corporation Licensing Department) (1) The scope of claims in the specification We will correct the description in the attached sheet. (2) "After reduction" on page 5, line 11 of the statement will be corrected to "after completion." (3) On page 5, line 14 of the specification, we have corrected the phrase ``to take an example'' to ``to take an example.'' (4) "5 bits" on page 5, line 15 of the specification will be corrected to "5 bits." (5) "In successive approximation register 5" on page 5, lines 17 to 18 of the specification will be corrected to "in successive approximation register 5."(6'l Details $5L line 19 rQ'J is r'O
' I would like to correct it as J. (7) Add “r-Q” on page 5, line 20 of the specification.
(8) r' IIQQIIQ on page 6 of the specification, line 2
I" J is corrected to r"11001101" J. (9) r-111QQIII" on page 6, line 3 of the specification
” will be corrected to “11100111” 0(1
0) Change “noyori” to “by” on page 6, line 15 of the specification
0 (11) "Bit" on page 6, line 20 of the statement will be corrected to "Bit". (]2) “Records” on page 7, line 13 of the specification is “various”
0 (13) Figure 2 is corrected as shown in "Attachment 2" 07 Attached documents Attachment 1 (corrected scope of patent claims) 1 Attachment 2 (Figure 2) 1 Attachment 1 ” Revised Claims [In an analog-to-digital converter using the successive approximation method, after the completion of the successive approximation method, until the timing at which the digital output signal is outputted to the outside, one or more specific bits of the digital output signal are An analog-to-digital conversion method 0 characterized by inverting bits in a successive approximation register and outputting a digital output signal according to a desired conversion law.

Claims (1)

[Claims] In an analog-to-digital converter using the successive approximation method, after the completion of the successive approximation, one bit or multiple pits of the % foot of the translated digital output signal are inverted in the successive approximation register before the digital output signal is output to the outside field. , an analog-to-digital conversion method whose characteristic is to output a digital output signal according to the desired conversion law.