JPS6028412B2 - Digital integrated circuit using FET - Google Patents

Description

Detailed Description of the Invention This invention forms a tri-state buffer circuit using FETs, and when enabled by a first input signal, the output of an external logic circuit connected to an output terminal is The present invention relates to a digital integrated circuit in which the level of an output terminal changes based on the logic level handled by an EFT, and the object is to eliminate power loss and heat generation and to reduce the size.

Conventionally, a tri-state buffer circuit using FETs is configured as shown in FIG.
two NOR gate circuits connected to one
The other input terminal of the OR gate circuit 1 is connected to the signal (SIGNA).
L) is connected to the input terminal 7, and the other input terminal of the other NOR gate circuit 2 is connected to the output terminal of the one NOR gate circuit 1.

3 and 4 are N-channel enhancement type MOSFEs.
There are two FETs consisting of T, and the gate and drain of one FET3 are the output terminals of the other NOR gate circuit 2,
are connected to the power supply VDD, and the other FE
The gate and drain of T4 are connected to the output terminal of one NOR gate circuit 1 and the drain of one FET3, and the FE
T4 source is grounded.

6 is an output terminal connected to a connection point between the source of one FET 3 and the drain of the other FET 4.

During the period when the enable signal at terminal 5, which is the first input signal, is at a low level, that is, during the enable control period in which the terminal 5 is held at a low level without being enabled, the second input signal at terminal 7 is is at a high level, FET3
Conversely, when the input signal at terminal 7 is at a low level, only FET 4 is turned on. Furthermore, the level of the output terminal 6 becomes high level due to the ON of FET3, and the level of the FET3 becomes high.
When ET4 is turned on, the level becomes low.

Therefore, during the period when terminal 5 is held at a low level,
A high level signal or a low level signal is output to the output terminal 6 based on the signal at the terminal 7.

On the other hand, while the enable signal is at a high level, that is, during the period in which the enable control is performed and the terminal 5 is held at a high level, both FETs 3
, 4 are both cut off, and the output terminal 6 is held in a high impedance open state.

By the way, the logic level handled by FETs 3 and 4, that is, MOS
an external logic circuit that operates at a logic level lower than
For example, even if you directly connect a TTL level logic circuit to the output terminal 6 and directly wire-OR the two levels to form an input signal for another logic circuit that operates at the MOS level, the TTL
Since the high level of the level output signal is lower than the high level of the MOS level input signal, the other logic circuit malfunctions.

Therefore, a configuration as shown in FIG. 2 has been devised.

That is, an FET 8 consisting of an N-channel enhanced method MOSFET is added to the configuration shown in FIG.
A power supply of 5V, which is the same as the power supply VDD in FIG. 1, is applied to the drains of FETs 3 and 8, and a voltage of 1
Apply a 2V power supply VDD2 and connect the source of FET8 to the output terminal 6.

Note that 9 in FIG. 2 is an external logic circuit at TTL level. The FET 8 is always on, and while both the FETs 3 and 4 are cut off, the level of the output terminal 6 is controlled to a high level or a low level based on the level of the output signal of the logic circuit 9. The output signal is TTL
When the level is high, the FET 8 acts as a pull-up resistor, and the high level of the output terminal 6 is pulled up to VDD, which satisfies the high level of the input signal of the MOS.

However, in the case of Figure 2, a relatively large current flows through FE'r8 and 4 while FET4 is on, resulting in power loss and heat generation that cannot be ignored. Considering this, a fairly large gain factor 8 is required for FET 8, and 8:0.1
Assuming 65mA/V2, when the low level voltage of output terminal 6 is 0.5V, a large current of about 6.8hA flows through the FE.
T8.4 was washed away. In addition, the gain factor 8 required for the FET 4 to allow such a current to flow through it also becomes considerably large, the input capacitance of the FET 4 increases, the delay time increases, the size increases, and the integration density becomes sparse. There are drawbacks. The present invention has been made with the above-mentioned points in mind, and includes a first FET that is turned off when the first input signal for enable control inputted to the gate is at a low level indicating no enable control, and a drain , the source is the first
a second FET connected to the drain and source of the FET, respectively, and whose source is grounded;
A pull-up FET is provided between the drain of the T and one power source, and the other FET has a gate and a source connected to the drain and source of the second FET, respectively, and the drain satisfies the high level of the MOS. connected to power,
a first output FET that is turned on only when the first and second FETs are both turned off; a second output FET whose drain is connected to the source of the first output FET; and a drain of the output FET. and an output terminal to which an external logic circuit whose high output level is set to a level that forcibly cuts off the first FET; The present invention provides a digital integrated circuit using an FET, comprising a gate circuit that turns on the second FET and the second output FET only when two input signals are both at a low level. be.

Therefore, according to the digital integrated circuit using the FET of the present invention, "during the enable non-control period when the first input signal is at a low level, the level of the output terminal is lower than that of the MO handled by the FET.
The first output FET is controlled to be turned on or off based on the output level of the external logic circuit during the efficient control in which the first input signal changes at the S level and the first input signal becomes high level. When the output level of the logic circuit is low, the first output FET is turned off and the output terminal is controlled to the low level of the MOS, and when the output level of the external logic circuit is high, the first output FET is turned on. The output terminal is pulled up to the high level of the MOS based on the other power supply, and a tristate output can be obtained at the output terminal based on the first and second input signals. Based on the output level of the circuit, the level of the output terminal can be changed at the so-called MOS level handled by the FET, and the output terminal can be used as an input terminal for a MOS level wired OR between the tristate output and the output of an external logic circuit. It is also possible.

Further, since there is no need to provide an FET that causes power loss and heat generation, and the current of the second output FET does not increase, power loss and heat generation can be eliminated and the device can be made smaller.

Next, this invention will be explained in detail with reference to FIG. 3 showing one embodiment thereof.

In FIG. 3, the same symbols as in FIG. 2 indicate the same or equivalent elements, 13 is the first FET whose gate is connected to the terminal 5, 14 is the drain and the source is the first FET 1.
A second FE connected to the drain and source of No. 3, respectively.
T, 12 is a pull-up FET whose gate and drain are connected to one power supply NDD2, and whose source is connected to the first FET.
Connected to the drain of ET13.

10 is a first output FET whose gate is connected to the drain of the second FET 14, whose drain is connected to the other power supply VDD, which satisfies the high level of the MOS, and whose source is connected to the first and second FETs. It is connected to the sources of FETs 13 and 14.

11 is a second output FET whose drain is connected to the source of the first output FET 10, and whose source is grounded.

Reference numeral 15 denotes an output terminal connected to the drain of the second output FET 11, to which an external logic circuit 9 at TTL level is connected.

16 is a NOR gate circuit with one input terminal connected to the terminal 5, the other input terminal connected to the terminal 7, and the output terminal connected to the second FET 14 and the second output FE.
Connected to the gate of TII.

In addition, each FETI 0, 1 1, 1 2, 1 3, 1
4 are five N-channel enhancement MOSFETs integrated on a common P-type semiconductor substrate.
, and the threshold voltage is IV.

Also, due to the setting of the gain factor 8 of the first and second FETs 13 and 14, when either of the FETs 13 and 14 is turned on, the first output FETIO is turned off, and when both FETs 13 and 14 are turned off, the first output FETIO is turned off. 1st only
The output FETIO of is turned on.

Furthermore, the pull-up FET 12 is set to be always on, and the gain factor B of the second output FET II is
It is set to a larger value than each gain factor 3 of the FETs 12, 13, and 14.

During the enable non-control period when the first input signal input to the terminal 5 is at a predetermined level, that is, a low level, the first FET 13 is cut off, and at this time, the first FET 13 is cut off.
If the second input signal input to
The output of the R gate circuit 16 goes low, and both the second output FET II and the second FET 14 are held in cutoff.

Therefore, while the first input signal is at a low level and the second input signal is at a high level, the first and second FETs 13 and 14
are both turned off and the first output FETIO is turned on, while the second output FETIO is cut off and the output terminal 15 becomes the high level of the MOS based on the power supply NDD.

Next, when the second input signal becomes low level during the period in which the first input signal is low level, the second output FETI
I and the second FET 14 are turned on, and the first output FE
TIO is cut off and the output terminal 15 goes to a low level based on the source level of the second output FET I.

That is, while both the first and second input signals are at a low level, the first output FETIO is cut off, the second output FETII is turned on, and the output terminals 1 to 5 are in the MOS state. becomes a low level.

On the other hand, during the enable control period in which the first input signal is at a high level, the second output FET II and the second FET 14 are held at cutoff regardless of whether the level of the second input signal is high or low. Ru.

The first FET 13 is turned on only when the output level of the logic circuit 9 is low, and is turned off when the output level of the logic circuit 9 is high. Therefore, while the first input signal is at a high level, the output level of the logic circuit 9 is T.
If TL is low level, the first, second output FETI
0 and 11 are both cut off, and at this time the logic circuit 9
Based on the output level of the output terminal 15, the level of the output terminal 15 becomes approximately the MOS low level.

Conversely, if the output level of the logic circuit 9 is a high level of TTL, both the first and second FETs 13 and 14 are cut off, so the first output FETIO is turned on and the level of the output terminal 15 is reduced. Power supply VDD. It is raised to a higher level of MOS based on

As described above, according to the embodiment, the level of the output terminal 15 changes at the MOS level based on the second input signal during the non-enable control period, as in the case of FIG. 2, and during the enable control period. changes at the MOS level based on the level of the external logic circuit 9, and not only has the function of a tristate buffer, but also connects the output terminal to a MOS level wired OR between the tristate output and the output of the external logic circuit 9. It can also be used as an input terminal.At this time, since FET8 shown in Fig. 2 is not provided, not only is there no power loss and heat generation due to FET8, but also the second output FET2 is not provided.
Since a large current does not flow through FET II as in FET 4 in Figure 2, there is no need to increase the size of FET II.
The circuit configuration is not more complicated than that shown in the figure, and it is possible to eliminate power loss and heat generation and to achieve a 4-inch design.

In addition, in the above embodiment, each FETI0, 11, 12, 13
, 14 are N-channel enhancement type MOSFEs.
Although the circuit is formed using a P-channel enhancement type or depletion type FET, it is of course possible to use a NAND gate circuit or the like in place of the NOR gate circuit 16.

[Brief Description of the Drawings] Figures 1 and 2 are connection diagrams of a subordinate tri-state buffer circuit, respectively, and Figure 3 is a wiring diagram of an embodiment of a digital integrated circuit using the FET of the present invention. It is. 10...First output FET, 11...Second output FET
, 13...first FET, 14... second FET, 15
...Output terminal, 16...NOR gate circuit. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A first FET that turns off when a first input signal for enable control input to the gate is at a low level indicating no enable control, and a drain and a source are connected to the drain and source of the first EFT, respectively. a second FET, a pull-up FET provided between the drains of both FETs and one power supply, and a pull-up FET whose gate and source are connected to the second FET.
A first output FET which is connected to the drain and source of the FET, respectively, and whose drain is connected to the other power supply that satisfies the high level of the MOS, and which is turned on only when both the first and second FETs are turned off. a second output FET whose drain is connected to the source of the first output FET and whose source is grounded; An output terminal to which an external logic circuit is connected is set to a level that forcibly cuts off the FET, and the second FET is connected only when the first input signal and the second input signal are both at low level. A digital integrated circuit using an FET, comprising: a gate circuit that turns on the second output FET.