JPS6028384A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To decrease sufficiently the effect of transfer efficiency even for a solid-state image pickup element having a large picture element number by dividing a CCD in a plural number to decrease the number of stages of transfer in the solid-state image pickup element provided with plural photodetectors arranged linearly. CONSTITUTION:The CCD is divided into four; 31-34. A clock phiT1 is inputted to a transfer gate and a signal of the photodetectors 15, 17 is read by the CCD33. Then a clock phiT3 is inputted and a signal of photodetectors 16, 18 is read by the CCD34. The signals are given to a multiplexer 60 through preamplifiers 43, 44 according to the drive of the CCDs 33, 34. The signal is read from an output terminal 50 in the order of photodetector 18 17 16 15. The CCDs 31, 32 are driven in the state not including any signal. Clocks phiT3 and phiT4 are inputted just before the signal of the photodetectors 15, 16 is read, the signal of the photodetectors 11, 13 is read by the CCD31, the signal of the photodetectors 12, 14 is read by the CCD32 and the signal is outputted in the order of photodetector 14 13 12 11.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state image pickup device that prevents uneven output caused by the transfer efficiency of a charge-coupled device.

Currently, -dimensional solid-state image pickup devices having 2,000 to 3,000 photodetectors are manufactured, and charge coupled devices (hereinafter referred to as CCDs) are usually used for readout.

FIG. 1 is a block diagram showing an example of a conventional one-dimensional solid-state image sensor. This example shows an image of 8 pixels for simplicity. In this figure, 11 to 18 are photodetectors, in which a PN junction or a MOS capacitor is used to detect visible light, and a Schottky diode or the like is used to detect infrared light. 21
28 are transfer gates that control charge transfer from the photodetectors 11 to 18 to the COD; in this example, the even numbered photodetectors 12, 14, 16.18 are the even numbered transfer gates) 22 , 24, 26, and 28 to the upper CCD 32, and the odd-numbered photodetector 11
．． 13, 15, 17 are odd numbered transfer gates 2
1,23,25,27'ft and is transferred to the lower CCD 31. The charges transferred to the C0D31゜32 are sequentially multiplexed by a charge detector/preamplifier (hereinafter simply referred to as preamplifier) 40 and are serially connected to one output terminal 5.
Read from 0.

The most important problem with a one-dimensional solid-state image sensor having such a conventional configuration is the transfer efficiency of the CCDs 31 and 32. C.C.
If the transfer efficiency of D31.32 is η, then after N stages of transfer, the first Q. The signal charge Q that was previously becomes Q=Q, η8. Here, if η=0.9999, N=200
At 0, Q/Qo=O182, resulting in a loss of 8% due to CCD transfer. This loss leads to non-uniform output when the average element is correct, and the loss of the normal signal is added to the subsequent output, leading to a reduction in resolution.

The present invention provides a solid-state imaging device that can reduce the number of transfer stages by dividing the output of a COD into a plurality of parts, thereby reducing the problems associated with the transfer efficiency of the above-mentioned normal solid-state imaging device. The present invention will be explained below with reference to the drawings.

FIG. 2 is a clock diagram for explaining one embodiment of the present invention, and FIG. 3 is a clock timing diagram for explaining this operation. For the sake of simplicity, the explanation will be made using an 8-pixel element as in the conventional example. In FIG. 2, the arrangement of photodetectors 11 to 18 and transfer gates 21 to 28 is the same as in the conventional example, but CC
D is divided into 4 parts, 31 to 34, and preamplifiers 41 to 34.
There are also four preamplifiers 44, and the outputs of the preamplifiers 41 to 44 are output in series through a multiplexer 6'0. The multiplexer 60 does not need to be located on the solid-state image sensor chip, and may be configured from an external circuit.

In Fig. 3, φl and φ2 are transfer locks given to CCD31 to 34Vc, and φT1 is transfer lock)25
．． 27K, φT2 is transfer goo) 26.28K
JφT3 is transfer gate 21゜23, φ14
is the transfer gate clock applied to transfer gates 22.24. In this example, 2
This is a case where phase drive COD is used.

Also, odd numbered transfer goo) 21.23゜25
．． It is assumed that the transfer lock φ1 is connected to the gate of 27, and the transfer lock φ2 of the even numbered transfer gates 22, 24, 26, and 28 is connected to the gate.

Note that T is the transfer ptsuk φ1. The period of φ2, Ts is the period of the transfer gate clock φT40.

Next, the operation of this invention will be explained. First, the transfer gate Cronk φ is input, and the photodetector 1
The signal of 5.17 is read out to C0D33. Next, T
, /2, the transfer gate clock φT2 is input, and the signals from the photodetectors 16 and 18 are read and hung on the CCD 34. Next, in accordance with the driving of the C0D 33.34, these signals are applied to the multiplexer 60 through the preamplifiers 43 and 44, and read out from the output terminal 50 to the face corresponding to the signals from the photodetectors 18→17→16→15. At this time, the CCDs 31 and 32 are being driven without any signals. Immediately before the signals from the photodetectors 15 and 16 are read out, the transfer gate clock φT3+4 is activated. is input, and the signal from the photodetector 11.13 is sent to the CCD 31,
The photodetector 12.14+7) signal is read and hung on the CCD 32. Subsequently, as C0D31.32 is driven, the signal is sent to the amplifier 41.42 and the multiplexer 60.
The signals corresponding to the photodetectors 14→13→12→11 are outputted through the photodetectors 14→13→12→11.

With the above operation, the outputs of the photodetectors 11 to 18 are output in order from the right, and video signals for one life can be obtained.

In this example, the storage time and readout time are equal, and the next readout is performed immediately after one readout, but there is no problem if the storage time is longer than the readout time.

FIG. 4 is a lock timing diagram illustrating another embodiment of the invention. The structure of the solid-state image sensor in this case may be the same as that shown in FIG. 2. In this case, all transfer gates 21-28 are provided with the same transfer gate rip φ. Therefore, all pixels perform storage and readout operations simultaneously. CCD transfer p
Tsukφ1. .

φ12 is CCD33, same φ2□, φ23 is CCD
34, same (φ4.φ3□ is CCD31, same φ
48. φ42 drives the CCD 32.

After the transfer gate clock φd is input and the signals are read out to each C0D31 to C0D34, first, the C0D
33 and 34 are driven. At this time, C0D31.32 remains stationary. Next, after the signals of C0D33.34 are read out, C0D31.32 is driven,
The signals are read out in the same order as in the embodiment of FIG.

In this manner, in each of the embodiments described above, the upper and lower CCDs 31 to 34 are divided into two to halve the number of transfer stages.

Therefore, performance deterioration due to transfer efficiency is reduced.

In each of the above embodiments, each of the CCDs 31 to 34 is divided into two parts, but the invention is not limited to this, and the same effect can be obtained if the CCDs are divided into a plurality of parts. In this case, the number of division stages should be determined based on transfer efficiency and performance requirements. Further, in the above description, all of the C0Ds 31 to 34 are driven in two phases, but it goes without saying that they may be driven in single phase, three phases, or four phases.

As explained above, this invention divides the CCD into multiple pieces to reduce the number of transfer stages in order to avoid adverse effects on transfer efficiency in a solid-state image sensor equipped with a plurality of photodetectors arranged in the − dimension. , there is an advantage that the influence of transfer efficiency can be sufficiently reduced even in a solid-state image sensor having a very large number of pixels.

[Brief explanation of the drawing]

Figure 1 is a graphic diagram showing the configuration of a conventional solid-state image sensor.
FIG. 2 is a diagram 1177 showing the configuration of an embodiment of this invention.
FIG. 3 explains the operation of the solid-state image sensor of the present invention.
Figure 4 is a clock timing diagram illustrating the operation of another embodiment of the invention. In the figure, 11 to 18 are photodetectors, 21 to 2B are transfer gates, 31 to 34 are CCDs, 41 to 44 are charge detectors/preamplifiers, 50 is an output terminal, and 60 is a multibunker. Agent Masuo Oiwa (2 others)

Claims (1)

[Claims] (In a solid-state imaging device configured with a plurality of photodetectors arranged in 11 dimensions and a charge-coupled device for sequentially reading out signals from these four photodetectors, A solid-state imaging device characterized in that the charge-coupled device is divided into a plurality of devices, and means is provided for driving outputs from the plurality of charge-coupled devices according to signal readout condyle order. (2) Division Claim (1) characterized in that the transfer gate connecting the photodetector with the charge-coupled device is driven by applying different transfer gate clocks depending on the division of the charge-coupled device. (3) The solid-state image sensor according to claim 1, wherein the divided charge-coupled devices are driven by applying different transfer pulses.