JP3449823B2 - Driving method of solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a solid-state imaging device.
About the law . 2. Description of the Related Art FIG. 7 shows a conventional example of a solid-state imaging device, for example, a CCD linear sensor. As is apparent from FIG.
The CD linear sensor 100 includes a plurality of light receiving units 1 for converting incident light into signal charges having a charge amount corresponding to the light amount and storing the signal charges.
01 are arranged in a line, a read gate unit 103 for reading signal charges from each light receiving unit 101 of the sensor line 102, and a read gate unit 10
3, a CCD charge transfer unit 104 for receiving and transferring the signal charges read out by the CCD charge transfer unit 1;
The charge detection unit 105 is provided at the end of the transfer destination of No. 04 to detect a signal charge and convert the signal charge into a signal voltage, and an output circuit 106 that outputs a signal voltage from the charge detection unit 105. I have. In this CCD linear sensor 100, a read gate pulse φROG is applied via a read pulse input terminal 107 to transfer pulse input terminals 108a and 108b.
, Two-phase transfer pulses φH1 and φH2 are input from outside. The read gate pulse φROG is applied to a gate electrode (not shown) of the read gate unit 103, and the two-phase transfer pulses φH1 and φH2 are applied to transfer electrodes (not shown) of the CCD charge transfer unit 104. The output signal Vout from the output circuit 106 is output to the outside via the output terminal 109. [0004] This type of CCD linear sensor is used by being incorporated in a bar code reader or the like. By the way, in a bar code reader or the like in which a CCD linear sensor is incorporated, a battery is often used as a driving power source, and therefore, low power consumption is desired.
Accordingly, low-voltage driving of the CCD linear sensor has been promoted. As described above, when the CCD linear sensor is driven at a low voltage, the amplitude of the read gate pulse φROG applied to the gate electrode 111 of the read gate unit 103 when the signal charge is read from the light receiving unit 101 in FIG. Since the potential cannot be secured, the potential under the gate electrode 111 cannot be sufficiently deep, and the light receiving portion 101
A potential peak 112 is formed between the charge transfer unit 104 and the charge transfer unit 104. For this reason, the signal charges stored in the light receiving section 101 are not completely transferred to the charge transfer section 104, and a part thereof is blocked by a potential peak 112 shown by a solid line in FIG. It remains in the unit 101.
This remaining signal charge affects the next signal period as an afterimage. That is, when the driving voltage of the CCD linear sensor is simply lowered uniformly, the light receiving unit 101
In this case, the ability to read signal charges from the CCD to the CCD charge transfer unit 104 is impaired, which adversely affects the afterimage characteristics. As a measure to solve such a problem, C
There is a method in which a high-voltage read gate pulse φROG is applied only to the gate electrode 111 of the read gate unit 103 while the drive voltage of the CD linear sensor is reduced. According to this, since the amplitude of the read gate pulse φROG can be sufficiently secured, the potential under the gate electrode 111 becomes sufficiently deep as shown by the dotted line in FIG. Can be solved. However, when this is realized by an external circuit, there are disadvantages such as the necessity of separately preparing a power supply for generating the high-voltage read gate pulse φROG. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to prepare a separate power supply outside in order to solve the problem of transfer residue when reading signal charges from a light receiving section to a charge transfer section. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for driving a solid-state imaging device which can solve the problem without reducing the driving voltage. In order to achieve the above object, the present invention provides a sensor unit, a read gate unit, and a power supply.
A load transfer unit and a booster circuit mounted on the same substrate.
The signal charge accumulated in each light receiving unit of the sensor unit is transferred to a charge transfer unit via a read gate unit having a read gate electrode arranged on the sensor unit side and a transfer gate electrode arranged on the charge transfer unit side. In the solid-state imaging device in which the signal charge is sequentially transferred by the charge transfer unit , the drive voltage is boosted by the booster circuit during the charge accumulation period of the sensor unit and applied to the read gate electrode of the read gate unit. The signal charge photoelectrically converted by the light receiving unit is read and stored in a buffer stage below the signal charge. Then, a predetermined time after the charge accumulation period elapses.
The read gate pulse is read by
And a read gate.
Read gate pulse to transfer gate electrode
In synchronization with the read gate of the read gate unit
By reducing the drive voltage applied to the electrodes,
Transfer the signal charge accumulated in the buffer stage to the charge transfer section
To do it. The signal charges accumulated in each light receiving section of the sensor section are
A solid-state circuit that reads signals to a charge transfer unit via a read gate unit having a read gate electrode disposed on the sensor unit side and a transfer gate electrode disposed on the charge transfer unit side, and sequentially transfers signal charges in the charge transfer unit. In an imaging device, a sensor
Section, readout gate section and charge transfer section on the same substrate
The mounted (so-called on-chip) booster circuit boosts the driving voltage of the solid-state imaging device to generate a high voltage.
Generate internally. By applying a high boosted voltage obtained by the booster circuit to the gate electrode of the read gate portion, the amplitude of the read gate pulse can be sufficiently ensured even when the drive voltage is reduced. Therefore, the signal charges accumulated in the light receiving unit can be read out to the charge transfer unit without leaving the transfer, even if a separate power supply is not provided outside and a high voltage is not taken in. Since the boosting cannot be performed instantaneously, by performing the boosting operation within the charge accumulation period of the sensor section, the voltage applied to the read gate electrode gradually increases during this charge accumulation period. . Then, the signal charge photoelectrically converted by the light receiving unit is gradually read out to the buffer stage below the readout gate electrode, and the readout is completed within the charge accumulation period. As described above, by temporarily storing the signal charges in the buffer stage, it is possible to avoid a jump of charges from the charge transfer unit performing the transfer operation during the charge storage period. Then, a readout gate pulse is applied to the transfer gate electrode at a predetermined timing after the elapse of the charge accumulation period, and the readout gate pulse is applied at the same time.
Applied to the read gate electrode of the read gate
By lowering the driving voltage, the signal charge once accumulated in the buffer stage is transferred to the charge transfer unit. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing one embodiment of the present invention applied to, for example, a CCD linear sensor.
In FIG. 1, a plurality of light receiving units 11 that convert incident light into signal charges having a charge amount corresponding to the light amount are linearly arranged in a row to form a sensor row 12. The signal charge photoelectrically converted by each light receiving unit 11 of the sensor array 12 is read out to the CCD charge transfer unit 14 via the readout gate unit 13. The read gate unit 13 includes a read gate electrode 15 arranged for each light receiving unit 11 on the sensor row 12 side.
And a transfer gate electrode 16 arranged for each light receiving unit 11 on the CCD charge transfer unit 14 side. FIG. 2 shows a specific configuration for one pixel. The CCD charge transfer section 14 receives signal charges read out from the sensor array 12 for each light receiving section 11 by the readout gate section 13 and sequentially transfers the signal charges from right to left in the drawing. At the end of the transfer destination of the CCD charge transfer unit 14, a signal charge transferred by the CCD charge transfer unit 14 is detected and converted into a signal voltage, for example, FD.
Charge detection unit 1 having A (Floating Diffusion Amplifier) configuration
7 are provided. The signal voltage detected by the charge detection unit 17 is supplied to an output circuit 18 including a source follower circuit and the like. The CCD linear sensor 10 having the above configuration includes:
The read gate pulse φROG1 is transferred via the read pulse input terminal 19 to the transfer pulse input terminals 20a and 20b.
, Two-phase transfer pulses φH1 and φH2 are input from outside. The read gate pulse φROG1 is applied to the transfer gate electrode 16 of the read gate unit 13 once in one signal period (time during which the charge transfer unit 14 completes the transfer of the signal charges for one line), and the two-phase transfer pulse φH is applied.
1 and φH2 are applied to a transfer electrode (not shown) of the charge transfer unit 14 during the charge accumulation period of the light receiving unit 11. The output signal Vout from the output circuit 18 is output to the outside via the output terminal 21. The sensor array 12, the read gate unit 1
3. A boosting operation is performed on the same substrate as the charge transfer unit 14 and the like based on, for example, two-phase transfer pulses φH1 and φH2 having opposite phases to each other, and the boosted voltage is read by the read gate electrode 15 of the read gate unit 13. -Pump type booster circuit 2 for applying a read gate pulse φROG2 to the
2 are provided. Here, the two-phase transfer pulse φH
1, φH2 is input only during the charge accumulation period of the light receiving unit 11. As a result, in the charge pump booster circuit 22, the boost operation is performed during the charge accumulation period of the light receiving section 11. FIG. 3 shows an example of the configuration of the charge pump type booster circuit 22. In this example, a three-stage configuration is shown, but the present invention is not limited to this, and a multi-stage configuration of two or four or more stages may be used. In FIG.
Between the power supply Vdd and the circuit output terminal 31, three diode-connected boosting MOS transistors Q1, Q2, and Q3 whose gates and drains are commonly connected are connected to the power supply Vdd.
Are connected in series in the forward direction from the side toward the circuit output end 31 side. The second-stage MOS transistor Q2
A transfer pulse φH1 is applied to the common connection point between the source of the third stage and the drain (gate) of the third-stage MOS transistor Q3 via the inverter 32 and the capacitor C1,
The source of the first-stage MOS transistor Q1 and the second-stage M
A transfer pulse φH2 is applied to a common connection point with the drain (gate) of the OS transistor Q2 via the inverter 33 and the capacitor C2. A load capacitor CL is connected between the circuit output terminal 31 and the ground, and a reset MOS transistor Q4 is connected in parallel to the load capacitor CL. A read gate pulse φROG1 is applied to the gate of the reset MOS transistor Q4 via inverters 34 and 35 cascaded in two stages. Thereby, the charge of the load capacitor CL is reset. Then, a pulse voltage obtained by boosting the drive voltage (voltage of the power supply Vdd) by three times is obtained as the read gate pulse φROG2 at the circuit output terminal 31, and the read gate pulse φROG2 is applied to the read gate electrode 15 of the read gate unit 13. You. Next, the boosting operation of the charge pump type boosting circuit 22 having the above configuration will be described with reference to the timing chart of FIG. In the following description of the operation, for the sake of simplicity, the threshold V of the boosting MOS transistors Q1 to Q3 will be described.
The explanation is made ignoring th. First, the light receiving unit 11
The read gate pulse φROG1 at the “H” level is supplied to the inverter 3
The charge is applied to the gate of the reset MOS transistor Q4 via the gates 4 and 35, and when the MOS transistor Q4 is turned on, the charge of the load capacitor CL is reset, and the voltage of the read gate pulse φROG2 becomes zero. When shifting from this state to the charge accumulation period,
The transfer pulse φH1 and the “L” level (0 level), which have been fixed at the “H” level (Vdd level) until then.
The transfer pulse φH2, which has been fixed to, starts an inversion operation at a constant period. During the charge accumulation period, when the transfer pulse φH1 is first inverted to the “L” level, this is inverted by the inverter 32 to become a pulse of the peak value Vdd, and is transferred to the load capacitor via the capacitor C1 and the boosting MOS transistor Q3. Charge CL. Then, even if the transfer pulse φH1 is inverted and becomes “H” level, the transfer pulse φH2 of the opposite phase becomes “L” level, and this is inverted by the inverter 33 to become a pulse of the peak value Vdd,
Capacitor C2 and boosting MOS transistor Q2
The charging of the load capacitor CL is continued via Q3. Therefore, in the first cycle, the peak value of the read gate pulse φROG2 becomes Vdd. In the next cycle, the transfer pulse φH1 goes low again.
When the level is inverted, the level is inverted by the inverter 32 and superimposed on the source voltage Vdd of the boosting MOS transistor Q2, thereby charging the load capacitor CL with a voltage of 2Vdd. Then, even if the transfer pulse φH1 is inverted and goes to “H” level, the transfer pulse φH2 goes to “L” level. Therefore, the transfer pulse φH2 is inverted by the inverter 33 to become a pulse of the peak value Vdd, which is boosted via the capacitor C2. Superimposed on the source voltage Vdd of the MOS transistor Q2, and continues to charge the load capacitor CL via the boosting MOS transistor Q3. Therefore, in the second cycle, the peak value of the read gate pulse φROG2 is 2 Vd
d. When the transfer pulse φH1 is again inverted to the “L” level in the next cycle, this is inverted by the inverter 32 and the source voltage 2 of the boosting MOS transistor Q2 is inverted.
By being superimposed on Vdd, the load capacitor CL is charged with a voltage of 3 Vdd. Then, even if the transfer pulse φH1 is inverted and goes to “H” level, the transfer pulse φH2 goes to “L” level, and this is inverted by the inverter 33 to become a pulse of the peak value Vdd, which is boosted via the capacitor C2. Source voltage of MOS transistor Q2
Superimposed on dd, the charge of the load capacitor CL is continued via the boosting MOS transistor Q3. Therefore,
In the third cycle, the peak value of the read gate pulse φROG2 is 3 Vdd. By the above-described boosting operation, the drive voltage Vdd of the CCD linear sensor 10 is gradually increased during the charge accumulation period, and can finally be increased to about three times. The 3 Vdd read gate pulse φRO thus obtained
G2 is the read gate electrode 1 of the read gate unit 13.
5 is applied. As described above, the drive voltage Vd of the CCD linear sensor 10 is
The operation when reading out the signal charge of the light receiving unit 11 to the CCD charge transfer unit 14 using the read gate pulse φROG2 by internally generating a high-voltage read gate pulse φROG2 by boosting the potential d in FIG. This will be described with reference to the drawings. In FIG. 5, the operation modes (A),
The potentials of (B) and (C) correspond to A, B, and C in FIG.
2 respectively show potential distributions at the cross section taken along line AA 'in FIG. First, in the operation mode (A), the read gate pulse φROG2 obtained by gradually increasing the voltage in the charge accumulation period in the charge pump type booster circuit 22 is applied to the read gate electrode 15, so that the read gate pulse 15 The potential of the buffer stage gradually becomes deeper. Accordingly, signal charges obtained by photoelectric conversion in the light receiving section 11 are read out to the buffer stage below the readout gate electrode 15. At this time, since the read gate pulse φROG1 applied to the transfer gate electrode 16 of the read gate unit 13 is at the “L” level, the potential below the transfer gate electrode 16 is shallow. Therefore, signal charges read from the light receiving unit 11 to the buffer stage below the read gate electrode 15 are accumulated in the buffer stage. Next, in the operation mode (B), when the read gate pulse φROG1 of “H” level is applied to the transfer gate electrode 16 of the read gate section 15, the potential under the transfer gate electrode 16 becomes deeper. At the same time, when the read gate pulse φROG2 becomes 0 V, the potential of the buffer stage below the read gate electrode 15 becomes shallower. Thus, the signal charges accumulated in the buffer stage are transferred below the transfer gate electrode 16. Next, in the operation mode (C), the read gate pulse φR
When OG1 is inverted to the “L” level, the potential under the transfer gate electrode 16 becomes shallow, and the signal charge under the transfer gate electrode 16 is finally transferred to the charge transfer unit 14. As described above, the CCD linear sensor 10
In the above, the booster circuit 22 is mounted on the same substrate, and the booster circuit 22 boosts the drive voltage Vdd to generate a read gate pulse φROG2 of a high voltage (3 Vdd in this example), which is output to the read gate unit. 1
3 is applied to the readout gate electrode 15 so that a high voltage can be taken in from the outside to generate a high-voltage readout gate pulse φROG2 without having to generate a high-voltage readout gate pulse φROG2.
, The signal charges can be completely read out to the charge transfer unit 14. This makes it possible to drive the CCD linear sensor 10 at a low voltage without preparing a separate power supply outside and applying a special voltage or preparing a special input terminal. Although the boosting operation of the boosting circuit, particularly the boosting operation of the charge pump type boosting circuit 22, requires time, the boosting operation of the read gate pulse φROG2 is performed within the charge accumulation period of the light receiving section 11. As a result, the signal charge photoelectrically converted by the light receiving unit 11 is read out to the buffer stage below the readout gate electrode 15 with the rise of the readout gate pulse φROG2, and the readout operation is performed simultaneously with the end of the charge accumulation period. Since the process is completed, there is no need to provide a special time for reading the signal charges from the light receiving unit 11. In order to perform the boosting operation of the read gate pulse φROG2 within the charge accumulation period of the light receiving section 11,
In the present embodiment, two-phase transfer pulses φH1 and φH for driving the charge transfer unit 14 are used as two-phase drive pulses of opposite phases to drive the charge pump type booster circuit 22.
2 was used. According to this, the transfer pulses φH1, φH2
Is a pulse that performs an inversion operation only during the charge accumulation period, so that there is no need to perform any signal processing such as timing control on the transfer pulses φH1 and φH2, and there is an advantage that it can be used as it is. However, the two-phase drive pulses of the charge pump type booster circuit 22 are not limited to the transfer pulses φH1 and φH2 of the CCD charge transfer unit 14. For example, it is also possible to use a master clock for an internal timing generation circuit (not shown) that generates various timing signals, or a pulse generated by the internal timing generation circuit. In this case, it is necessary to add a circuit for generating two-phase pulses having phases opposite to each other based on a master clock or the like.
The circuit configuration is slightly more complicated than when H2 is used. Further, the read gate section 13 is provided with the read gate electrode 15 and the transfer gate electrode 16, and the read gate section 13 has a two-stage gate structure. The signal charge of the charge transfer section 14 is
Function as a barrier to prevent the stored signal charges from being mixed into the buffer stage below the buffer stage. In other words, during the charge accumulation period, the transfer operation is performed in the charge transfer unit 14, and the signal charges during the transfer are read out by the read gate electrode 15.
Can be prevented from jumping into the buffer stage below. As a result, even if the signal charges are read from the light receiving unit 11 during the charge accumulation period, there is no fear that a problem such as color mixing occurs. In the above embodiment, the case where a multi-stage charge pump type booster circuit using two-phase driving pulses is used as the booster circuit is described. However, the present invention is not limited to this. It is also possible to use a one-stage charge pump type booster circuit using a single-phase drive pulse as shown. Hereinafter, a specific circuit configuration of the one-stage charge pump type booster circuit will be described. In FIG. 6, the read gate pulse φR
OG1 is composed of five cascaded inverters 61-65.
To one input of the NAND gate 66, and further to the MO through three inverters 67 to 69 connected in cascade.
The voltage is applied to the drain of the S transistor Q61 and becomes one input of the NAND gate 70. The read gate pulse φROG1 is further supplied directly to the NAND gate 6
6 and 70 as well as an inverter 7
It is inverted by 1 and becomes the gate input of the MOS transistor 62. The output of NAND gate 66 is inverted by inverter 72 and becomes the gate input of MOS transistor Q61. The source of the MOS transistor Q61 is
Connected to the drain of S transistor Q62, the source of MOS transistor Q62 is grounded. The common source / drain connection point of the MOS transistors Q61 and Q62 is connected to the circuit output terminal 73. Circuit output terminal 73
Is connected to one end of a load capacitor CL. The other end of the load capacitor CL has a NAND gate 70
Are inverted by an inverter 74 and applied. By using the charge pump type booster circuit having the above configuration, the drive voltage Vdd can be boosted to almost twice the voltage. However, when the drive voltage Vdd of the CCD linear sensor is further reduced, the use of the charge pump type booster circuit of FIG. 6 limits the boosting to twice the voltage, so that the read gate pulse φROG
2 cannot be sufficiently secured. From this point of view, the multi-stage charge pump type booster circuit of FIG. 3 can increase the number of stages freely, so that the drive voltage Vdd of the CCD linear sensor can be sufficiently reduced even further. There are advantages that can be accommodated. In the above embodiment, the case where the present invention is applied to a linear sensor has been described. However, the present invention is not limited to this. The present invention can be similarly applied to an area sensor in which light receiving portions are two-dimensionally arranged. . As described above, according to the present invention,
In the solid-state imaging device, the signal charges accumulated in each light receiving unit of the sensor unit are read out to the charge transfer unit via the readout gate unit, and the signal transfer unit sequentially transfers the signal charges.
By applying a boosted voltage obtained by boosting the drive voltage to the gate electrode of the readout gate section, the charge transfer section can be transferred from the light receiving section to the internally generated readout gate pulse without taking in a high voltage from the outside. Since the signal charge can be completely read out, prepare another power supply externally,
The device can be driven at a low voltage without applying a special voltage or preparing a special input terminal. Further, in a solid-state imaging device having a read gate portion provided with a read gate electrode provided on the sensor portion side and a transfer gate electrode provided on the charge transfer portion side, a drive voltage is applied during a charge accumulation period of the sensor portion. By applying the voltage to the read gate electrode of the read gate unit while boosting the voltage, the signal charge photoelectrically converted by the light receiving unit is read and stored in the buffer stage below it, and the read pulse is read at a predetermined timing after the elapse of the charge storage period. By applying the signal charge accumulated in the buffer stage to the charge transfer unit by applying the voltage to the transfer gate electrode of the gate unit,
Even if it takes time to boost the voltage, it is possible to complete the reading of the signal charge from the light receiving section within the charge accumulation period, and prevent the signal charge from the charge transfer section from being mixed into the read signal charge. It is possible to read out the signal charges in a short period of time and reliably while preventing color mixing or the like due to the mixing of.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram showing one embodiment of the present invention. FIG. 2 is a configuration diagram illustrating a specific example of one pixel around a readout gate unit; FIG. 3 is a circuit diagram illustrating an example of a charge pump type booster circuit. FIG. 4 is a timing chart for explaining a boosting operation; FIG. 5 is a potential diagram for describing a read operation of a signal charge; FIG. 6 is a circuit diagram showing another example of the charge pump type booster circuit. FIG. 7 is a configuration diagram showing a conventional example of a CCD linear sensor. FIG. 8 is a potential diagram for explaining a conventional problem. [Description of Signs] 10 CCD linear sensor 11 Light receiving section 12 Sensor row 13 Readout gate section 14 CCD charge transfer section 15 Readout gate electrode 16 Transfer gate electrode 17 Charge detection section 22 Charge pump type booster circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04N 1/024-1/207

Claims (1)

(57) [Claim 1] A sensor unit in which a plurality of light receiving units for arranging a plurality of light receiving units for converting incident light into signal charges having a charge amount corresponding to the amount of light and storing the signal charges are provided. A read gate for reading signal charges from each light receiving unit; a charge transfer unit for transferring signal charges read from each light receiving unit of the sensor unit by the read gate unit ; a sensor unit, the read gate unit; Charge transfer
A booster circuit mounted on the same substrate as the transfer unit , wherein the read gate unit includes a read gate electrode disposed on the sensor unit side and a transfer gate electrode disposed on the charge transfer unit side In the imaging device, the photoelectric conversion is performed in each light receiving unit of the sensor unit by applying a drive voltage to the read gate electrode of the read gate unit while boosting a driving voltage by the boosting circuit during a charge accumulation period of the sensor unit. The read signal charges are read and stored in a buffer stage below the read signal charges, and a read gate pulse is applied to a transfer gate electrode of the read gate unit at a predetermined timing after the elapse of the charge storage period , and the transfer of the read gate unit is performed. Game
Synchronized with the application of the read gate pulse to the
Reading from the read-out gate unit from the booster circuit
A driving method, wherein a signal charge accumulated in the buffer stage is transferred to the charge transfer unit by lowering a drive voltage applied to a gate electrode .