JPS6028373A - Decoder of picture signal - Google Patents

Abstract

PURPOSE:To reduce the time when a coded data is inputted until the data is used for recording and to eliminate the need for a memory and its control circuit by using a memory for restoration in common use with a memory for reference and also using instantly the data restored once as a recording data. CONSTITUTION:When a coded picture signal is inputted to a decoding circuit, the decoding circuit 6 references an output R of a shift register 10 so as to decode a coded picture signal inputted by a known method thereby applying a decoded picture data to the shift register 10. The picture signal decoded sequentially is being stored in the shift register 10. When a counter 12 counts the picture signal having the picture element number for one line's share, the output latches the picture signal stored in the shift register 10. The picture signal latched in the latch 11 is recorded on a recording paper sheet by a recording section 13. The next coding picture signal is fed to the shift register 10 similarly as above in parallel with the recording processing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for decoding and reproducing encoded signals such as facsimile, and in particular, to a device that decodes and reproduces a coded signal such as a facsimile. The present invention relates to an image signal decoding device that reproduces an input encoded signal.

(b) Technical background Reproduction transmission technology or image processing (optical character reading processing)
In the field of technology, encoding for encoding read images, code compression, and band compression.

Decoding techniques are generally known. In such encoding and decoding technology, when compressing a signal for each unit scanning line, the changes from the image signal obtained from the previous scan are usually encoded, and when decoding, the changes from the image signal obtained from the previous scan are encoded. A so-called two-dimensional compression technique is used to further improve the compression efficiency by using a signal to decode and reproduce an encoded signal to be decoded.

(C) Prior Art FIG. 1 is a diagram for explaining a conventional decoding device for a two-dimensionally compressed image signal. In the figure, 1 to 3 are memories; 4.
5 is a selector circuit (hereinafter referred to as a selector), 6 is a restoration circuit, and 7 and 8 are counters.

9 is a control section.

Each memory 1, 2.3 has a unit scanning line.

In other words, it has a capacity equal to the number of pixels obtained when scanning a document on which an image is recorded once, and each scan line image of the unit in which the encoding and signal to be decoded are decoded.
a restoration memory having a function of storing an image signal; a reference memory having a function of storing a previously restored image signal used for decoding this image signal;
It is used as a recording memory that has the function of storing stored image signals for recording. Also, each memory 1
゜2.3 uses selector 4.3 to increase its usage efficiency.
5, the function requires a memory with a capacity corresponding to the number of pixels for at least 3 lines,
Although it is large-sized and can be output for recording, it has the disadvantage that a poem is required from the time it is restored until the image for the next line is restored.

(dl) Purpose of the Present Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks of the conventional art and to provide an image signal decoding device that is compact and capable of high-speed recording.

<111) Structure of the Invention In order to achieve the above object, the present invention focuses on the fact that the readout amount of the reference image signal and the output amount of the restored image (image signal) are the same and at the same timing. The above-mentioned restoration memory and reference memory are also used, and once restored data is immediately used as recording data, and will be described in detail below with reference to embodiments. .

(f) Embodiment FIG. 2 is a block diagram of an embodiment of the present invention. Components in the figure that are the same as those shown in FIG. 1 are designated by the same numbers. It is controlled to switch sequentially.

Explain the operation.

First, selector 4□5 selects memory 1 as recording memory, memory 2 as reference memory, and memory 3 as memory 3.
are respectively allocated as restoration memory.

That is, the image signal read out from the memory 1 is sent to the selector 5.
is supplied to a recording unit such as a printer (not shown) via
The image signal read from the memory 2 is supplied to the decoding circuit 6 as a reference image signal via the selector 5. Further, the memory 3 is supplied with sequentially decoded image signals from the decoding circuit 6 via the selector 4 . The decoding circuit 6 is supplied with the encoded image signal and the reference image signal and outputs a decoded (restored) image signal.

The counter 7 counts the number of restored image signals (the number of pixels), and when the number of pixels for one line is counted, the control unit 9
emits output to .

On the other hand, in parallel with this, the above-mentioned decoding process is performed in parallel from the memory 1 used as a recording memory at the recording timing of the recording device (not shown), which is different from the output timing of the image signal of the decoding circuit 6. The already restored image signal is output via the selector 5.

The number of pixels of this output image signal is counted by a counter 8. The counter 8 issues an output when image data corresponding to the number of pixels for one line is read out. The control unit 9 receives outputs from the counters T and 8 that count pixels for one line and switches the selectors 4 and 5, thereby setting the memory 1 as the restoration memory and the memory 2 as the recording memory. Furthermore, the memory 3 can be used as a reference memory.

Thereafter, in the same manner as described above, this circuit operates to sequentially read the recorded image signal and the reference image signal from each memory 2.3 and supply the restored image signal to the memory 1. Furthermore, when the recording output and restoration input are completed in this state, the selector 4.5 sets the memory 1 as the reference memory and sets the memory 2 as the reference memory.
is used as the restoration memory, and the memory 3 is switched so that it can be used as the recording memory, and the same process is repeated.
The encoded image signal input to the selector 5 is outputted as a final G-recordable image signal.

(a) Conventional disadvantages The conventional decoding device described above outputs a restored image signal. Also, 10 is a shift register that stores an image signal corresponding to one line of pixels, and 11 is a launch circuit. (hereinafter referred to as U-Nochi), 12 is a counter, 1
3 is a recording section.

The counter 12 counts the timing t output from the decoding circuit 6 every time one pixel is decoded, and when the count value becomes equal to the number of pixels for one line, the latch 11 stores the shift register 10. It outputs a signal that latches the stored signal and also resets itself.

Furthermore, the shift register 10 transfers the image signal P at a timing t.
, the image signal is shifted in at timing t, and a reference image signal R is output.

Explain the operation.

When the encoded image signal is input to the decoding circuit 6, the decoding circuit 6 refers to the output R of the shift register 10, restores the input encoded image signal using a known method, and restores it to the shift register 10. image data. Thereafter, the restored image signals are sequentially stored in the shift register 10. When the counter 12 counts image signals corresponding to the number of pixels for one line, its output causes the latch 11 to latch the image signal stored in the shift register 10. The image signal latched by the latch 11 is recorded by the recording section 13 on recording paper (not shown). In parallel with this recording process, the next encoded image signal is sent to the shift register 10.
is supplied in the same manner as described above.

In the above embodiment, a shift register in which one pixel is outputted from the output every time one pixel is input was explained as the shift register means, but the present invention is not limited to this, and for example, one line of A memory having a capacity equivalent to the number of pixels may be used.

In this case, a so-called write pointer (counter) indicating the write address written in this memory and a continuation pointer (counter) indicating the read address are provided, so that the address indicated by the read pointer exceeds the address indicated by the write pointer. Conventional controls are required, such as those that do not exist.

Further, in the above embodiment, the reference image signal used when decoding the image signal of one pixel is a signal corresponding to one pixel, but the reference image signal is not limited to this, and the write pointer as described above is used. , when using a read pointer, as long as the number of signals read from the memory does not become less than the number of signals written, and the number already read for one line of signals does not become less than that number of signals. For example, it is also possible to use a plurality of already stored decoded reference image signals.

(hl Effects of the Invention As described above, according to the present invention, the one-line shift register means is used both as a reference memory and a restoration memory, so a memory and its control circuit are not required, and It is also possible to shorten the time from when encoded data is input until it is provided for recording.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional decoding device, and FIG. 2 is a block diagram of an embodiment of the present invention. In the figure, 6 is a decoding circuit, and 10 is a shift register. 11 is a latch circuit, 12 is a counter, 13 is a recording section j
Figure A2 Figure 2

Claims (1)

[Claims] Shift register means for storing an image signal representing an image of a unit scanning line; a coded signal encoded in accordance with the image signal stored in the shift register means; and an image signal stored in the shift register means. are sequentially input, the code decodes the signal according to the image signal, and a decoding means supplies the decoded image signal to the shift register means; 1. A decoding device for an image signal, comprising means for reproducing and outputting an image for each image signal of a scanning line.