JPH0484521A - Data compression and expansion circuit - Google Patents

Abstract

PURPOSE:To attain compression processing of two sets of data information or over each different from one line with one data compression circuit by writing any of plural coded data stored in a storage section to a register section so as to compress a picture data different from each prescribed length. CONSTITUTION:A reference line and a coded line by one line each in a picture 'a' are fetched in a buffer 11 and a buffer section 3 and data compression processing is implemented by a compression circuit 4 based on each line data. The data compressed by the compression circuit 4 is outputted to a register section 5, in which a code output is implemented in the timing when an inputted data reaches 8 bits. When the compression processing by one line of the picture 'd' is finished, information of a bit counter 5b and a shift register 5a is stored in an external memory 9. Thus, the compression processing of two sets of data information or over each different from one line is implemented with one data compression circuit.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 5) (Fig. 1) Working examples 1 Embodiment (Figure 2) Second embodiment of the present invention (Figure 3) Effects of the invention [Summary] Regarding the data compression/expansion circuit, in one data compression/expansion circuit, ■ 2 different lines for each line.
Data compression/expansion processing for the above data information
The purpose is to provide a decompression circuit, which includes a buffer section that stores data of two or more different pieces of information for a predetermined length, and a compression section that compresses and encodes the data stored in the no/sofa section. a circuit, a register section that reads and temporarily holds the data encoded by the compression circuit, and outputs the data when the data reaches a predetermined amount; a data compression means having a storage section that stores a plurality of pieces of encoded data per unit, writes any of the plurality of encoded data stored in the storage section into the register section, and compresses different image data for each predetermined length. It is configured to do this.

It also includes a storage unit that stores a plurality of pieces of coded data obtained by compressing data of two or more different pieces of information in units of a predetermined bit width, and a storage unit that reads out and temporarily holds the coded data and stores it once the data reaches a predetermined amount. a register section that outputs the data to the next stage at a timing; an expansion circuit that expands the encoded data held in the register section and restores it to the original data; a data decompression means having a buffer section for storing data, and is configured to write any of the plurality of encoded data stored in the storage section into the register section, and to decompress different data every predetermined length. are doing.

[Industrial Field of Application] The present invention relates to a data compression/decompression circuit, and more specifically, the present invention relates to a data compression/decompression circuit that is suitable for use in the field of facsimile machines, etc., and is capable of handling data in a compact manner in order to reduce memory consumption. related to data compression/decompression circuits.

In recent years, facsimile machines that handle very large amounts of information, such as image data made up of raster data, require a huge amount of memory capacity for data processing if the large data is used in its original form. However, since it takes a long time to transfer the data, it is not practical to use the image data in its original form. Therefore, many data compression/expansion circuits have been developed to enable compact handling of image data.

This data compression/decompression circuit compresses large data to make it smaller, performs necessary processing on the smaller compressed data, such as data transfer, and then decompresses the data when it is used again in the form of light. The data is restored by performing the following steps, thereby reducing the memory capacity for data processing.

The methods for compressing and decompressing image data can be roughly divided into two types: ■ MH (mod Hied
Huffman) method, ■MR (modified relative
ve element address design
ate) method, ■MMR that two-dimensionally encodes all information
There are several methods, and the compression ratio of image data increases in the order of ■, ■, and <■.

Among these, the basic principle of MH Ho 2 is explained based on Attached Table 1. For example, if one line of black and white two-tone image data read by a reading unit of a facsimile machine, etc.
White 10. Black 9. White 7. Assuming that black is composed of pixels of 6°..., these data are preset white and
Based on Black's table, White 5 is 1100 and Black 4 is 01.
1, white 3 is converted to 1000, black 2 is converted to 11, and compressed data is generated. By this, the original 00000000
001111111110000000111111 and 32 bit image data becomes 00111000100
It is compressed by 13 bits: 11110010.

Therefore, encoded data generally has a variable length in order to perform the above-described processing.

Note that the decompression operation is accomplished by a process that is the reverse of the compression operation.

Both MH and MR encoding systems are used for code compression in the CCITT's GI facsimile standard, and in such G
Although it is possible to transmit and receive the compressed code by the H, MR method, the compression rate by the MH, MR method is low.
Even if the data is compressed using the MR method, the amount of data handled within the facsimile machine is still large.

That is, for example, as shown in FIG. 4, taking the case of sending a document as an example, in an actual facsimile machine, in order to further compress the amount of data, when the document is read, two MMR methods are used. Dimensional encoding compression is performed. Two-dimensional encoding uses the line before the line to be compressed (hereinafter referred to as the encoded line) as a reference line, and uses this reference line and the encoded This code encodes parts that differ from the line. Predetermined internal processing is performed in a state where memory is saved to the maximum by compression of two-dimensional encoding using the MMR method, and when data is transmitted, this compressed data is decompressed using the MMR method, and the MH
, which is compressed and transmitted using the MR method.

Therefore, in a facsimile machine equipped with such a data compression/expansion circuit, for example, if you are trying to send a document and another document is already being received, it is necessary to compress/decompress two or more lines at the same time. There is.

(Prior Art) Conventionally, as such a data compression/expansion circuit, there is one shown in FIG. 5, for example.

The data compression/decompression circuit for each is roughly divided into data compression means 1 and data decompression means 2. Data compression means 1 comprises a buffer section 3, compression circuit 4, and register section 5, and data decompression means 2 consists of , register section 6, expansion circuit 7,
It is composed of a buffer section 8.

When compressing an image, the image data accumulated in the buffer section 3 is compressed and encoded by the compression circuit 4.
The encoded data is read out to the register section 6. Generally, data processing is often performed in units of 1 hide, that is, 8 bits, so when expanding data onto memory, the register section 6 has a bit size that is an integral multiple of 8 (in this case, 8 bits). It has become. Therefore, the data read into the register section 6 is temporarily held until it reaches 8 bits, and the compressed encoded data is output as a code at the timing when the data reaches 8 bits.

When decompressing an image, the compressed encoded data is read out and temporarily held by the register section 6, and as in the case of compression, the encoded data is transferred to the next stage decompression circuit 7 when the data becomes 8 bits worth. is output to. The encoded data output from the register section 6 is decompressed by the decompression circuit 7 and restored to the original image data, and the decompressed image data is outputted via the buffer section 8, which is a process completely opposite to image compression. Expansion is performed at

[Problems to be Solved by the Invention] However, in such a conventional data compression/expansion circuit, a register section 6 is provided inside the data compression/expansion circuit, and data is stored in this register section 6 all at once. Since the configuration is such that the data is output from the register unit 6 to the outside when the - Unable to perform decompression processing.

This is because the data encoded by the above-mentioned MH, MR, and MMR methods has a variable length, so the encoded data may have a number of bits that is not evenly divisible by 8 (in the case of the conventional example). , 1947 minutes of image data is completed, and if, for example, 3-bit encoded data remains in the register unit 6, if compression processing of other image data is performed in this state, the register unit 6 This is because the newly generated data will be added to the remaining 3 bits of data, and the image data will be meaningless even if it is restored by decompression processing.

By the way, with a facsimile machine equipped with such a data compression/expansion circuit, for example, when you try to send a document, if another document is already being received, the telephone line is busy, so the device When data information to be transmitted is stored in the internal memory and retransmitted after a predetermined period of time, or when data information in the stored memory is being transmitted while another document is being scanned. When performing an operation, it is necessary to perform compression/expansion processing on two or more lines at the same time.

However, with conventional data compression/decompression circuits, it was not possible to compress/decompress other image data until the compression/decompression process of one image data was completed.
This problem was addressed in the following way.

■Compression and expansion processing was performed for each image data.

2) A plurality of data compression/expansion circuits as shown in FIG. 5 were provided, and one data compression/expansion circuit was used for each image data.

However, in the conventional example (2), there is a problem in that a large amount of memory is required to perform compression and expansion processing once one piece of image data is complete.

In addition, in the conventional example (2), processing is performed line by line, so processing can be performed with the minimum necessary memory, but it requires multiple sets of data compression/expansion circuits, so the circuit configuration is There was a problem that it became complicated and led to an increase in cost.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data compression/expansion circuit that performs compression/expansion processing of two or more pieces of data information that are different for each line using a single data compression/expansion circuit.

[Means for Solving the Problems] In order to achieve the above object, the data compression/expansion circuit according to the present invention, as shown in the principle diagram in FIG. a buffer unit 3 that stores data in a predetermined amount; a compression circuit 4 that compresses and encodes the data stored in the buffer unit 3;
a register unit 5 that reads and temporarily holds encoded data and outputs the data when the data reaches a predetermined amount; and a register unit 5 that stores a plurality of pieces of encoded data in the register unit 5 in units of a predetermined bit width. The apparatus includes a data compression means 1 having a storage section 9, writes any of a plurality of encoded data stored in the storage section 9 to the register section 5, and compresses different image data for each predetermined division. It is configured as follows.

It also includes a storage unit 10 that stores a plurality of encoded data obtained by compressing data of two or more different pieces of information in units of a predetermined bit width; a register unit 6 that outputs the data to the next stage at the same timing; and an expansion circuit 7 that expands the encoded data held in the register unit 6 and restores it to the original data.
and a /N sofa section 8 for storing the data restored by the decompression circuit 7 in a predetermined amount.
The configuration is such that any one of the plurality of encoded data stored in the storage section 9 is written into the register section 5, and different data is expanded every predetermined length.

[Operation] In the present invention, by writing any of a plurality of pieces of encoded data stored in the storage unit into the register unit, different image data is compressed/expanded for each predetermined length.
Two or more pieces of data information that differ line by line are compressed and expanded by one data compression/expansion circuit.

Therefore, only one data compression/decompression circuit is required,
The circuit configuration is simplified, and costs for memory and the like are also reduced.

〔Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 2 is a diagram showing a first embodiment of the data compression/expansion circuit according to the present invention. In this diagram, the same numbers as in the principle diagram shown in FIG. 1 indicate the same or corresponding parts.

The register sections 5 and 6 of this embodiment are respectively composed of shift registers 5a and 6a and bit counters 5b and 6b. The shift registers 5a and 6a output the input data in multiples of 8 bits, and the bit counters 5b and 6b output the input data in multiples of 8 bits.
, 6a is used to count the number of data bits input to 6a.

Further, the storage units 9 and 10 of this embodiment use external memories, and the shift registers 5a and 6 are controlled by a control means (not shown).
By reading and writing the contents of a and the focus counters 5b and 6b, the encoded data held in the shift registers 5a and 6a and the bit counters 5b and 6b and the plurality of pieces of data stored in the storage unit 9.10 are It is possible to selectively exchange any of the encoded data.

Note that the buffer LL12 performs compression and compression using two-dimensional encoding.
This is used to import reference line data to be referred to during decompression processing.

Next, the operation will be explained by taking as an example the case where two image data of images "'α" and "β" are compressed.

First, the shift register 5a and the bit counter 5b
The contents of are cleared and initialized. And the image “′
The reference line and encoded line for one line of α' are taken into the buffer 11 and the buffer unit 3, and data compression processing is performed by the compression circuit 4 based on the respective line data. The data compressed by the compression circuit 4 is
The code is output to the register unit 5, and the code is output at the timing when the input data reaches 8 bins 1-min.

At the time when the compression process for one line of the image "α" is completed, the information of the focus counter 5b and the shift register 5a is stored and held in the external memory 9. In this case, since the data encoded by the compression process has a variable length, there may be cases where data remains in the shift register 5a at the time when the compression process for one line of the image pattern α'' is completed. be.

When the information is stored in the external memory 9, the contents of the shift register 5a and the focus counter 5b are cleared and initialized again. Then, the reference line and encoded line for one line of the image "β" are taken into the buffer 11 and the buffer section 3, and data compression processing is performed by the compression circuit 4 based on the respective line data. When the compression process for one line of the image β pattern is completed, the information in the bit counter 5b and the shift register 5a is stored and held in the external memory 9. When the information is stored and held in the external memory 9, the shift register 5a and the bit counter 5b are cleared, and the information in the shift register 5a stored in the external memory 9 is shifted again when the compression processing for one line of the image ゛'α゛° is completed by the previous processing. The data is written to the register 5a, and then data compression for 1547 portions of the image "α" is performed.

Thereafter, by repeating this operation, it is possible to compress two or more pieces of image data that are different every several lines.

Note that the decompression process is performed by the reverse process of the compression process, so its explanation will be omitted.

FIG. 3 is a diagram showing a second embodiment of the data compression/expansion circuit according to the present invention. In this figure, the same numbers as in the first embodiment shown in FIG. 2 indicate the same or corresponding parts.

The storage units 9 and 10 of this embodiment include shift registers 5a and 6a, bit counters 5b, and
Shift registers 9a, 9c, 10a, same as 6b,
10c, bit counter 9b, 9d, 10b,
10d and a register selection circuit j3, and by the register selection circuit 13, the shift registers 5a, 6a,
and bit counters 5b, 6b, (1) shift I registers 9a, 10a and bit counters 9b, 10b of storage units 9.10, (2) shift registers 9c, 10c and bit counters 9d, 10d of storage units 9, 10.

Switching control is performed so that one of the two becomes active.

That is, the image "α" is similar to the first embodiment.

Taking the case of compressing two image data "'β"' as an example, and explaining the operation, the contents of the shift register 5a and bit counter 5b are cleared and initialized.Then, the image "' When the compression process for one line of α"° is completed, the register selection means 13 switches the bit counter that takes in the output data from the compression circuit 4 and the shift register to 9a and 9b. Then, the next image "°" When the compression process for one line of "β" is completed, the register selection means 13 switches the bit counter that takes in the output data from the compression circuit 4 and the shift register to 5a and 5b again.
By repeating this operation, it is possible to compress two or more pieces of image data that are different for each line or several lines, as in the first embodiment.

In this way, in this embodiment, by selectively exchanging the encoded data held in the register section with any of a plurality of encoded data stored in the storage section, different image data for each line can be created. Can be compressed and expanded.

Therefore, one data compression/expansion circuit can compress/expand two or more pieces of data information that differ from each other line by line.

In the above embodiments, processing of two different types of image data has been described, but in the first embodiment, the address of the external memory is changed, and in the second embodiment, the processing of the storage unit 9.
By increasing the number of shift registers and bit counters to 10, it is possible to perform data compression/expansion processing on two or more pieces of image data.

〔Effect of the invention〕

According to the present invention, one data compression/expansion circuit can compress/expand two or more pieces of data information that differ one line at a time.

Therefore, the circuit configuration can be simplified and the cost of memory and the like can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the data compression/expansion circuit of the present invention, Figs. 2 and 3 show the data compression/expansion circuit of the invention, and Fig. 2 is a block diagram showing the overall configuration of the first embodiment. , Fig. 3 is a block diagram showing the overall configuration of the second embodiment, Fig. 4 is a diagram illustrating the flow of data compression/expansion operations of a facsimile machine, and Fig. 5 is a conventional data compression/expansion diagram. FIG. 2 is a block diagram showing the overall configuration of the circuit. 1... Data compression means, 2... Data decompression means, 3... Buffer section, 4... Compression circuit, 5.6...・Register part, 5a 6a...Shift register, 5b 6b・
...Bit counter, 7...Expansion circuit, 8...Buffer section, 910...Storage section, 9a, 9c, 10a, 10c...-・Shift register, 9b 9d, 10b, 10d...Focus counter, 1L12...Buffer, 13...Register selection circuit.

Claims (1)

[Claims] (1) A buffer unit (3) that stores data of two or more different pieces of information for a predetermined length, and compresses and encodes the data stored in the buffer unit (3). a compression circuit (4) for reading out and temporarily holding data encoded by the compression circuit (4), and outputting the data when the data reaches a predetermined amount; a storage section (9) for storing a plurality of encoded data of the section (5) in units of a predetermined bit width; A data compression circuit characterized in that the data is written in the register section (5), and different data is compressed every predetermined length. (2) a storage unit (10) that stores a plurality of encoded data obtained by compressing data of two or more different pieces of information in units of a predetermined bit width; A register unit (6) that outputs the data to the next stage at the timing when the data becomes quantitative; and an expansion circuit (7) that expands the encoded data held in the register unit (6) and restores it to the original data. , a data decompression means having a buffer section (8) for accumulating a predetermined length of data restored by the decompression circuit (7), and which one of the plurality of encoded data stored in the storage section (10) A data decompression circuit, characterized in that the data is written in the register section (6), and different data is decompressed every predetermined length. (3) A data compression/expansion circuit comprising the data compression circuit and the data expansion circuit. (4) The data compression/expansion circuit according to claim 3, wherein the storage section is an external memory that reads and writes the contents of the register section according to a predetermined control signal. (5) The storage section includes a plurality of registers that hold data of the same length as the register section, and selects one of the registers and stores the encoded data held in the register section and the encoded data in the storage section. 4. The data compression/expansion circuit according to claim 3, further comprising a register selection circuit for exchanging a plurality of encoded data.