KR960005686Y1 - Address signal generator of jpeg decoder - Google Patents

Abstract

None.

Description

Address generation circuit in JPEG decoder

Figure 1 is a block diagram of a JPEG decoder

2 is an 8, 8-block pixel data output flow chart of the IDCT processor.

3 is an address generating circuit diagram of a JPEG decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

FF1 ~ 3: flip flop AND1 ~ 5: AND gate

OR1,2: OA gate 1,2: logic operation part

3: count

The present invention relates to an address generating circuit for storing output data of an Inverse Discrete Cosine Transform (IDCT) processor of a Joint Photographic Expert Group (ISO / CCITT Recommendation) codec in a memory. In the address generator circuit of the JPEG decoder which can generate the lower 3 bits of the row address and column address so that 8 blocks of data can be stored in arbitrary 8, 8 blocks in the memory in order. It is about.

In general, the JPEG method divides pixel data composing one screen into 8,8 block units, converts and quantizes DCT (Discrete Cosine Transform) for each 8,8 block unit, converts to digital data, and decodes the variable length. Compressed and transmitted, the receiving side is to obtain the original video signal through the reverse process of the above process.

A typical JPEG decoder used at the receiving side of the JPEG system as described above is a FIFO (31: First-In First-Out) storing compressed image data received from the other party's JPEG system, as shown in FIG. And a variable length decoder 32 for decoding the compressed image data output from the FIFO 31 into variable lengths and quantizing the data into 8, 8 block units, and the variable length decoder 32. An inverse quantization unit 33 for inversely quantizing the output signal of the inverse signal and outputting the DCT coefficients, an IDCT processor 34 for restoring the output signal of the inverse quantization unit 33 to pixel data, and the IDCT processor 34 Memory unit 35 for storing the pixel recovery data output from the "

Therefore, when the image data received from the other JPEG system is stored in the FIFO 31, the data is restored to the original data in the compressed form in the variable-length decoder 32 to the original data, and the inverse quantizer 33 The DCT coefficient obtained after inverse quantization of the corresponding data is converted into pixel data in units of 8 and 8 blocks by the IDCT processor 34 and stored in the memory unit 35.

Here, the output of the IDCT processor 34 continuously obtains 8, 8 block units of data in 64 serial bitstreams, and a flow chart in which the bitstreams are output is shown in FIG.

That is, pixel data of 8,8 block units output from the IDCT processor 34 is stored in the memory unit 35 in the numerical order as described in FIG. ) Reads and reads the corresponding data stored in the memory unit 35 in the order shown in FIG.

However, in the above-described conventional method, the IDCT processor 34 must simultaneously perform an operation of restoring the output signal of the inverse quantization unit 33 to pixel data and an operation of addressing the pixel data to magnetic field in the memory unit 35. do. For example, 640,840 pixels are required to construct a NTSC screen. The IDCT processor 34 processes such a large amount of pixel data in software and addresses the memory unit 35 by addressing the data. Since the storing operation must be performed in parallel, the IDCT processor 34 takes a lot of load, resulting in a problem that the overall data processing efficiency is lowered.

An object of the present invention for solving the above problems is to generate a row address and column address of the lower 3 bits of the memory unit in order to address the pixel data output from the IDCT processor in the memory unit in order to replace the memory in place of the IDCT processor. The present invention provides an address generator circuit in a JPEG decoder that performs an operation of addressing a unit to reduce a load of an IDCT processor.

The present invention for achieving the above object is a FIFO for storing the compressed image data received from the other party's JPEG system; A variable length decoder for decoding the compressed image data output from the FIFO into variable lengths and quantizing the data into 8, 8 block units; An inverse quantizer for outputting a DCT coefficient by inversely quantizing the output signal of the variable length decoder; An IDCT processor for restoring the output signal of the inverse quantization unit to pixel data; A JPEG decoder comprising a memory unit for storing pixel reconstruction data output from the IDCT processor, wherein the first clock signal having a predetermined frequency is input to a synchronization signal input terminal and the second clock signal inverted the first clock signal is cleared. First to third flip-flops which are inputted to the data input terminal at the time when the operation is possible and output one bit of the lower three bits of the low address to be applied to the memory unit; A first logic operation unit which receives the normal output signals and the inverted output signals of the first to third flip-flops and performs a logic operation to output the data input terminals of the second flip-flop; A second logic operation unit which receives the normal output signals and the inverted output signals of the first and third flip-flops and performs a logic operation to output the data to the data input terminals of the third flip-flop; A sixth AND gate which receives the normal output signal of the first flip-flop, the inverted output signal of the second flip-flop, and the inverted output signal of the third flip-flop, and outputs the result of the AND operation; And a counter configured to receive the output signal of the sixth AND gate into the synchronization signal input terminal, and output the lower 3 bits of the column address generated by the counting operation by receiving the second clock signal to the clear terminal to the memory unit. It is done.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is an address generation circuit diagram of a JPEG decoder according to the present invention, in which a first clock signal having a predetermined frequency is input to a synchronization signal input terminal CK, and an inverted signal CK 'of the first clock signal is hereinafter referred to as a second clock. A signal) is inputted to the clear stage CL, and the data inputted to the data input terminal D is output at the time of operation, and each bit of the low address 3 bits R2 to R0 is outputted to the memory unit 35; The first to third flip-flops FF1 to 3, the normal output signals A, B, and C and the inverted output signals of the first to third flip-flops FF1 to 3 applied to the side of FIG. A ', B', C '), and a logic operation to input the data input terminal D of the second flip-flop (FF2) and the first logical operation unit 1, and the first and third flip-flop The normal output signals A and C and the inverted output signals A 'and C' of (FF1, 3) are inputted and logically processed to the data input terminal D of the third flip-flop FF3. A second logic operation unit 2, a normal output signal A of the first flip-flop FF1, an inverted output signal B 'of the second flip-flop FF2, and the third flip-flop. The sixth AND gate AND6, which receives the inverted output signal C ′ of FF3, and performs a logical multiplication on the output signal C ′, and the output signal of the sixth AND gate AND6 is inputted to the synchronization signal input terminal CK. The counter 3 is configured to receive the two clock signals CK 'to the clear terminal CK and perform a counting operation so as to form the lower three bits C2 to C0 of the column addresses of the memory unit 35.

In the above configuration, the first logic operation unit 1 receives the inverted output signals A 'and B' of the first and second flip-flops FF1 and 2, and outputs the first AND gate. (AND1) and a second AND gate that receives and logically multiplies and outputs the inverted output signal B 'of the second flip-flop FF2 and the normal output signal C of the third flip-flop FF3. AND2, the normal output signal B of the second flip-flop FF2, the inverted output signal C 'of the third flip-flop FF3, and the normal output signal of the first flip-flop FF1 ( The data input terminal D of the second flip-flop FF2 is formed by performing a logical OR on the third AND gate AND3 for receiving and logically multiplying A) and the output signals of the first to third AND gates AND1 to 3. It consists of the 1st OR gate OR1 output to.

In addition, the second logic operation unit 2 of the above-described configuration receives the inverted output signal (A ', C') of the first, third flip-flops (FF1, 3) and the fourth to output the logical multiplication An AND gate AND4, a fifth AND gate AND5 that receives and outputs ANDs the normal output signals A and C of the first and third flip-flops FF1 and 3, and outputs the AND gate AND4. The second orifice OR2 outputs the output signals of the AND gates AND4 and 5 to the data input terminal D of the third flip-flop FF3.

In addition, the inverted output signal A 'of its own output signal is input to the data input terminal D of the first flip-flop FF1.

Referring to the effect of the present invention configured as described above are as follows.

First, since the second clock signal CK 'is input to the clear terminal CL before the predetermined clock pulse is input to the registered signal input terminal CK, the output terminals of the plurality of flip-flops FF1 to 3 and the counter 3 are provided. In both cases, the 'low' signal is output, and the row and column addresses R2 to R0 and C2 to C0 applied to the memory unit 35 (refer to FIG. 1) become '000'.

At this time, since the 'high' signal is output from the inverted output signals A 'to C' of the first to third flip-flops FF1 to 3, the 'high' signal at the first and fourth AND gates AND1 and 4 is output. Is output. Therefore, the outputs of the first and second orifices OR1 and 2 are all high, and the high signal is input to the data input terminal D of the first to third flip-flops FF1 to 3.

Therefore, when the first clock pulse CK is input thereafter, the normal output signals A, B, and C of the first to third flip-flops FF1 to 3 are all inverted to output the high signal. The row addresses R2 to R0 applied to 35 are '7' which is a '111' state.

In this case, a 'low' signal is applied to the data input terminal D of the first flip-flop FF1, and the outputs of the first to third AND gates AND1 to 3 and the first oragate OR1 are also 'low'. 'Low' signal is also applied to the data input terminal D of the second flip-flop FF2, and the output signal of the fourth AND gate AND4 is in the 'low' state or the fifth end gate ( Since the output of AND5 is 'high', the output of the second OA gate OR2 becomes 'high', and a 'high' signal is applied to the data input terminal D of the third flip-flop FF3.

Therefore, when the second clock signal is input, the normal output signals A and B of the first and second flip-flops FF1 and 2 are converted to a low state, but the normal output of the third flip-flop FF3 is output. The signal C maintains the 'high' state so that the row addresses R2 to R0 applied to the memory unit 35 become the '001' state.

Thereafter, as the output signals of the first to third flip-flops FF1 to 3 change, the output signal state of the first and gate AND1 is 'high', and the fourth and fifth endgates AND4 and 5 are respectively. The output signal states of are all converted to 'low', and the 'low' signal is applied only to the data input terminal D of the third flip-flop FF3.

Therefore, when the third clock pulse CK is input, the row addresses R2 to R0 applied to the memory unit 35 are outputted with '6' having a '110' state.

Since the output signal of the third AND gate AND3 becomes 'high' as the normal output signal of the first to third flip-flops FF1 to 3 becomes '6', the output of the first oragate OR1 is 'high'. Is in the 'high' state, and the outputs of the fourth and fifth AND gates AND4 and 5 and the second oragate OR2 are all 'low', so that the first to third flip-flops FF1 to 3 Data input stages are 'low', 'high' and 'low' respectively.

Therefore, a fourth time, when the clock pulse is input, the low output address R2 to R0 applied to the memory unit 35 is '010', that is, the normal output signal of the first to third flip-flops FF1 to 3 is '2'. 'High' signal is applied to the data input terminal of the first flip-flop FF1, and the outputs of the first to third AND gates AND1 to 3 and the first OR gate OR1 are 'low'. Since a 'low' signal is applied to the data input terminal of the second flip-flop FF2, and the output of the fourth AND gate AND4 becomes' high ', the output of the second orifice OR2 is' Becomes high, and a 'high' signal is applied to the data input terminal of the third flip-flop FF3.

Therefore, when the fifth clock pulse is input, the row addresses R2 to R0 output from the output terminals A to C of the first to third flip-flops FF1 to 3 to the memory unit 35 are '101'. That is, since '5' is output, a 'low' signal is input to the data input terminal of the first flip-flop FF1 and the output of the second AND gate AND2 is supplied to the data input terminal of the second flip-flop FF2. Since the signal is in a 'high' state, 'high', which is an output of the first oragate OR1, is input.

In addition, since the output signal of the fifth and gate AND5 is 'high', the 'high', which is the output of the second oracle OR2, is input to the data input terminal of the third flip-flop FF3.

Thereafter, when the sixth clock pulse is input, the row addresses R2 to R0 output from the output terminals A to C of the first to third flip-flops FF1 to 3 to the memory unit 35 become '011'. As a result, a 'high' signal is applied to the data input terminal of the first flip-flop FF1 and the output signal of the first to third AND gates AND1 to 3 is 'low'. At the gate OR1, a signal having a 'low' state is output and input to the data input terminal of the second flip-flop FF2.

In addition, since the output signals of the fourth and fifth AND gates AND4 and 5 are 'low', the signal of the 'low' state is output from the second oragate OR2 to form the third flip-flop FF3. It is entered at the data input stage.

Therefore, when the seventh clock pulse is input, the outputs A through C of the first to third flip flops FF1 to 3 are in a '100' state, and thus, the data input terminal of the first flip flop FF1. Since the 'low' signal is applied and the output signal of the first to third AND gates AND1 to 3 is 'low' state, the first ora gate OR1 outputs a 'low' state signal to the second signal. It is input to the data input terminal of the flip-flop FF2.

In addition, since the output signals of the fourth and fifth AND gates AND4 and 5 are 'low', the signal of the 'low' state is output from the second oragate OR2 to form the third flip-flop FF3. It is entered at the data input stage.

Therefore, when the eighth clock signal is input, the outputs of the first to third flip-flops FF1 to 3 are all low, and the row addresses R2 to R0 applied to the memory unit 35 are '000'. The above operation is repeated for subsequent clock pulses.

That is, the row addresses R2 to R0 output to the memory unit 35 are 000 (0) ⇒ 111 (7) ⇒ 001 (1) ⇒ 110 (6) 010 (2) ⇒ each time a clock pulse is input. The cycle is repeated in the order of 101 (5) → 011 (3) ⇒100 (4).

On the other hand, the counter 3 is a sixth end gate that becomes 'high' whenever a 'high' signal is output from the output terminals A, B 'and C' of the first to third flip-flops FF1 to 3. The output signal of AND6 is inputted as a clock pulse to perform a counter. At this time, the column addresses C0 to C2 applied to the memory unit 35 from the output terminals QA to QC of the counter 3 are 000. (0) ⇒001 (1) ⇒010 (2) ⇒011 (3) ⇒100 (4) ⇒101 (5) ⇒110 (6) ⇒111 (7) The memory unit 35 can be addressed.

As described above, according to the present invention, a plurality of logic gates, flip-flops, and counters can store 8, 8 blocks of IDCT processor output data in arbitrary 8, 8 blocks of a memory unit in order of output. Since the row address and column address can be generated, the load on the IDCT processor due to the addressing operation of the memory unit by the IDCT processor can be reduced, thereby improving the overall data processing efficiency of the JPEG system.

Claims (4)

(Twice correction) The FIFO 31 storing the compressed image data received from the JPEG system of the other party and the decoded image data output from the FIFO 31 are decoded to variable length into 8, 8 block units of data. A variable length decoder 32 for quantization; An inverse quantization unit 33 for inversely quantizing the output signal of the variable length decoder 32 to output a DCT coefficient; An IDCT processor 34 for restoring the output signal of the inverse quantization unit 33 to pixel data; In the JPEG decoder having a memory unit 35 for storing pixel reconstruction data output from the IDCT processor 34, The first clock signal having a predetermined frequency is input to the synchronization signal input terminal CK, the second clock signal inverting the first clock signal is input to the clear terminal CL, and is input to the data input terminal D at an operable time point. First to third flip-flops (FF1 to 3) for outputting data to be output, and outputting one bit of the lower address lower 3 bits to the memory unit 35; A first logic operation unit which receives the normal output signal and the inverted output signal of the first to third flip-flops FF1 to 3 and performs a logic operation to output the data to the data input terminal D of the second flip-flop FF2 (1); A second logic operation unit which receives the normal output signals and the inverted output signals of the first and third flip-flops FF1 and 3 and performs a logic operation to output them to a data input terminal D of the third flip-flop FF3 (2); A sixth AND gate which receives and outputs the normal output signal of the first flip-flop FF1, the inverted output signal of the second flip-flop FF2, and the inverted output signal of the third flip-flop FF3, and outputs the result of the logical multiplication. (AND6); The memory unit outputs the lower three bits of the column address generated by the output signal of the sixth AND gate AND6 to the synchronization signal input terminal CK, and the counting operation by receiving the second clock signal to the clear terminal CL. And a counter (3) output to the (35) side. (Correction) The method according to claim 1, The first logic operation unit (1) includes: a first AND gate (AND1) for receiving an AND output of the inverted output signals of the first and second flip-flops (FF1, 2) and outputting the result; A second AND gate (AND2) which receives the inverted output signal of the second flip-flop (FF2) and the normal output signal of the third flip-flop (FF3) and outputs the result of the logical multiplication; A third AND gate that receives and outputs the AND output signal of the second flip-flop FF2, the inverted output signal of the third flip-flop FF3, and the normal output signal of the first flip-flop FF1. And a first or gate OR1 configured to logically combine the AND3 and the output signals of the first to third AND gates AND1 to 3 to output to the data input terminal D of the second flip-flop FF2. An address generating circuit in a JPEG decoder, characterized in that. (Correction) The method according to claim 1, The second logic operation unit 2 includes a fourth AND gate AND4 for receiving the AND output signals of the first and third flip-flops FF1 and 3 and performing logical multiplication on the inverted output signals; A fifth AND gate (AND5) which receives and outputs AND outputs the normal output signals of the first and third flip-flops (FF1, 3); And a second orifice OR2 for ORing the output signals of the fourth and fifth AND gates AND4 and 5 to the data input terminal D of the third flip-flop FF3. Address generation circuit in JPEG decoder. (Correction) The address generating circuit according to claim 1, wherein an inverted output signal of its own output signal is input to a data input terminal (D) of the first flip-flop (FF1).