JPH08167856A - Decoding circuit for run length code - Google Patents

Abstract

PURPOSE: To provide a highly efficient run length decoding circuit capable of corresponding to a picture element clock signal with high frequency at real time. CONSTITUTION: After initializing all data words stored in a 1st scan converting RAM 131a to '0', only a code-added level data word is overwritten on a position '0' in the RAM 131a which is specified by a zigzag scanning address based upon a zero run length data word. Thus one block stored in a 2nd scan converting RAM 131b is read out and initialized during the writing of only non-zero components out of 84m8 components constituting one block in the RAM 131a. During the writing of only non-zero components of the succeeding block in the RAM 131b, one block stored in the RAM 131a is read out and initialized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a run length code decoding circuit.

[0002]

2. Description of the Related Art As an international standard for compression and expansion of moving image data, it is generally called MPEG2 (Moving Picture Image) under the name of ISO / IEC working group.
An international standard called Coding Experts Group Phase 2) is known. According to MPEG2, moving image data is divided into blocks of size 8 × 8 pixels or macroblocks of size 16 × 16 pixels, and data processing is performed in block units or macroblock units.

An image encoder for compressing moving image data conforming to MPEG2 is a DCT (Discrete Cosin).
The main components are an e Transform (discrete cosine transform) circuit, a quantizer, an RLC (Run Length Coder), and a VLC (Variable Length Coder). The DCT circuit converts data in the spatial domain into data in the frequency domain in block units. This transformation aims at uneven distribution of non-zero coefficients having a relatively large value in the low frequency region by utilizing the property that most of the energy is generally concentrated in the low frequency region in a natural image. ing. The quantizer utilizes the fact that the human visual sensitivity to the high frequency range is lower than that to the low frequency range, and more coarsely quantizes the high frequency coefficient of the result of the DCT circuit. As a result, most of the coefficients having small values in the high frequency range are converted into zero components. The RLC scans the result of the quantizer in a zigzag manner so that the zero components are easily concatenated, and calculates a zero run length data word representing the number of zero components preceding each nonzero component and the value of the nonzero component. And generating a data stream having a plurality of data sets composed of a level data word and a level data word. This run length encoded data stream is variable length encoded by VLC by using a table of Huffman codes.

Here, the RL in the image encoder is
The data processing of C will be described with reference to the examples shown in FIGS. FIG. 5 shows 8 × 8 components QF [v] [u] (0 ≦ v ≦, which form one block immediately after quantization.
7, 0 ≦ u ≦ 7) is shown. According to the rule regarding the order of the zigzag scanning shown in FIG. 6, 8 × 8 in FIG.
While scanning each component, pairs of zero run length data words and level data words (data words relating to non-zero components) are sequentially obtained. Reference numbers 1-2 in FIG.
1 indicates 21 pairs of data words obtained,
These correspond to 63 AC (alternating current) coefficients of the result of the DCT circuit. D at the position of v = 0 and u = 0
The data word corresponding to the C (DC) coefficient is code number 0
Further, the EOB (End of Block) code is shown by the code number 22, respectively. The EOB code indicates that there are no non-zero components in the result of the quantizer thereafter. According to FIGS. 5 to 7, the result of the quantizer is 1
The 8 × 8 components that form one block include one data word corresponding to the DC coefficient in the result of RLD and AC.
It is compressed into 21 pairs of data words corresponding to the coefficients and the EOB code.

On the other hand, the image decoder for reproducing the original moving image data corresponds to the above image encoder,
VLD (Variable Length Decoder), RLD (Run Length Decoder), inverse quantizer, IDCT (Inverse Disc)
The main components are a rete cosine transform circuit and an inverse discrete cosine transform circuit.

FIG. 4 shows the RL in the conventional image decoder.
An example of the circuit configuration of D is shown together with the VLD in the preceding stage. The decoding circuit of FIG. 4 has a VLD 201, a 1-bit latch 210, a first data latch 211, a down counter 212 with a data preset, a second data latch 221, an address counter 223, and a lookup table 226. And scan conversion RAM (Ranmom Acc
ess Memory) 232. The bit lengths of the first data latch 211, the down counter 212, and the second data latch 221 are 16, 8 and 16, respectively. The variable length coded data stream supplied via the data input terminal 200 is supplied to the VLD 201. The clock signal 202 is distributed to the 1-bit latch 210, the first data latch 211, the down counter 212, the second data latch 221, and the address counter 223 for the synchronous operation of the decoding circuit. It is also supplied to the VLD 201 via the mask circuit 203 and the signal line 204.

When the variable length code of the DC coefficient is applied to the data input terminal 200, the VLD 201 supplies a block start signal indicating the start of one block to the signal line 205. Further, when the variable length code of the AC coefficient is given to the data input terminal 200, the VLD 201 sends a zero run length data word representing the number of zero components preceding the nonzero component to the signal line 207 and outputs the zero run component of the nonzero component. A level data word representing an absolute value is supplied to the signal line 208, and 1-bit information specifying whether the non-zero component is positive or negative is supplied to the signal line 209. The decoding result related to the DC coefficient is supplied to the signal lines 208 and 209 as level data. Further, the VLD 201 supplies an EOB detection signal to the signal line 206 when the variable length code related to EOB is given to the data input terminal 200.

Upon receiving the block start signal on the signal line 205, the address counter 223 receives the clock signal 202.
The count value is sequentially incremented from the initial value “0” in synchronism with, and the count value is supplied to the signal line 224 as a linear address. When the count value reaches “63 (decimal notation)”, the address counter 223 sets the pulse signal indicating the end of the block as the block end signal to the signal line 225.
Supply to The RS flip-flop 228 connected to the VLD 201 and the address counter 223 holds the signal line 229 at the “L” level in the initial state, and when receiving the EOB detection signal on the signal line 206, the signal line 22.
9 is set to "H" level, and when the block end signal on the signal line 225 is received, the signal line 229 is reset to "L" level.

The look-up table 226 has the address conversion table shown in FIG. 8 corresponding to the zigzag scan of FIG. 6, and converts a linear address on the signal line 224 into a zigzag scan address corresponding to the linear address, and outputs the zigzag scan address. The scan address is supplied to the signal line 227. The zigzag scan address on the signal line 227 is given to the scan conversion RAM 232 as a write address.

The zero run length data word on signal line 207 is to the down counter 212, the level data word on signal line 208 is to the first data latch 211, and the 1-bit information on signal line 209 is to the 1-bit latch 210. ,
Each is taken in synchronization with the clock signal 202.
The down counter 212 counts down the preset zero-run length data word in synchronization with the clock signal 202 until it becomes “0”. During this counting operation, the signal line 213 of the down counter 212 is "H".
As a result of being fixed to the level, the mask circuit 203 becomes VLD2.
01 to prevent the clock signal 202 from propagating to VLD2
01 holds the states of the signal lines 207, 208 and 209. On the other hand, the level data word taken in by the first data latch 211 is passed through the signal line 215 and the 1-bit information taken by the 1-bit latch 210 is taken by the signal line 214.
And is supplied to the positive / negative value switching unit 216 via each. LEVEL the level data word on signal line 215
(N), and the 1-bit information on the signal line 214 is S (n)
(When n = 0 to 21 in the example of FIG. 7), the positive / negative value switching unit 216 determines If S (n) = 0 then SLEVEL (n) = LEVEL (n) (1) If S (n) = 1 then SLEVEL (n) = (-LEVEL (n)) ... (2) Signed level data word SLEVEL (n)
And outputs the signed level data word to the signal line 218.
Supply to

During the counting operation of the down counter 212, the other signal line 217 of the down counter 212 is also fixed to the "H" level, and as a result, the signals on the two signal lines 217 and 229 are input as two inputs. The NOR circuit 230 fixes the selection signal on the signal line 231 to the “H” level. The multiplexer 219, which has been supplied with the “H” level selection signal on the signal line 231, supplies the fixed data word “0” to the signal line 220. When the count value of the down counter 212 becomes "0", the signal lines 213 and 217 become "L" level. As a result, the VLD 201 supplies the decoding result of the next variable length code to the signal lines 207, 208 and 209, and the multiplexer 219 supplies the signed level data word on the signal line 218 to the signal line 220. When the variable length code related to EOB is applied to the data input terminal 200, the VLD 201 supplies the EOB detection signal to the RS flip-flop 228 as described above, and as a result, the multiplexer 219 again outputs the fixed data word “0” to the signal line 2.
20 will be supplied. As described above, the signal line 2
The fixed data word “0” and the signed level data word supplied onto the 20 are taken into the second data latch 221 in synchronization with the clock signal 202. The data words sequentially taken in by the second data latch 221 are given as write data to the scan conversion RAM 232 via the signal line 222. As a result, a series of data words are sequentially written in the scan conversion RAM 232 at the positions designated by the zigzag scan address on the signal line 227, and are composed of 8 × 8 components as shown in FIG. One block is the scan conversion RAM 23
Restored in 2. Then, the scan conversion RAM 2
The 8 × 8 components of 32 are sequentially supplied to the dequantizer of the next stage through the data output terminal 234 by the reading means (not shown).

[0012]

As described above, the conventional RLD processes one block regardless of the number of non-zero components among the 8 × 8 components forming one block. Requires 8 ² clock pulses in the clock signal 202.

On the other hand, according to the so-called 4: 2: 0 format, the macroblock of the size of 16 × 16 pixels in the color moving image has four blocks relating to the luminance signal Y and two relating to the color difference signals Cb and Cr. It is composed of a total of 6 blocks including individual blocks. Each block is composed of 8 × 8 data elements. That is, according to the conventional RLD described above, 6 representing a macroblock having a size of 4 × 8 ² pixels is represented.
Clock signal 2 for run length decoding of × 8 ² components
It requires 6 × 8 ² clock pulses in 02. Therefore, the frequency of the clock signal 202 is required to be 1.5 times or more the frequency of the pixel clock signal.

This is because if the frequency of the pixel clock signal is about 13.5 MHz as in the main profile (MP @ ML) at the main level corresponding to the resolution of the current television system among the 11 kinds of specifications of MPEG2. , There is no particular problem. This is because it is possible to easily prepare a system clock signal having a frequency of about 54 MHz, which is four times that in consideration of other conditions.

However, in the case of the main profile (MP @ H1440) at the high 1440 level and the main profile (MP @ HL) at the high level of MPEG2 corresponding to the HDTV (High Definition Television) system having a higher resolution than the current television system. However, since the frequency of the pixel clock signal is a high frequency exceeding 40 MHz, it is difficult to realize real-time run-length decoding with the above-mentioned conventional RLD.

It is an object of the present invention to provide a highly efficient run length decoding circuit capable of responding to a high frequency pixel clock signal in real time.

[0017]

In order to achieve the above object, according to the present invention, all the data words stored in the scan conversion RAM are initialized to "0" in advance, and the scan conversion RAM is To overwrite the “0” inside,
Only the level data word is written in the corresponding position in the scan conversion RAM based on the zero run length data word. The write address of the level data word to the scan conversion RAM is
It is generated by an adder for calculating a linear address and a look-up table for converting the linear address into a zigzag scan address.

Particularly, when the scan conversion RAM is composed of two dual-port RAMs, the data word stored in the other dual-port RAM during the writing period of the level data word into one of the dual-port RAMs. Are read out and initialized. in this case,
Conveniently, the data word is initialized immediately after reading it.

Further, when the scan conversion RAM is composed of three single-port RAMs, the other one single-port RAM is written in the writing period of the level data word in any one single-port RAM. The reading of the stored data word and the initialization of the data word stored in the other single port RAM are performed.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of the circuit configuration of an RLD (run length code decoder) according to the present invention, which is the V circuit in the preceding stage.
It is shown together with LD (variable length code decoder). The decoding circuit of FIG. 1 includes a VLD 101 and a first data latch 10
8, the second data latch 109, and the 1-bit latch 1
10, a third data latch 115, an address adder 119, a lookup table 122, a read address generation circuit 124, an initialization address generation circuit 127, a first scan conversion RAM 131a, and a first scan conversion RAM 131a. It has a pipeline configuration including two scan conversion RAMs 131b. The first and second scan conversion RAMs 131a and 131b are dual port RAs, respectively.
It is composed of M. The address adder 119 and the look-up table 122 constitute the write address generation circuit 118. First data latch 10
The bit lengths of 8, 8, the second data latch 109, and the third data latch 115 are, for example, 8, 16, and 16, respectively. The variable-length coded data stream supplied via the data input terminal 100 is a VLD 101.
Supplied to The clock signal 102 is supplied to the first data latch 108, the second data latch 109, the 1-bit latch 110, the third data latch 115, and the address adder 119 for the synchronous operation of the decoding circuit. To be distributed. Further, the clock signal 102 is directly supplied to the VLD 101.

When the variable length code of the DC coefficient is applied to the data input terminal 100, the VLD 101 outputs a block start signal indicating the start of one block to the clock signal 1.
The signal is supplied to the signal line 103 in synchronization with 02. Also, VLD
101 is a variable length code of the AC coefficient is the data input terminal 10
When given to 0, a zero run length data word representing the number of zero components preceding non-zero components is provided on signal line 105.
To the signal line 106, the level data word representing the absolute value of the non-zero component, and 1-bit information specifying whether the non-zero component is positive or negative to the signal line 107 are respectively synchronized with the clock signal 102. And supply. The decoding result related to the DC coefficient is used as the level data in the signal lines 106 and 107.
Supplied to Further, when the variable length code related to EOB is given to the data input terminal 100, the VLD 101 outputs EO.
The B detection signal is synchronized with the clock signal 102 and the signal line 10
Supply to 4.

The zero run length data word on signal line 105 is in the first data latch 108 and the level data word on signal line 106 is in the second data latch 109.
The 1-bit information on the signal line 107 is the 1-bit latch 110.
Respectively, in synchronization with the clock signal 102. The zero run length data word captured in the first data latch 108 is supplied to the signal line 113.
The level data word taken in by the second data latch 109 is transferred to the 1-bit latch 110 via the signal line 111.
The 1-bit information taken in is supplied to the positive / negative value switching unit 112 via the signal line 135. Positive / negative when the level data word on the signal line 111 is LEVEL (n) and the 1-bit information on the signal line 135 is S (n) (n = 0 to 21 in the example of FIG. 7). The value switching unit 112 calculates the signed level data word SLEVEL (n) according to the equations (1) and (2), and supplies the signed level data word to the signal line 114. The signed level data word on signal line 114 is
The third data latch 11 is synchronized with the clock signal 102.
Taken in 5. The signed level data word captured in the third data latch 115 is supplied to the signal line 116.

The address adder 119 receiving the block start signal on the signal line 103 initializes the held linear address to "0" in synchronization with the clock signal 102, and sends the linear address to the signal line 121. Supply. Also,
The address adder 119 sets the held linear address as LADDR (n−1) and the zero run length data word on the signal line 113 as RUN (n) (FIG. 7).
In the example, n = 1 to 21. ), Clock signal 102
In synchronism with LADDR (n) = LADDR (n-1) + RUN (n) +1 (3), a new linear address LADDR (n) is calculated and held. This new linear address is also
It is supplied to the signal line 121. Also, the address adder 11
9 is the first selection signal on the signal line 120a and the signal line 12
It has a function of setting either one of the second selection signal on 0b to the “H” level and the other to the “L” level, each time the EOB detection signal on the signal line 104 is received. The logic levels of the first and second selection signals are inverted.

The look-up table 122 has the address conversion table shown in FIG. 8 corresponding to the zigzag scan of FIG. 6, converts the linear address on the signal line 121 into the corresponding zigzag scan address, and outputs the zigzag scan address. The scan address is supplied to the signal line 123.

When the first selection signal on the signal line 120a is at the "H" level, the read address generation circuit 124 sends the signal to the signal line 125b and the second selection signal on the signal line 120b is at the "H" level. If the level is the signal line 125a
The read address is supplied to each. Signal line 125
The read address on a is the first scan conversion RAM
131a and the read address on the signal line 125b is given to the second scan conversion RAM 131b. The first according to the read address on the signal line 125a
The data word read from the scan conversion RAM 131a is output to the first data output terminal 134a through the signal line 1
The data word read from the second scan conversion RAM 131b according to the read address on 25b is supplied to the second data output terminal 134b. Further, the same read address as that of the signal line 125a is supplied to the signal line 126a, and the same read address as that of the signal line 125b is supplied to the signal line 126b.

When the read address is supplied to the signal line 126a, the initialization address generation circuit 127 supplies the same address as the read address to the signal line 128a as the initialization address at a slightly delayed timing. Further, when the read address is supplied to the signal line 126b, the initialization address generation circuit 127 supplies the same address as the read address to the signal line 128b as an initialization address at a slightly delayed timing.

First and second scan conversion RAM 13
Around the 1a and 131b, first and second data multiplexers 129a and 129b and first and second address multiplexers 132a and 132b are provided. The first data multiplexer 129a outputs the signed level data word on the signal line 116 when the first selection signal on the signal line 120a is at "H" level, and the first selection signal at "L". Signal line 1 if level
Fixed data word “0” on 17
Supply to 0a. The data word on signal line 130a is
It is given as write data to the first scan conversion RAM 131a. Second data multiplexer 129
b indicates a signed level data word on the signal line 116 when the second selection signal on the signal line 120b is at the "H" level, and b when the second selection signal is at the "L" level. Supplies the fixed data word "0" on the signal line 117 to the signal line 130b, respectively. The data word on the signal line 130b is given to the second scan conversion RAM 131b as write data. When the first selection signal on the signal line 120a is at "H" level, the first address multiplexer 132a outputs the zigzag scan address on the signal line 123 at the "L" level. In some cases, the initialization address on the signal line 128a is supplied to the signal line 133a. Signal line 133a
The upper address is the first scan conversion RAM 131a.
Given as a write address. When the second selection signal on the signal line 120b is at "H" level, the second address multiplexer 132b outputs the zigzag scan address on the signal line 123 at the "L" level. In some cases, the initialization address on the signal line 128b is supplied to the signal line 133b. The address on the signal line 133b is the second scan conversion RAM.
It is given to 131b as a write address.

According to the decoding circuit of FIG. 1, after all the data words stored in the first scan conversion RAM 131a are initialized to "0", the signed level is calculated based on the zero run length data word. Only the data word is overwritten in "0" at the position designated by the zigzag scan address in the first scan conversion RAM 131a. 8 × 8 which constitutes one block in this way
While only the non-zero component of the individual components is being written to the first scan conversion RAM 131a, one block stored in the second scan conversion RAM 131b is read and initialized. Be seen. Further, only the non-zero component of the next block is the second scan conversion RAM 1
While being written in 31b, one block stored in the first scan conversion RAM 131a is read out and initialized.

For example, the first scan conversion RAM 13
In the mode in which the writing of 1a is executed, following the variable length code of the DC coefficient, the VLD 101 sets the zero run length data word RUN (n) of "3", the level data word LEVEL (n) of "2", It is assumed that a variable length code of an AC coefficient that generates 1-bit information S (n) of "0" is given to the data input terminal 100. At this time, the address adder 119 supplies the linear address LADDR (n−1) of “0” to the signal line 121, and then the linear address LADDR (n) of “4 (decimal notation)” according to the equation (3). Is supplied to the signal line 121. Therefore, according to the address conversion table shown in FIG. 8, the lookup table 122 stores the zigzag scan address of "000 000 (binary expression)" followed by "001 001 (binary expression)" in the first scan conversion RAM1.
31a. The third data latch 115 is DC
Signed level data word SLEVEL (n
After -1), the signed level data word SLEVEL (n) of "+2" obtained from the equation (1) is supplied to the first scan conversion RAM 131a. Therefore, the first
"0" in the position designated by the zigzag scan address "000000" in the scan conversion RAM 131a is a signed level data word SL related to the DC coefficient.
After being rewritten to EVEL (n-1), "0" at the position designated by the zigzag scan address "001 001" is "+2" and is a signed level data word SLEV.
It is rewritten as EL (n). At this time, "0" at the position designated by the zigzag scan address corresponding to each of the linear addresses "1", "2", and "3" remains in the first scan conversion RAM 131a. In the same manner, the variable length code of the AC coefficient is the data input terminal 10
Each time it is given to 0, the signed level data word fetched by the third data latch 115 is overwritten on “0” at the corresponding position in the first scan conversion RAM 131a.

As described above, according to the decoding circuit of FIG.
Initialize all the data words stored in the scan conversion RAM (for example, 131a) to “0” in advance, and write only the signed level data word in the scan conversion RAM in synchronization with the clock signal 102. Therefore, the number of clock pulses in the clock signal 102 required to process one block is 8 according to the number of non-zero components among the 8 × 8 components that configure one block. Much less than ^two . Therefore, even when processing a macro block (4: 2: 0 format) having a size of 16 × 16 pixels in a color moving image, the clock signal 102 having the same frequency as the pixel clock signal is used.
Can be used. This is because, according to the decoding circuit of FIG. 1, even if the frequency of the pixel clock signal is a high frequency exceeding 40 MHz, the macroblock can be generated with the number of clock pulses smaller than 4 × 8 ² in the clock signal 102. This is because real-time run-length decoding of the expressed 6 × 8 ² components can be easily realized.

The data word read on the first data output terminal 134a is read on the second data output terminal 134b to a set of inverse quantizers and IDCT circuits each having a pipeline structure. The other data word has a pipeline structure and another set of dequantizer and IDC.
Advantageously, each is supplied to a T circuit. The parallel operation of a plurality of pipelines enables effective use of the decoding circuit of FIG.

Obviously, the same effect can be obtained by using three or more dual port RAMs. In the above example, each time one data word is read, the data word is initialized to "0".
The initialization of the blocks may be started after the reading of the blocks is completed. However, the reading and initialization of the preceding block must be completed by the time the writing of the non-zero component of the 8 × 8 components forming one block is completed.

In the decoding circuit of FIG. 1, the initialization address generation circuit 127 may supply the write request signal to the address adder 119 when the initialization of the preceding block is completed. Until the address adder 119 receives the EOB detection signal on the signal line 104, it receives the first selection signal on the signal line 120a and the second selection signal on the signal line 120b until it receives the write request signal. It waits without inversion and gives a wait signal to the VLD 101. By doing this, only after the reading and initialization of the preceding block and the writing of the next block are completed,
Further, the writing of the next block will start. The first and second scan conversion RAMs 131a, 1
In order to speed up reading and initialization of the block in 31b, it is effective to execute reading and initialization in units of a plurality of data words.

FIG. 2 shows first, second and third scan conversion RAMs 13 each composed of a single port RAM.
It shows a part of the configuration of another decoding circuit according to the present invention including 1a, 131b, 131c. This decoding circuit includes a VLD 101, a first data latch 108, and a second data latch 108 in FIG.
The data latch 109, the 1-bit latch 110, the positive / negative value switching unit 112, and the third data latch 115 are also provided, but the circuits other than the third data latch 115 are included. The illustration of blocks is omitted in FIG. 2 for simplicity.

The address adder 119 shown in FIG. 2 operates when a block start signal is supplied to the signal line 103.
The held linear address is initialized to “0” in synchronization with the clock signal 102, and the linear address is set to the signal line 12
1 and a trigger signal to the signal line 152. Further, the address adder 119 sets the held linear address to LADDR (n−1), and the signal line 11
When the zero run length data word on 3 is RUN (n), a new linear address LADDR (n) is calculated in synchronization with the clock signal 102 according to the above equation (3), and this is held. This new linear address is also
It is supplied to the signal line 121. Also, the address adder 11
9 indicates the 2-bit information on the signal line 151 as “00”, “1”
It has a function of cyclically setting to "0" and "01", and each time the EOB detection signal on the signal line 104 is received, the 2-bit information is changed from "00" to "10", to "1".
Update from "0" to "01" and from "01" to "00".

The look-up table 122 in FIG.
It has the address conversion table shown in FIG. 8 corresponding to the zigzag scan of FIG. 6, converts the linear address on the signal line 121 into the corresponding zigzag scan address, and supplies the zigzag scan address to the signal line 123. .

The trigger signal on the signal line 152 is supplied to the read / initialization address generation circuit 159. The read / initialization address generation circuit 159 uses the signal line 15
In response to the trigger signal on line 2, the operation of sequentially supplying the read and initialization addresses to the signal line 160 is started.

The 2-bit information on the signal line 151 is supplied to the decoder 153. An example of the internal configuration of the decoder 153 is shown in FIG. The decoder 153 includes high-order bits 151 .., which form 2-bit information on the signal line 151.
Four logic circuits 171, 172, 173, 175 having 1 and lower bit 151.0 as two inputs, an inverter 174 having an upper bit 151.1 as an input, and a lower bit 151.0 as an input. And an inverter 176 that has been installed. The decoder 153 has six output signal lines 154.
a, 154b, 154c, 155a, 155b, 155
I have c. The truth table of this decoder 153 is shown in FIG.
It shows in (b).

Around the first, second and third scan conversion RAMs 131a, 131b and 131c in FIG.
The first, second and third data multiplexers 129a,
129b and 129c, the first, second and third non-inverting control buffers 156a, 156b and 156c and the first, second and third inverting control buffers 158a, 158b and 1
58c and first, second and third address multiplexers 132a, 132b, 132c are provided.

The first data multiplexer 129a is
When the selection signal on the signal line 154a is at "H" level, the signed level data word on the signal line 116 is set. When the selection signal is at "L" level, the fixed data word on the signal line 117 is set. "0" is supplied to each signal line 130a. The first non-inverting control buffer 156a supplies the data word on the signal line 130a to the signal line 157a when the control signal on the signal line 155a is at "H" level, and the control signal is at "L" level. If so, the self output is kept in a high impedance state. Signal line 157a
The data word supplied to the top is R for the first scan conversion.
Given to the AM 131a. First inversion control buffer 1
When the control signal on the signal line 155a is at the "L" level, 58a supplies the data word read on the signal line 157a from the first scan conversion RAM 131a to the data output terminal 134, and controls the data word. When the signal is at "H" level, its output is kept in a high impedance state. The first address multiplexer 132a outputs the zigzag scan address on the signal line 123 when the selection signal on the signal line 154a is at "H" level, and the signal line when the selection signal is at "L" level. The read and initialization addresses on 160 are supplied to the signal line 133a, respectively. The address on the signal line 133a is given to the first scan conversion RAM 131a. Second data multiplexer 129b, second non-inverting control buffer 156
b, the second inversion control buffer 158b, the second address multiplexer 132b, and the signal lines 130b and 133.
b, 154b, 155b, 157b are provided for the second scan conversion RAM 131b, and include a first data multiplexer 129a, a first non-inversion control buffer 156a, and a first inversion control buffer 15.
8a, the first address multiplexer 132a and the signal lines 130a, 133a, 154a, 155a, 157a.
Respectively correspond to. Third data multiplexer 12
9c, a third non-inverting control buffer 156c, a third inverting control buffer 158c, a third address multiplexer 132c and signal lines 130c, 133c, 154c, 1
55c and 157c are the third scan conversion RAM 13
1c is provided for the first data multiplexer 129a, the first non-inverting control buffer 15
6a, the first inversion control buffer 158a, the first address multiplexer 132a, and the signal lines 130a and 133.
a, 154a, 155a, 157a, respectively.

According to the decoding circuit of FIG. 2, after all the data words stored in the first scan conversion RAM 131a are initialized to "0", the signed level is calculated based on the zero run length data word. Only the data word is overwritten in "0" at the position designated by the zigzag scan address in the first scan conversion RAM 131a. 8 × 8 which constitutes one block in this way
While only the non-zero component of the individual components is being written to the first scan conversion RAM 131a, reading of one block stored in the second scan conversion RAM 131b and the third block Scan conversion RAM 131
One block stored in c is initialized. Further, while only the non-zero component of the next block is being written in the third scan conversion RAM 131c, 1 is stored in the first scan conversion RAM 131a.
Reading of one block and the second scan conversion RA
One block stored in M131b is initialized. Only the non-zero component of the next block is the second
Of one block stored in the third scan conversion RAM 131c and one block stored in the first scan conversion RAM 131a while being written in the scan conversion RAM 131b. Initialization is performed. Therefore, according to the decoding circuit of FIG. 2, as in the case of FIG. 1, highly efficient run-length decoding corresponding to a high-frequency pixel clock signal in real time can be realized.

Obviously, the same effect can be obtained by using four or more single port RAMs. Two single port RAMs are sufficient to initialize one block after it has been read.

In the decoding circuit of FIG. 2, when the initialization of the first preceding block and the reading of the second preceding block are completed, the read / initialization address generating circuit 159.
May supply the write request signal to the address adder 119. The address adder 119 receives the EO on the signal line 104 until receiving the write request signal.
Even if the B detection signal is received, it waits without updating the 2-bit information on the signal line 151, and gives a wait signal to the VLD 101. With this configuration, initialization of the first preceding block and reading of the second preceding block,
Only after the writing of the next block is completed, the writing of the next block is started. In addition,
The first, second and third scan conversion RAMs 131a,
In order to speed up reading and initialization of blocks in 131b and 131c, it is effective to perform reading and initialization in units of a plurality of data words.

[0044]

As described above, according to the present invention, all the data words stored in the scan conversion RAM are initialized to "0" in advance, and "0" in the scan conversion RAM is initialized. Since only the level data word is written to the corresponding position in the scan conversion RAM based on the zero run length data word so as to overwrite "," it is possible to correspond to a high frequency pixel clock signal in real time. An efficient run-length decoding circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a decoding circuit according to the present invention.

FIG. 2 is a block diagram showing a part of a configuration example of another decoding circuit according to the present invention.

3A is a circuit diagram showing an internal configuration example of the decoder in FIG. 2, and FIG. 3B is a diagram showing a truth table thereof.

FIG. 4 is a block diagram showing a configuration example of a conventional decoding circuit.

FIG. 5 is a diagram showing an example of components in one block immediately after quantization.

FIG. 6 is a diagram illustrating an example of a rule regarding a zigzag scan order.

FIG. 7 is a diagram illustrating an example of a run-length encoded data stream.

8 is a diagram showing an example of an address conversion table corresponding to FIG.

[Explanation of symbols]

100 data input terminal 101 variable length code decoder (VLD) 102 clock signal 103 signal line (block start signal) 104 signal line (EOB detection signal) 105 signal line (zero run length data word) 106 signal line (level data word) 107 Signal Line (1 Bit Information Representing Positive or Negative of Level Data Word) 108 First Data Latch 109 Second Data Latch 110 1 Bit Latch 111 Signal Line (Latched Level Data Word) 112 Positive / Negative Value Switching Unit 113 Signal Line (Latched Zero Run Length Data Word) 114 Signal Line (Signed Level Data Word) 115 Third Data Latch 116 Signal Line (Latched Signed Level Data Word) 117 Signal Line (Fixed Data Word “0” ") 118 address for writing Address generation circuit 119 address adder 120a, 120b signal line (selection signal) 121 signal line (linear address) 122 lookup table 123 signal line (zigzag scan address) 124 read address generation circuit 125a, 125b signal line (read address) 126a, 126b Signal line (read address) 127 Initialization address generation circuit 128a, 128b Signal line (initialization address) 129a, 129b, 129c Data multiplexer 130a, 130b, 130c Signal line 131a, 131b, 131c Scan conversion RAM 132a , 132b, 132c Address multiplexer 133a, 133b, 133c Signal line 134, 134a, 134b Data output terminal 135 Signal line (latched 1-bit information ) 151 signal line (2-bit information) 151.0 2-bit information lower bit 151.1 2-bit information upper bit 152 signal line (trigger signal) 153 decoder 154a, 154b, 154c signal line (selection signal) 155a, 155b , 155c Signal line (control signal) 156a, 156b, 156c Non-inversion control buffer 157a, 157b, 157c Signal line 158a, 158b, 158c Inversion control buffer 159 Read / initialization address generation circuit 160 Signal line (read / initialization address) ) 171, 172, 173, 175 2-input logic circuit 174, 176 Inverter

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication H04N 7/30

Claims (5)

[Claims] 1. A run having a plurality of data sets each comprising a zero run length data word representing the number of zero components each preceding a non-zero component, and a level data word representing the value of the non-zero component. A circuit for decoding a length-encoded data stream, means for latching one zero-run length data word and one corresponding level data word in said data stream; Storage means for storing a series of data words at predetermined positions for initialization, initialization means for initializing the data words stored in the storage means to all zero data words, and the latched Latched to overwrite one zero data word in the storage means based on a zero run length data word. Level and writing means for writing the data word in the storage means, decoding circuits run-length code, characterized by comprising reading means for sequentially reading the data words stored in the storage means. 2. The run-length code decoding circuit according to claim 1, wherein the writing means holds a linear address, and the number of zero components represented by the latched zero run-length data word. 1
An adder for calculating a new linear address by adding and a zigzag scan address is calculated from the calculated linear address, and the zigzag scan address thus calculated is supplied to the storage means as a write address. A decoding circuit comprising a look-up table. 3. The run-length code decoding circuit according to claim 1, wherein the storage means includes two dual-port RAMs, and the latched level to one of the two dual-port RAMs. A decoding circuit, wherein a data word stored in the other dual-port RAM is read and initialized during a data word writing period. 4. The run length code decoding circuit according to claim 3, wherein the data word is initialized immediately after reading one data word stored in the other dual port RAM. Characterizing decoding circuit. 5. The run-length code decoding circuit according to claim 1, wherein the storage means includes three single-port RAMs, and the latch to any one of the three single-port RAMs. During the writing of the level data word, the reading of the data word stored in the other single port RAM and the initialization of the data word stored in the other single port RAM are performed. Decoding circuit characterized by being performed.