KR100202307B1 - Dct variable coder for mpeg-2 image compression - Google Patents

Abstract

The present invention relates to a structure of a DCT coefficient variable length encoding apparatus of an image encoding apparatus according to the MPEG-2 standard. The configuration proposed in the present invention is suitable to be implemented using an ASIC or an FPGA, and can be used at high speed because it can be operated at high speed. Therefore, it can be developed as a core ASIC and used to implement a video encoding / decoding device having various performances. The configuration of the present invention comprises a macroblock memory for storing DCT transformed coefficients; A counter unit for counting the output data from the memory; A CBP calculator configured to determine a coding pattern (CBP) on a block-by-block basis for the output data from the memory; A DC processor for processing DC data from the memory; An AC processor for processing AC data from the memory; A multiplexer unit for selecting data from the DC processor and the AC processor and outputting the data to an output unit; And an internal control unit for inputting control signals from an external system control unit, a variable length encoding control unit, and the counter unit and the CBP calculating unit to generate control signals for controlling the DC processing unit, the AC processing unit, and the multiplexer unit. .

Description

DCT Coefficient Variable Length Coding Device for MPEG-2 Video Compression

The present invention relates to a DCT coefficient encoding apparatus employed in a variable length coding (VLC) apparatus used in a video encoding apparatus conforming to the MPEG-2 standard among video signal compression algorithms.

Recently, with the rapid development of semiconductor technology, each core device in the signal processing field is being implemented as a single application specific integrated circuit (ASIC) chip at the existing large system or board level. Accordingly, it is necessary to design high-capacity hardware to be bonded to a highly integrated semiconductor (VLSI) implementation. The structure of the variable length encoder proposed by the present invention is not a system or board-level low-volume hardware but a special structure suitable for high-speed processing, and can be effectively employed as part of a high-speed video encoder.

SUMMARY OF THE INVENTION An object of the present invention is to provide a hardware structure for VLSI implementation of a variable length coding apparatus that can be applied to digital TV, high definition television (HDTV), and the like, which reduces chip area and enables high-speed operation.

1 is an interface of an input / output signal of a DCT coefficient variable length encoder.

2 is an input / output signal definition diagram of a DCT coefficient encoding apparatus.

3 is a detailed block diagram of a DCT coefficient encoding apparatus.

Figure 4 Variable Length Code-dct_dc_size_luminance dct_dc_size _chrominance

5 to 8 show the DCT coefficient table

9 is a coding table of run and level according to ESCAPE code

10 is a state diagram of the DCT coefficient encoder

11 to 18 show a state table of the DCT coefficient encoder.

19. mux_sel Condition Table

20 is a dc_dct_pred load signal determination condition table

21 is a DCT memory block diagram

22 is a timing diagram of the DCT coefficient encoder.

* Explanation of symbols for main parts of the drawings

1: Internal controller 2: CBP calculation unit

3: AC selection processing unit 4: next quarter

5: AC table 6: DC table

7: DC addition part 8: AC addition part

9,10,11: Multiplexer 12: DC register

13: Backup register 14: Previous block DC register

15: block counter 16: pixel counter

The present invention proposes an effective hardware implementation method of DCT coefficient coding for MPEG-2 video compression. The present invention proposes a dedicated hardware controller having eight states for its effective implementation.

The present invention to achieve the above object;

A macroblock memory for storing DCT transformed coefficients;

A counter unit for counting the output data from the memory;

A CBP calculator for determining a coding pattern (CBP) on a block-by-block basis for output data from the memory;

A DC processor for processing DC data from the memory;

An AC processor for processing AC data from the memory;

A multiplexer unit for selecting data from the DC processor and the AC processor and outputting the data to an output unit; And,

And an internal control unit 1 for inputting control signals from an external system control unit and a variable length encoding control unit and the counter unit and the CBP calculating unit to generate control signals for controlling the DC processing unit, the AC processing unit and the multiplexer unit. To be characterized.

In addition, the DC processing unit

A DC register 12 which receives data from the MB memory;

A previous block DC register 14 for storing the DC value of the previous block during intra block coding;

A divider (4, 9) for subtracting data from the DC register (12) and the previous block DC register (14) to output a difference value;

And a DC adding section 7 for variable length encoding the output of the difference with reference to the DC table 6.

The AC processing unit may further include: an AC selection processing unit 3 for determining an AC coefficient and counting the number of '0's;

It is characterized by including an AC adding section 8 for variable length encoding the AC coefficient with reference to the AC table 5 and adding a sign bit and an EOB code.

The counter unit may further include a block counter 15 for counting and storing the number of blocks; And a pixel counter 16 for counting and storing the number of pixels in the current block.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 shows interface signals of a VLC DCT coefficient encoder. 2 illustrates signals received from external modules (system controller module, DCT and quantization / dequantization module) and output signals to the VLC packer in the DCT coefficient encoder.

3 is a detailed block diagram of the DCT coefficient encoding apparatus. As shown, the DCT coefficient encoding apparatus is composed of a controller, a memory, a counter, a register, a MUX, etc., and its role is to receive a signal and data from another block to determine a coded block pattern (CBP) and to apply quantized DCT coefficients. The DCT coefficient inputted to the packer is output to the packer by variable length coding, and the input DCT coefficient is input to the CBP calculation unit. After determining whether a coefficient other than '0' is present among 64 coefficients in block units, the CBP pattern is determined. Output the result to the VLC controller.

The coding method of the DCT coefficient can be classified into two types. One is coding for the DC coefficient of the intra block, and the other is coding for the AC coefficient of the intra block and the AC coefficient of the non-intra block.

1) Coding Method of Intra Block DC Coefficient

The encoding of the intra block DC coefficient does not encode the absolute size of the coefficient but transmits only the difference compared to the DC value of the previous block, and uses a predictor having the coefficient value of the previous block. The value of the predictor is reset to a certain value according to intra_dc-precision. In this case, it is fixed to 128 and used in the following case.

At the beginning of the slice

Each time a non-intra macro block is decoded

Whenever a macroblock is skipped (ie macroblock_address_increment 1)

In general, DC coefficients are very large in contrast to AC coefficients, so they do not use the same VLC table as AC coefficients. The code is divided into two parts of the differential value representing the actual difference.

If the size value is '0', only the code of size is transmitted. If not, the differential value is transmitted with the number of bits of size after the code.

As shown in FIG. 4, the size is about luminance signal and chrominance, and the table is selected and used according to cc (colour component), where cc has values of 0, 1, and 2, respectively. Means Y, Cb and Cr.

2) Coding method of AC coefficient

The VLC table and FIG. 5 show a combination of the absolute level of the non-zero quantized DCT coefficients and the number of runs of zeros preceding the current nonzero coefficient. The variable bits are coded by FIG. 8, and the last bit 's' in this table means the sign of the level. If the level is positive, it is '0' and if it is negative, it is '1'.

Among the possible combinations of run and level, statistically rare combinations that cannot be represented by variable-length code in the drawing use fixed length coding (ie, ESCAPE coding). Fixed-length code consists of 24 bits, ESCAPE code (6 bits) indicating the use of fixed length code, run (6 bits) indicating run length (number of 0), and signed_level (12 bits) indicating the magnitude of the coefficient. It consists of).

When the encoding of one block is finished, an end of block (EOB) code, which means the end of the block, is added, and when the block coefficients are all '0', that is, the non-coded block Just goes without coding. Therefore there is no EOB code.

In the following, each block is disclosed to be easily implemented by those skilled in the art.

(1) Internal controller

The internal controller 1 receives various signals such as sck2, vlck, coding_end_2, scan_data_en, mb_intra, cbp from the external block, and transmits / controls necessary signals and data inside the block. The notification outputs the data_en signal to the output unit, and when the coding of one macro block is completed, the coding_end_3 signal is output to the VLC controller indicating that the coding is completed. The following is a description of the state diagram of the DCT coefficient encoder.

The state diagram of the DCT coefficient encoder is divided into eight states, such as RESET, IDLE, VLCK, SKIP, and SH1 to SH4, as shown in FIG. 10, and each state maintains its current state according to whether an input signal is generated. Or move to the next state.

First, the IDLE state is not coded. The state remains until the vlck becomes '1'. The RESET state initializes the entire DCT coefficient encoder. The reset signal is generated when the system is first operated. When vlck, which is a clock signal generated for each macroblock to be coded by VLC from the IDLE state, is transferred to the VLCK state, when vlck is input, mb_intra and cbp are also inputted and maintained for 660 sck2. When vlck becomes '0', the VLCK returns to the IDLE state and remains in the current state until the coding_end_2 signal is generated. At this time, if the dc_dct_pred_reset signal is generated, the previous block DC register is reset, and when coding_end_2, which is a signal for starting variable-length encoding of the DCT coefficient, is input from the motion vector encoder, it moves to the next state SH1.

In SH1, blkclk, intra_load, and back_load are generated, and a read_1 or read_2 signal is generated depending on a condition. SH1 can be in the state of SKIP or SH2 by the condition of cbp. If the bit of the corresponding block among the 6 bits of the cbp value is '0', it moves to SKIP. However, in the SKIP state without any coding, the data_en signal is '0', so the data is not valid. The coeffcnt value moves to the next state SH3. The SH3 state also generates a coding_end_3 signal, which signals to the variable length encoder controller that the variable length encoding of a macroblock is finished.If the blkcnt value is smaller than 5 and the coeffcnt value is 63 (binary 111111), the value is SH1. If blkcnt is 5 (binary 101), go to SH4. A state table for this is described in FIGS. 11 to 18. And the selection condition of the multiplexer is shown in FIG. In addition, the load signal of dc_dct_pred is shown in FIG. 20.

(2) CBP calculation unit

The CBP calculation unit 2 receives scan data corresponding to one macroblock and checks whether there is a coefficient other than '0' among 64 coefficients in block units to determine cbp, and then outputs the result to the variable length coding controller. do. cbp is represented by 6 bits, and each 6-bit place indicates whether or not 6 blocks are coded, and a value of '0' for an uncoded block that is not coded and a '1' for a coded block to be coded is represented. Will have

(3) MB memory

21 shows a macroblock memory. Receives scan data from DCT block and delays by one macro block while data valid signal (scan_data_en) is input. Two memories are required to input and output scan data during 660 sck2 when all coding for one macro block must be completed. Do.

(4) DC processing section (12, 13, 14)

The DC register 12 receives scan data from the MB memory and outputs data by the load signal. It is a 12-bit register. The backup register 13 is used to store the DC value of the previous block in the previous block DC register during intra block coding, and outputs data by the load signal. This is a register that stores the previous DC coefficients Y, Cb and Cr of the previous block DC register 14. The previous block DC register 14 stores the DC value of the previous block during intrablock coding. The previous block DC register 14 outputs data by a load signal.

(5) AC processing unit (3,5,8)

The AC selection processing unit 3 is a part that processes to make the run count only when the input coefficient is not the DC coefficient of the intra block and its value is '0'. It serves to deliver to the table (5) and the AC additional unit (8). The AC table 5 is a look-up table (LUT) for run length coding the AC coefficient. The AC table 5 is coded with reference to the table as one of the configurations for run length coding of the AC coefficient. The variable length code thus has a length of 2-24 bits. The AC appender 8 attaches a sign bit and an EOB code to the variable length coded value obtained from the AC table. The output data has a length of 26 bits.

(8) Next quarter (4)

In intrablock DC coefficient coding, the difference and size value between the DC coefficient of the current block and the DC coefficient of the previous block is calculated. That is, the difference and the magnitude are output as a difference inputting the DC coefficient of the previous block and the DC coefficient of the current block.

(9) DC table (6)

When coding the DC coefficient, the size value representing the difference (bit number) between the coefficient of the current block and the coefficient of the previous block is coded by referring to the table.

-VDCT_DC_L_TABLE: Luminance lookup table (LUT) that inputs the size value which is the output calculated in the next quarter.

-VDCT_DC_C_TABLE: A chroma lookup table that takes an input of the size value that is the output from the next quarter.

(10) DC attachment (7)

In the DC coefficient coding, the difference value representing the actual difference between the coefficient of the current block and the coefficient of the previous block is coded by referring to the table. If the previously calculated size value is '0', only the code of size is transmitted and the value is '0'. Otherwise, the code for size is passed along with the difference by the number of bits in size. The length of the variable-length coded code is variable and has a length of 2-20 bits for the luminance component and 2-21 bits for the chroma component.

If the size value in the next quarter is '0', only the code of size is transferred, and if it is not '0', it plays the difference value with the number of bits of size after the code for size.

The MUX 9 is a multiplexer that inputs the outputs (previous DC coefficients) of the previous block DC register 14 and inputs one of three DC coefficient values (Y, Cb, Cr components) stored in the dc_dct_pred_REG. Select using (12bit). The MUX 11 selects the corresponding data_len of the variable length coded code as a select signal of the multiplexer and outputs it to the output unit (5 bits). The MUX 10 selects the data among the variable length coded values as a selection signal of the multiplexer and outputs the data to the packer (32 bits).

In addition, the block counter 15 is a counter that stores the number of blocks, and the pixel counter 16 is a counter that stores the number of pixels in the current block.

22 is a timing diagram showing the overall operation of the above-described DCT coefficient encoder.

As described above, the present invention can be effectively used in applications using the MPEG-2 standard such as digital TV or high definition TV, since the high-speed processing is possible with the VLSI structure for the hardware implementation of the DCT coefficient coding among the variable length coding apparatus. Can be. This circuit can be implemented as an FPGA or ASIC and can be used as part of the MPEG-2 encoder.

In addition, a preferred embodiment of the present invention is disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the following claims You will have to look.

Claims (4)

A DCT coefficient variable length encoding apparatus for MPEG-2 video compression; The encoder is; A macroblock memory for delay storing the DCT transformed coefficients; A counter unit for counting the output data from the memory; A CBP calculator configured to determine a coding pattern (CBP) on a block-by-block basis for the output data from the memory; A DC processor for processing DC data from the memory; An AC processor for processing AC data from the memory; A multiplexer unit for selecting data from the DC processor and the AC processor and outputting the data to an output unit; And an internal control unit configured to generate a control signal for controlling the DC processor, the AC processor, and the multiplexer by inputting control signals from an external system controller, a variable length coding controller, and the counter unit and the CBP calculator. Variable length coding device of DCT coefficients. 2. The apparatus of claim 1, wherein the DC processing unit comprises: a DC register for receiving data from the MB memory; A previous block DC register for storing the DC value of the previous block during intra block coding; A divider for subtracting data from the DC register and the previous block DC register to output a difference value; And a DC adding unit for variable length encoding the output of the difference with reference to a DC table. 2. The apparatus of claim 1, wherein the AC processing unit comprises: an AC selection processing unit for determining an AC coefficient and counting the number of '0's; A variable length coding apparatus for DCT coefficients, comprising: an AC appending section for variable length encoding the AC coefficient by referring to the AC table, and adding a sign bit and an EOB code. The apparatus of claim 1, wherein the counter unit comprises: a block counter for counting and storing the number of blocks; And a pixel counter for counting and storing the number of pixels in the current block.