JP4502383B2 - Decoding device and method thereof - Google Patents

Description

  The present invention relates to a decoding apparatus and method thereof, and more particularly to a decoding apparatus and method for decoding run-length encoded codes at high speed.

  Conventionally, as an encoding method for storing and displaying a still image on a storage medium such as a CD-ROM or a hard disk, the JPEG method standardized by ISO (International Organization for Standardization) has been widely used. In addition, the MPEG standardized by ISO is widely used as an encoding method for storing and displaying moving images and audio on the same storage medium, broadcasting over a communication channel, or bidirectional communication. ing.

  The MPEG system, which is a video and audio encoding system, has been improved year by year for the purpose of improving encoding efficiency. MPEG-1 in 1992, MPEG-2 in 1994, and MPEG-2 in 1999 MPEG-4 is defined as an international standard. In MPEG-4, not only improvement in coding efficiency but also enhancement of a code error correction function and introduction of object coding for performing optimum coding for each coding target are realized. Furthermore, the system layer that defines the file format including the visual layer and audio layer on the MPEG-4 syntax has a mechanism that allows easy access to moving image or audio data at any time requested by the user. providing.

  In any of the encoding processes of the above-described JPEG still image encoding method and MPEG-1 / 2/4 moving image encoding method, first, the original signal of the still image or moving image is DCT converted to DC component after DCT conversion. They are divided into coefficients and AC coefficients that are alternating current components. Thereafter, both coefficients are quantized and further differently encoded. First, the AC coefficient that is two-dimensional information is converted into one-dimensional information using a zigzag scanning method. Since many “0” s are generated in the high-frequency component of the AC coefficient, the AC coefficient value (significant coefficient; level) other than “0” and how many “0” s precede it (number of insignificant coefficients; run) Symbol) is generated, and is encoded by a Huffman encoding method that employs an entropy encoding method that assigns a codeword having a short code length to information with a high occurrence frequency.

  On the other hand, the decoding processing of the JPEG still image encoding method and the MPEG-1 / 2/4 moving image encoding method starts with Huffman decoding, in contrast to the above-described encoding processing, and is based on run length decoding and zigzag scanning method 1 Reconstructed still images / moving images are generated through restoration from dimensional information to two-dimensional information and inverse DCT transformation.

  In a general Huffman decoding process (see, for example, Patent Document 1), encoded data is sequentially analyzed from the top, and converted into a corresponding symbol by referring to a Huffman table having a Huffman code prepared in advance as an address. At the same time, by extracting the Huffman code from the encoded data from the code length information obtained from the Huffman table, the decoding process for one Huffman code is completed.

  Therefore, in a general Huffman decoding process, decoding of a subsequent Huffman code cannot be started until decoding of one Huffman code is completed. That is, only one symbol can be decoded in one cycle. Although various proposals have been made to date to solve this problem, images that still perform Huffman decoding of one symbol or more in one cycle by improving the operating frequency of system LSIs and the like accompanying recent semiconductor process evolution It is difficult to realize a decoding device.

As described above, after the Huffman decoding process with one symbol per cycle is performed, the run-length decoding process is performed. Conventionally, in the run-length decoding process, one symbol input per cycle is converted to a DCT coefficient composed of a DC component and an AC component at a speed of 1 DCT coefficient per cycle.
Japanese Unexamined Patent Publication No. H4-284782

  However, high-resolution still images and high-resolution still images have come along with higher resolution of digital image sensors mounted on portable information devices such as digital cameras in recent years, the widespread use of high-resolution HDTV broadcasting, and the speed of digital communication networks such as the Internet. With the increase in the distribution of moving image content, there is an increasing demand for image decoding devices that decode still images and moving images taken at high resolution at high speed.

  Therefore, an object of the present invention is to provide a decoding apparatus and method for decoding a symbol composed of a number of consecutive insignificant coefficients and subsequent significant coefficient sets at high speed.

  In order to achieve the above object, an image decoding apparatus according to the present invention has the following arrangement.

That is, a decoding device for decoding a symbol comprising a set of consecutive non-significant coefficients followed by a significant coefficient, and significant coefficient decoding means for decoding the significant coefficients of the symbols by a multistage pipeline configuration; , Coefficient transmission means for transmitting a coefficient identification signal representing the type of coefficient processed in each stage of the multistage pipeline configuration in synchronization with the multistage pipeline configuration, and the coefficient to the coefficient transmission means according to the symbol Outputting an identification signal and controlling the supply of symbols to the significant coefficient decoding means according to the number of consecutive insignificant coefficients of the symbol; and the coefficient identification signal transmitted by the coefficient transmission means Correspondingly, the coefficient output means for outputting the significant coefficient decoded by the significant coefficient decoding means in combination with a non-significant coefficients, to the control means Coefficient changing means for changing a coefficient identification signal transmitted by the coefficient transmission means according to control, and the control means inputs a coefficient identification signal transmitted by the coefficient transmission means in a first clock cycle. According to the symbol, the coefficient identification signal in the second clock cycle following the first clock cycle is determined .

  According to the present invention, the number of consecutive insignificant coefficients input at one symbol per cycle and a symbol consisting of a set of subsequent significant coefficients are decoded, and the decoding result of one or more symbols is output per cycle. By doing so, it is possible to perform a high-speed decoding process with a minimum circuit configuration.

  Hereinafter, the present invention will be described in detail based on preferred embodiments with reference to the accompanying drawings.

<First Embodiment>
Hereinafter, as an embodiment according to the present invention, an example using an MPEG encoding method will be described. However, the present invention is not limited to the moving image encoding method, and can be similarly applied to a JPEG encoding method that is a still image encoding method.

  FIG. 2 is a block diagram showing a functional configuration of the image decoding apparatus according to the present embodiment. In the figure, 100 is a variable length decoding unit, 200 is a symbol decoding unit that inputs a symbol consisting of a set of run length and level output as a variable length decoding result and outputs a desired DCT coefficient sequence, 300 is an inverse quantization unit that performs inverse quantization on the DCT coefficient sequence, 400 is an inverse DCT unit that outputs a reconstructed image from the inversely quantized DCT coefficient sequence, and 500 is an encoded data decoding unit having the configurations 100 to 400 described above. It is a control part which controls arithmetic processing. Reference numeral 601 denotes an encoded data input signal for inputting encoded data from the outside. Reference numeral 602 denotes a reconstructed image data output signal for outputting a reconstructed image to the outside. Is configured.

  FIG. 1 is a block diagram showing a detailed configuration of symbol decoding section 200. In the figure, 201 is a symbol data input signal for inputting one symbol per cycle from the variable length decoding unit 100 in the previous stage. Here, the symbol is a set of the number of consecutive insignificant coefficients followed by a significant coefficient, that is, a set of run length and level.

  202 is a run-length decoding unit that controls symbol data decoding processing in the symbol decoding unit 200 according to the run length.

  Reference numeral 203 denotes a level decoding unit that decodes a level composed of a positive / negative code and an amplitude, and 204 denotes a DPCM decoding unit that performs DPCM decoding on a symbol corresponding to a DC coefficient. 205 is a serial / parallel converter that inputs one DCT coefficient per cycle and outputs a plurality of coefficients simultaneously according to the bit width of the DCT coefficient data output signal of the symbol decoding unit 200, and 206 is one cycle. This is a DCT coefficient data output signal output as two DCT coefficients. In this embodiment, a level decoding unit 203, a DPCM decoding unit 204, and a serial / parallel conversion unit 205 form a pipeline structure, and thereby a series of symbol decodings for decoding input symbol data into DCT coefficient data The calculation processing is performed. Hereinafter, a configuration including the level decoding unit 203, the DPCM decoding unit 204, and the serial / parallel conversion unit 205 is referred to as a pipeline unit, and details of the operation will be described later.

  Reference numerals 207, 208, and 209 denote flip-flops (hereinafter referred to as FFs), which divide a series of symbol decoding arithmetic processing by the pipeline unit into a three-stage pipeline structure.

  210 is a coefficient identification signal, and whether the symbol to be processed existing in the first stage of the series of symbol decoding arithmetic processing by the pipeline unit corresponds to the DC coefficient or the AC coefficient. Etc., indicating the type.

  211, 212, and 213 are FFs, and transmit the coefficient identification signal 210 to the subsequent stage in synchronization with the pipeline section. 214, 215, and 216 are coefficient identification signals output from the FFs 211, 212, and 213, respectively.

  Reference numeral 217 denotes a coefficient identification signal transmitted to the subsequent stage instead of the coefficient identification signal 214, and reference numeral 218 denotes a coefficient identification signal selection unit that is controlled by the run length decoding unit 202 to select one of the coefficient identification signals 214 and 217. Similarly, 219 is a coefficient identification signal transmitted to the subsequent stage instead of the coefficient identification signal 215, and 220 is a coefficient identification signal selection unit that is controlled by the run-length decoding unit 202 to select one of the coefficient identification signals 215 and 219. It is.

  Reference numeral 221 denotes a HOLD signal that keeps the first stage FF 207 in the pipeline section in the HOLD state so as to delay the subsequent input and processing of the symbols in accordance with the run length of the input symbol. The HOLD signal is separately output as a Busy signal for delaying the output of symbols to the variable length decoding unit 100 at the previous stage.

  FIG. 3 is a table showing each state of the signal portion corresponding to one DCT coefficient and its meaning in the coefficient identification signal 210 output from the run-length decoding unit 202. The coefficient identification signal 210 corresponding to one DCT coefficient is composed of 2 bits, and a value of “00” means that there is no DCT coefficient in each stage of the corresponding pipeline section. If the value is "01", it means that there is a DC component coefficient. If the value is "10", there is a non-zero AC component coefficient (so-called AC component significant coefficient). And a value of “11” means that there is an AC coefficient with a value of zero. In each of the following drawings, description will be made using symbols “X”, “DC”, “AC”, and “0” shown in FIG. 3 as an alternative to the value of the coefficient identification signal 210.

  FIG. 4 is a table showing the states that can be taken by the coefficient identification signal 210 corresponding to the two DCT coefficients output from the run-length decoding unit 202 and their meanings. In the pipeline section, one symbol can be decoded per cycle and 1DCT coefficient can be output. On the other hand, of the two DCT coefficients that can be expressed by the coefficient identification signal 210, one corresponds to the DCT coefficient output after a series of symbol decoding operation processing by the pipeline unit, and the other one decodes the symbol. It corresponds to an AC coefficient having a zero value in which the value of the DCT coefficient to be output is self-explanatory without performing arithmetic processing.

  Here, of the two DCT coefficients that can be expressed by the coefficient identification signal 210, the DCT coefficient to be output in advance is referred to as C1, and a part of the coefficient identification signal 210 corresponding to C1 is referred to as a coefficient identification signal S1, The DCT coefficient to be output subsequently is called C2, and a part of the coefficient identification signal 210 corresponding to C2 is called a coefficient identification signal S2. Then, as shown in the table of FIG. 4, there are eight possible combinations of the coefficient identification signals S1 and S2, and on the right side of the table, each of the coefficient identification signals S1 and S2 represents the state of the coefficient C1 and The state of the coefficient C2 is shown.

  As shown in the table of FIG. 4, when the combination of the coefficient identification signals S1 and S2 is (00, 00), it means that there is no DCT coefficient in each stage of the corresponding pipeline section. Similarly, if (S1, S2) is (01,00), it means that there is a DC coefficient as coefficient C1 and no coefficient C2, and if (01,11), there is a DC coefficient as coefficient C1. This means that there is an AC coefficient having a value of zero as the coefficient C2, and (10,00) means that there is an AC coefficient with a non-zero value as the coefficient C1, and there is no coefficient C2. (10,11) means that there is a non-zero AC coefficient as coefficient C1 and there is an AC coefficient with a value of zero as coefficient C2, and (11,00) is zero as coefficient C1. This means that there is an AC coefficient with a value and no coefficient C2, and in the case of (11,10), there is an AC coefficient with a zero value as the coefficient C1, and there is an AC coefficient with a non-zero value as the coefficient C2. In the case of (11, 11), it means that there is an AC coefficient having a zero value as the coefficient C1, and there is an AC coefficient having a zero value as the coefficient C2.

  FIG. 5 is a truth table showing logic for determining coefficient identification signals 214, 215, and 216 in N + 1 clock cycles from input symbols and coefficient identification signals 214 and 215 in N clock cycles.

  As shown in FIG. 1, from the input coefficient identification signals 214 and 215 and the information of the input symbols, the run-length decoding unit 202 performs coefficient identification signals 214, 215, and 216 in the next clock cycle according to this truth table. Can be determined.

  Of the states of the various coefficient identification signals corresponding to the various symbols shown in FIG. 5, the case where an AC coefficient with a run length of 3 appears as an input symbol in the N clock cycle will be described below.

  First, if the state of the preceding coefficient C1 and the subsequent coefficient C2 represented by the coefficient identification signal 214 in N clock cycles is (DC / AC, X), respectively, the DC coefficient or the AC coefficient whose value is not zero as the coefficient C1 Means that coefficient C2 does not exist. Further, if the state of the preceding coefficient C1 and the subsequent coefficient C2 represented by the coefficient identification signal 215 in N clock cycles is (don't care, don't care), respectively, the coefficient C1 and the coefficient C2 are in any state. Means that it doesn't matter.

  In the state described above in N clock cycles, the state of the preceding coefficient C1 and the subsequent coefficient C2 represented by the coefficient identification signal 214 in the N + 1 clock cycle is (0, 0), and the coefficient identification signal 215 is ( DC / AC, 0) and coefficient identification signal 216 are (don't care, don't care). Note that the state of the coefficient indicated by the diagonal lines in the drawing means that the run-length decoding unit 202 has changed the state from (X) to (0).

  Specifically, the state (X) of the coefficient C2 represented by the coefficient identification signal 214 in the N clock cycle is compared with the state of the coefficient C2 represented by the coefficient identification signal 215 in the N + 1 clock cycle. The state has been changed to (0). In response to the fact that the input symbol that appeared in N clock cycles was an AC coefficient with a run length of 3, an AC coefficient having a value of zero was piped to the coefficient identification signal for which no coefficient existed. Inserted by jumping over one line. This insertion is performed using the identification signal 217.

  Further, the state of the preceding coefficient C1 and the subsequent coefficient C2 represented by the coefficient identification signal 214 in N + 1 clock cycles is (0,0), which means that the input symbol that appeared in N clock cycles is run length: In response to the AC coefficient of 3, the remaining two AC coefficients having zero values are transmitted in one clock cycle.

  Here, in the coefficient identification signals 215 and 214, two DCT coefficients are transmitted for each clock cycle, and it can be seen that high-speed symbol decoding processing is performed. As described above, according to the present embodiment, symbol decoding processing for an 8 × 8 pixel block in which the number of AC coefficients having a run length is dominant, or a block having many AC coefficients having a long run length is not limited. High-speed processing close to 2DCT coefficient / one clock cycle can be realized.

  As described above, the case where the AC coefficient of run length: 3 appears as an input symbol in the N clock cycles of the truth table shown in FIG. 5 and the coefficient identification signals 214 and 215 are in a specific state has been described. However, in the present embodiment, the same idea is applied even in other states, and thus description of other cases is omitted.

  Hereinafter, a specific operation example in symbol decoding section 202 will be described using FIG. 6 and FIG.

  FIG. 6 is a diagram showing a sequence of input symbols in the following operation example. The sequence of input symbols corresponds to one block of variable length decoded data (here, quantized DCT coefficients), as shown in FIG. 6, first DC coefficients, then run length: 3 AC coefficients, Assume that it consists of a total of five symbols: AC coefficient of run length: 1, AC coefficient of run length: 4, and finally EOB (End of Block).

  FIG. 7 shows time-series changes of the coefficient identification signals 214, 215, and 216 output from the run-length decoding unit 202 when the symbol sequence shown in FIG. 6 is decoded by the symbol decoding unit 200. It is a timing chart. In the figure, the flow of time is from top to bottom, and the flow of data processed in each stage of pipeline processing proceeds from left to right.

  Hereinafter, with regard to the decoding process of the present embodiment, the decoding process procedure for the symbol data input to the symbol decoding unit 200 will be described with reference to FIGS. 1, 6, and 7. FIG. Please refer to FIGS. 3, 4 and 5 separately as needed.

  As shown in FIG. 7, first, at time T0, a symbol corresponding to the DC coefficient is input as the symbol data input signal 201. Note that the processing proceeds from time T0 shown in FIG. 7 to time T1, T2,.

  Next, at time T1, the DC coefficient is transmitted as the preceding coefficient C1 in the coefficient identification signal 214 in parallel with the decoding operation processing by the level decoding unit 203. On the other hand, the coefficient C2 expressed by the coefficient identification signal 214 does not exist at the time T1. At this time, an AC coefficient with a run length of 3 appears as a subsequently input symbol, as shown in FIG.

  At time T2, the DC coefficient is transmitted as a coefficient C1 whose state is preceded by the coefficient identification signal 215 in parallel with the decoding calculation process performed by the DPCM decoding unit 204. At the same time, because the symbol corresponding to the AC coefficient of run length: 3 is input at time T1, the coefficient C2 of the coefficient identification signal 215 is zero as the coefficient does not exist at time T1. The AC coefficient having a zero value is transmitted as the coefficient identification signal 217 from the run-length decoding unit 202 so that the AC coefficient having the value is transmitted, and the coefficient identification signal 215 is selected by the coefficient identification signal selection unit 218. “X” in the coefficient C2 is changed to “0”.

  Note that an arrow indicated by a one-dot chain line in FIG. 7 indicates that “X” in the coefficient identification signal 214 or 215 is changed to the coefficient identification signal 217 or 219 by data selection by the coefficient identification signal selection unit 218 or the coefficient identification signal selection unit 220. The process of substituting “0” which is the original coefficient is shown.

  In addition, since the run length is 3, the AC coefficient having the remaining two values zero is not subjected to the symbol decoding calculation process by the pipeline unit, and the coefficient identification signal 214 has the AC value having two values zero. It is only communicated that the coefficient exists.

  Note that at time T2, since one AC coefficient having a non-zero value following the three AC coefficients having a value of zero has not yet been processed, the HOLD signal 221 from the run-length decoding unit 202 is stored in FF207. Thus, an AC coefficient whose value is not zero (so-called significant coefficient) is held for the next processing.

  Next, at time T 3, the DC coefficient is input to the serial / parallel conversion unit 206, and a set of AC coefficients having a DC coefficient and a value of zero is output as the DCT coefficient data output signal 206 depending on the state of the coefficient identification signal 216. In the coefficient identification signal 215, AC coefficients having two values of zero are transmitted.

  One AC coefficient having a non-zero value following three AC coefficients having a value of zero is in the state of the coefficient identification signal 214 in parallel with the decoding calculation process performed by the level decoding unit 203. It is transmitted as the preceding coefficient C1. On the other hand, the coefficient C2 expressed by the coefficient identification signal 214 does not exist at the time T3.

  At time T3, the hold state by the HOLD signal 221 is released, and an AC coefficient with a run length of 1 appears as a symbol that is subsequently input, as shown in FIG.

  At time T4, the AC coefficient state having two remaining zero values of the AC coefficient of run length: 3 is input to the serial-parallel converter 206 by the coefficient identification signal 216, and a set of two AC coefficients having a value of zero Is output as the DCT coefficient data output signal 206.

  One AC coefficient having a non-zero value following the three AC coefficients having a value of zero is bypassed in the DPCM decoding unit 204 and transmitted to the subsequent stage, and the coefficient identification signal 215 is used. The state is transmitted as the preceding coefficient C1.

  Along with this, due to the input of the symbol corresponding to the AC coefficient of run length: 1 at time T3, an AC coefficient having a value of zero is transmitted as the coefficient C2 of the coefficient identification signal 215. An AC coefficient having a value of zero is transmitted as the coefficient identification signal 217 from the run-length decoding unit 202, and “X” in the coefficient C2 of the coefficient identification signal 215 is changed to “0” by selection by the coefficient identification signal selection unit 218. (A portion indicated by a one-dot chain line in the figure).

  In addition, one AC coefficient having a non-zero value following one AC coefficient having a value of zero is received by the coefficient identification signal 214 in parallel with the decoding operation processing by the level decoding unit 203. The state is conveyed as the preceding coefficient C1.

  At time T4, valid data does not appear as an input symbol. This explains the case where the present invention can cope with exception processing, and such processing occurs when the input of symbols from the variable length decoding unit 100 shown in FIG. 2 is delayed. In this case, the coefficient C2 represented by the coefficient identification signal 214 does not exist at the time T4.

  However, since such exception processing depends on the function of the variable-length decoding unit 100, the processing contents are different in an apparatus in which exception processing does not occur. At time T4 in that case, some value is entered in the coefficient C2 expressed by the coefficient identification signal 214.

  At time T5, a non-zero AC coefficient corresponding to an AC coefficient symbol with a run length of 3 is input to the serial-parallel converter 206, and an AC coefficient having an AC coefficient and a value of zero is input according to the state of the coefficient identification signal 216. The set is output as the DCT coefficient data output signal 206. One AC coefficient having a non-zero value following one AC coefficient having a value of zero is bypassed in the DPCM decoding unit 204 and transmitted to the subsequent stage. The state is transmitted as the preceding coefficient C1.

  On the other hand, the coefficient C2 expressed by the coefficient identification signal 215 does not exist at time T5. In addition, there is nothing in the coefficients C1 and C2 expressed by the coefficient identification signal 214 because no valid input symbol appeared at time T4. Then, as shown in FIG. 6, an AC coefficient with a run length of 4 appears as a subsequently input symbol.

  At time T6, the AC coefficient whose value is not zero corresponding to the AC coefficient symbol of run length: 1 is input to serial / parallel conversion section 206. On the other hand, coefficient identification is performed so that an AC coefficient having a value of zero is transmitted as coefficient C2 of coefficient identification signal 216 due to the input of a symbol corresponding to the AC coefficient of run length: 4 at time T5. The coefficient C2 is changed via the signal 219 and the coefficient identification signal selection unit 220 (a portion indicated by a one-dot chain line in the figure). As a result, a set of AC coefficients having a non-zero preceding value and an AC coefficient having a subsequent value of zero is output as the DCT coefficient data output signal 206.

  Furthermore, due to the input of the symbol corresponding to the AC coefficient of run length: 4 at time T5, AC coefficients having a value of zero are transmitted as the coefficients C1 and C2 of the coefficient identification signal 215. An AC coefficient having a value of zero is transmitted as the coefficient identification signal 217 from the run-length decoding unit 202, and “X” in the coefficient C2 of the coefficient identification signal 215 is changed to “0” by selection by the coefficient identification signal selection unit 218. Is done. (Locations indicated by alternate long and short dashed lines in the figure).

  Further, as the coefficient C1 represented by the coefficient identification signal 214, the last one of the four AC coefficients having a value of zero is transmitted, and the AC coefficient whose subsequent value is not zero is decoded by the level decoding unit 203. In parallel with the calculation processing, the state is transmitted as the preceding coefficient C2 by the coefficient identification signal 214. Subsequently, EOB (End of Block) appears as the last input symbol of the block as shown in FIG.

  In this way, according to FIG. 7, the sequence of the coefficients that are output in sequence as the coefficient identification signal 216 is “DC, 0, 0, 0, AC, 0, AC, 0,. Until the symbol EOB is input to the run-length decoding unit 202, it can be seen that it corresponds to the symbol sequence shown in FIG.

  As described above, according to the image decoding apparatus of the present embodiment, a symbol consisting of a set of run length and level input at one symbol per cycle is decoded into two DCT coefficients at maximum in one cycle. Can be output. That is, a high-speed decoding process can be performed with a minimum circuit configuration.

  In the present embodiment, for ease of understanding, the symbol decoding unit 200 has been described as outputting two DCT coefficients per cycle, but the present invention is not limited to this example. For example, although the control of various processes is complicated, the number of FF stages holding the coefficient identification signal (three stages of FF211, 212, and 213 in FIG. 1) is increased, and the “final output 206 as described with reference to FIG. By adjusting the truth table described in Fig. 5 so that `` pipeline processing that can output a predetermined number of DCT coefficients as '' can be realized, it is possible to output more than two DCT coefficients per cycle Is possible. Accordingly, the symbol decoding unit 200 can output 4 DCT coefficients, 8 DCT coefficients, and the like per cycle.

  In this embodiment, the target data for run-length encoding has been described as a “DCT coefficient having a value of zero” known in JPEG, MPEG, etc., but the present invention is not limited to a method for encoding zero-run. Any method that performs run-length encoding on some sample values is effective. In that case, the variable length decoding unit 100, the inverse quantization unit 300, and the inverse DCT unit 400 of the image decoding unit shown in FIG. 2 are not necessarily required.

[Other embodiments]
Although the embodiments have been described in detail above, the present invention can take embodiments as, for example, a system, an apparatus, a method, a program, or a storage medium (recording medium). The present invention may be applied to a system composed of a single device or an apparatus composed of a single device.

  In the present invention, a software program (in the embodiment, a program corresponding to the flowchart shown in the drawing) that realizes the functions of the above-described embodiment is directly or remotely supplied to the system or apparatus, and the computer of the system or apparatus Is also achieved by reading and executing the supplied program code.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, or the like.

  As a recording medium for supplying the program, for example, floppy (registered trademark) disk, hard disk, optical disk, magneto-optical disk, MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card , ROM, DVD (DVD-ROM, DVD-R).

  As another program supply method, a client computer browser is used to connect to an Internet homepage, and the computer program of the present invention itself or a compressed file including an automatic installation function is downloaded from the homepage to a recording medium such as a hard disk. Can also be supplied. It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  In addition, the program of the present invention is encrypted, stored in a storage medium such as a CD-ROM, distributed to users, and key information for decryption is downloaded from a homepage via the Internet to users who have cleared predetermined conditions. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  In addition to the functions of the above-described embodiments being realized by the computer executing the read program, the OS running on the computer based on the instructions of the program is a part of the actual processing. Alternatively, the functions of the above-described embodiment can be realized by performing all of them and performing the processing.

  Furthermore, after the program read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion board or The CPU or the like provided in the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

It is a block diagram which shows the detailed structure of the symbol decoding part in the image decoding apparatus which is one Embodiment of this invention. It is a block diagram which shows the structure of the image decoding apparatus in this embodiment. It is a table | surface which shows the kind of coefficient identification signal corresponding to one DCT coefficient. It is a table | surface which shows the combination of the coefficient identification signal corresponding to two DCT coefficients. It is a truth table which shows the logic which determines the coefficient identification signal of the next stage from an input symbol and a coefficient identification signal. It is a figure which shows the symbol sequence used for the symbol decoding example of this embodiment. It is a timing chart which shows the time-sequential change of the coefficient identification signal in the example of the symbol decoding process of this embodiment.

Claims (16)

A decoding device for decoding a symbol consisting of a number of consecutive insignificant coefficients followed by a set of significant coefficients,
Significant coefficient decoding means for decoding the significant coefficient of the symbol by a multistage pipeline configuration;
Coefficient transmission means for transmitting a coefficient identification signal indicating the type of coefficient processed in each stage of the multistage pipeline configuration in synchronization with the multistage pipeline configuration;
Control means for outputting the coefficient identification signal to the coefficient transmission means in accordance with the symbol, and for controlling the symbol supply to the significant coefficient decoding means in accordance with the number of consecutive insignificant coefficients of the symbol;
Coefficient output means for outputting a significant coefficient decoded by the significant coefficient decoding means in combination with an insignificant coefficient in response to the coefficient identification signal transmitted by the coefficient transmission means;
Coefficient changing means for changing a coefficient identification signal transmitted by the coefficient transmitting means according to control by the control means,
The control means determines a coefficient identification signal in a second clock cycle following the first clock cycle in accordance with a coefficient identification signal and an input symbol transmitted by the coefficient transmission means in the first clock cycle. A decoding device characterized by the above.   The decoding apparatus according to claim 1, wherein the coefficient identification signal represents a combination of a significant coefficient and an insignificant coefficient processed in each stage of the multistage pipeline configuration.   The decoding apparatus according to claim 2, wherein the coefficient identification signal represents a combination of a single significant coefficient and a single insignificant coefficient.   The decoding apparatus according to claim 2, wherein the coefficient identification signal represents a combination of a single significant coefficient and a plurality of insignificant coefficients. The symbol decoding apparatus according to any one of claims 1 to 4, characterized in that a run-length encoded data. The non-significant value coefficients is zero, non number of significant coefficients decoding apparatus according to claim 5, characterized in that the zero run length. A decoding device for decoding a symbol consisting of a set of a number of consecutive first samples and a subsequent second sample,
Decoding means for decoding the second sample of the symbols by a multistage pipeline configuration;
Transmission means for transmitting an identification signal indicating the type of sample processed in each stage of the multistage pipeline configuration in synchronization with the multistage pipeline configuration;
Control means for outputting the identification signal to the transmission means in response to the symbol, and for controlling the symbol supply to the decoding means in accordance with the number of consecutive first samples of the symbol;
Output means for outputting the second sample decoded by the decoding means in combination with the first sample in response to the identification signal transmitted by the transmission means;
Changing means for changing the identification signal transmitted by the transmission means in accordance with the control by the control means;
The control means determines an identification signal in a second clock cycle following the first clock cycle in accordance with an identification signal and an input symbol transmitted by the transmission means in the first clock cycle. Decoding device to perform. 8. The decoding apparatus according to claim 7 , wherein the identification signal represents a combination of a second sample and a first sample processed in each stage of the multistage pipeline configuration. 9. The decoding apparatus according to claim 8 , wherein the identification signal represents a combination of a single second sample and a single first sample. The identification signal decoding apparatus according to claim 8, wherein the representing the combination of the single second sample and a plurality of first sample. The symbol decoding apparatus according to any one of claims 7 to 1 0, characterized in that a run-length encoded data. Wherein the value of the first sample is zero, the number of samples of said first decoding device according to claim 1 1, wherein it is a zero run length. A decoding method performed by a decoding apparatus that has a multi-stage pipeline configuration and decodes a symbol including a number of consecutive insignificant coefficients followed by a significant coefficient,
Significant coefficient decoding means of the decoding apparatus, a significant coefficient decoding step of decoding the multi-stage pipeline structure of the significant coefficients of the symbol,
A coefficient transmission step in which the coefficient transmission means of the decoding apparatus transmits a coefficient identification signal representing the type of coefficient processed in each stage of the multistage pipeline configuration in synchronization with the multistage pipeline configuration;
The control means of the decoding device outputs the coefficient identification signal to the coefficient transmission means in accordance with the symbol, and the symbol to the significant coefficient decoding means in accordance with the number of consecutive insignificant coefficients of the symbol and a control step of controlling the supply,
Coefficient output means of the decoding apparatus, the coefficients in accordance with the transmitted the coefficient identification signal in the transmission step, the significant coefficient decoding step by a factor output in combination with the decoded significant coefficient of insignificant coefficients output Process,
The coefficient changing means of the decoding device comprises a coefficient changing step for changing a coefficient identification signal transmitted in the coefficient transmitting step according to the control by the control step,
In the control step, a coefficient identification signal in a second clock cycle following the first clock cycle is determined according to the coefficient identification signal and the input symbol transmitted in the coefficient transmission step in the first clock cycle < A decoding method characterized by the above. A decoding method performed by a decoding apparatus that has a multistage pipeline configuration and decodes a symbol composed of a number of consecutive first samples and a subsequent second sample set,
Decoding means of the decoding apparatus, a decoding step of decoding the second sample of the symbol by the multi-stage pipeline structure,
A transmission step in which the transmission means of the decoding device transmits an identification signal representing the type of sample processed in each stage of the multistage pipeline configuration in synchronization with the multistage pipeline configuration;
Control means of the decoding device, outputs the identification signal to said transmission means in response to the symbol, control symbol supplied to said decoding means according to the number of first consecutive samples of the symbol A control process ,
An output step in which the output means of the decoding device outputs the second sample decoded in the decoding step in combination with the first sample in accordance with the identification signal transmitted in the transmission step ;
The changing unit of the decoding device includes a changing step of changing the identification signal transmitted in the transmission step according to the control by the control step,
In the control step, an identification signal in a second clock cycle following the first clock cycle is determined according to the identification signal and the input symbol transmitted in the transmission step in the first clock cycle. A decoding method characterized by the above. The computer, computer program for causing function as each means included in the decoding apparatus according to any one of claims 1 to 1 2. Claim 1 5 storing a computer program described in a computer-readable recording medium.

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