JPS6028344A - Packet-switching exchange - Google Patents

Abstract

PURPOSE:To realize a high throughput by allowing a line controller acquiring the right of using a bus to write a storage memory address of a reception data to hard ware cue of a line controller corresponding to the information in the said reception data to attain exchange processing in a time equal to that of memory write. CONSTITUTION:Since high-order 5 bits of a path selecting register 2-6 are set to logical ''1'' at all times and an address is assigned to each line controller 1-1, an address reception circuit 2-2 of the line controller is started according to the address and a memory address on a data bus is fetched to a queue cue ralating to the hardware cue. On the other hand, when the address is fetched to the queue cue of the address reception circuit 2-2, the head address is displayed on a reception data address register 2-4. A sequence control circuit 2-3 gives a read request to a memory and when a signal of read OK is returned, a data transmission request is given to the line control circuit 2-3 to transmit the data onto the line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a packet switch, and particularly to a packet switch suitable for a packet relay switch that requires high throughput.

[Background of the invention]

In a DDX packet switch (see "Basic knowledge of DDX data exchange", edited by the Telecommunications Association), the central control unit analyzes the address information in the packet that the line control unit has captured into memory, and controls the line to which the packet is sent. However, since it requires processing by a program, it takes a long time to process one packet and has the disadvantage that throughput cannot be increased.

[Purpose of invention σ]

SUMMARY OF THE INVENTION An object of the present invention is to provide a packet switch that achieves high throughput, for example in a packet relay switch.

[Summary of the invention]

The configuration of the packet switch according to the present invention includes a plurality of line control devices that control transmission lines, a memory that temporarily stores received data, and a bus that sequentially grants the right to use the bus to the line control devices. The line control device that has obtained the right to use the bus writes the storage memory address of the received data to the hard queue of the line control device that corresponds to the information in the received data. It is configured so that it can be exchanged.

As an additional note, the present invention considers that it is difficult to increase throughput with program control by a central control unit, so the relay exchange only performs transfers between data lines, and as a measure to achieve this, This system involves transmitting and receiving data between line control devices only by transmitting and receiving data addresses based on the outgoing line number in the data.

[Embodiments of the invention]

An embodiment of a packet switching device according to the present invention will be explained with reference to FIGS. 1 to 3.

Here, FIG. 1 is an overall configuration diagram of a packet relay switch according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a line control device that also shows its connections, and FIG. 3 is its data format. FIG.

In the figure, l-1 is a line control device, 1-2 is a memory, and 1-3
is a bus right control circuit, 1-4 is an address bus, 1-
5 is an f-tabus, 1-6 is a control bus (I), 2-1 is a line control circuit, 2-2 is an address receiving circuit, 2-3 is a sequence control circuit, 2-4 is a received data address register, 2-5 is a transmission/reception timing generation circuit, 2-6 is a route selection register, 2-7 is a reception data register, 2-8 is a transmission data address register, and 2-9 is a transmission data register. What is displayed as address and data are address buses 1-4. Those related to data bust 5 are shown, and other items indicated as memory requests, OK, etc. are related to control bust 6.

That is, as shown in FIG. 1, the packet relay switch according to the embodiment of the packet switch controls the transmission line.
A plurality of line control devices 1-1. A memo to temporarily store received data! The right to use the J121 bus is sequentially granted to line controller 1.
-1 is comprised of a bus right control circuit 1-3.

First, the bus right control circuit 1-3 sequentially selects the line control device 1-1 every 1 μs and turns on the select signal shown in FIG. 2.

When the ON of the select signal is detected, the transmission/reception timing generation circuit 2-5 shown in FIG.
For the next 500 μs, the transmission timing φ1 is turned on, and the reception timing φ2 is turned on for the next 500 μs. In addition, when the select signal is OFF, the transmission and reception timing φ
Both φ2 and φ2 are OFF. These transmission and reception timings φl and φ2 are used, for example, as a clock signal in the line control circuit 2-1.

The line control circuit 2-1 also controls the frame synchronization line, and when synchronization is established, reports a synchronization establishment signal to the sequence control circuit 2-3.

Next, the sequence/sequence control circuit 2-3 controls the previous memory 1.
-2 issues a memory hunt request signal as shown in the figure, and memory 1-2 hunts the memory block in response, displays the address on takebust 5, and sends the memory hunt request signal to sequence control circuit 2-3. ) returns an OK signal.

In this way, when the sequence control circuit 2-3 receives the memory handle OK signal, it takes in the data on the data bust 5 into the reception data register 2-7, transfers it to the transmission data address register 2-8, and then transfers it to the transmission data address register 2-8. Control circuit 2-
1 to issue a data reception request.

Upon receiving the data, the line control circuit 2-1 reports data reception completion for each byte to the sequence control circuit 2-3, and the sequence control circuit 2-3 transfers the received data to the transmission data register 2-9. It is something to do.

Next, as described above, when the transmission timing φ1 turns ON, the sequence control circuit 2-3 transfers the contents of the transmission data address register 2-8 to the address bus 1-4, and the contents of the transmission data register 2-9. is sent to the data bus 5 and a write request is made, and then the line control circuit 2
-1 is for issuing a data reception request.

The first byte of the received data is an outgoing line number as shown in FIG. 3, which will be described later, and its contents are also stored in the strategy selection register 2-6.

When the line control circuit 2-1 detects the end of data, it sends a data reception completion report to the sequence control circuit 2-3.

In response, the sequence control circuit 2-3 transfers the contents of the transmission data address register 2-8 to the transmission data register 2-9, and transfers the contents of the route selection register 2-6 to the transmission data address register 2-8. It transfers the data and issues a write request.

Therefore, the upper 5 bits of the strategy selection register 2-6 are
It is always set to '1'', and each line control device 1-1
Since addresses from H"F8" to H"FF" are assigned to the The memory address on the data bus 5 is taken into the waiting queue related to the queue. Further, when the OK signal is returned, the sequence control circuit 2-3 issues a memory hunt request.

On the other hand, when an address is taken into the waiting queue of the address receiving circuit 2-2, the first address is displayed in the received data address register 2-4.

The sequence control circuit 2-3 makes a read request to the memory 1-2, and when read OK is returned, reads the data into the reception data register 2-7, and then sends the data to the line control port/path 2-3. Make a request and have data sent out on the wire.

Next, when the line control circuit 2-1 finishes sending the data, it returns data sending completion and the sequence control circuit 2-3
is to perform the memo IJ IJ-code again.

Since the memory 1-2 reports read completion when there is no more data, the sequence control circuit 2-3 issues a memory free request, extracts the first address from the address receiving circuit 2-2, and stores it in the received data address register 2. -4.

The above operation is repeated until there is no more received data.

FIG. 3 shows an example of a data format. In this example, the first byte is the output route number.

Here, in Figure 3, F (fragnokens) and F
The data between the output path number and Fe2 (7 frame check sequence) indicates the data format of the level procedure class of one division in the packet switch.

According to this embodiment, memory addresses are transferred, that is, exchanged, between line control devices with only simple sequence control, so packets are exchanged in one cycle.
High throughput is achieved.

In other words, conventionally, a CPU requires l to process one packet.
Since the time was about ms, a maximum throughput of only 1,000 buckets could be obtained.

According to this embodiment, since the outgoing line number is inserted into the data and the data is exchanged between the line control devices only by filling in the memory address, the exchange process can be performed in the same time as memory write. This has the effect of increasing throughput.

In addition, in the case of processing by the CPU, if short packets are input in excess of the processing capacity, the input packets cannot be processed, but in this embodiment, since the exchange is performed within the memory access cycle, data transfer on the control bus Speed>If the total data transfer speed of the line is satisfied, it can be exchanged regardless of the packet length.

Although the above-mentioned embodiments relate to relay exchanges, the present invention has a general-purpose configuration as a wide-range exchange.

〔Effect of the invention〕

According to the present invention, it is possible to provide a packet switch that can achieve high throughput, and it can be said that the present invention has excellent practical effects.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of a packet relay switch according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a line control device that also shows its connections, and FIG. 3 is an illustrative diagram of its data format. It is. 1-1... Line control device, 1-2... Memory, 1-
3...Bus usage right control circuit, 1-4...Address bus, 1-5...Data bus, 1-6...Control bus,
2-1... Line control circuit, 2-2... Address receiving circuit, 2-3... Sequence control circuit, 2-4...
Reception data address register, 2-5... Transmission/reception timing generation circuit, 2-6... Route selection register, 2-
7... Receive data register, 2-8... Transmit data address '((1 other person) ゛-1

Claims (1)

[Claims] 1. A bus system comprising a plurality of line control devices that control transmission lines, a memory that temporarily stores received data, and a bus right control circuit that sequentially grants bus use rights to the line control devices. The line control device that has obtained the usage right writes the storage memory address of the received data to the 7-docue of the line control device that corresponds to the information in the received data, so that data can be exchanged. A packet switching device characterized in that it is configured as follows.