JP2865314B2 - Packet communication device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a packet communication device for packetizing and transmitting voice information and the like.

(Prior Art) There is a network as shown in FIG. 3 as a system for packetizing and transmitting voice information and the like. In FIG. 3, 1 is a multiplex line, 2A, 2B, and 2C are packet switches, and 3A to 3A.
3C is a packet end, 4A to 4C is an exchange, 5 is a telephone.For example, a voice input to the packet terminal 3A is encoded here, then decomposed into predetermined information units, and a packet to which destination information is added. The packet switch 2A, 2
The packet is transmitted to the destination packet terminal 3B via B.

FIG. 4 is a block diagram showing the internal configuration of the packet switches 2A to 2C. The terminal interface TINF provided for each packet terminal, the line interface LINF with the multiplex line 1, the control unit CONT, the bus access control Department
An ARB, an interrupt control bus BUS1, a control bus BUS2, an access control bus BUS3, and a data bus BUS4 are provided. When each terminal interface TINF receives a call packet from a packet terminal connected to itself, it interrupts the control unit CONT using the interrupt control bus BUS1. When confirming the interrupt, the control unit CONT accesses the memory in the terminal interface TINF (not shown) using the control bus BUS2, and confirms the call information (information such as the destination number and the window size). Thereafter, the control unit CONT outputs an access request for the data bus BUS4 to the access control bus BUS3 in order to transmit a connection request packet to the opposite packet terminal which is the opposite node. If the control unit CONT obtains the data bus access right,
After that, the data bus BUS4 is used for line interface.
Transfer the connection request packet to LINF. Then, the line interface LINF assembles the connection request packet in the same manner as the data packet, and sends it out to the multiplex line 1. On the other hand, when a packet of connection permission or non-permission is returned from the opposite packet terminal of the opposite node, the line interface LINF transfers the packet to the control unit CONT. When receiving the connection permission packet, for example, the control unit CONT creates a connection table in a memory (not shown) between the line interface LINF and the terminal interface TINF via the control bus BUS2 and sends the connection permission packet to the terminal interface TINF. Therefore, terminal interface TI
The NF sends a connection permission packet to the corresponding packet terminal, and then moves to a data transfer phase. In the data transfer phase, the terminal interface TINF is connected to the data bus BUS4
To send a data packet to the line interface Linf. At this time, the header section H shown in FIG. 5 is added to the information section D using the connection table created by the control section CONT, and this is transmitted as a data packet. After storing the data packet in the buffer, the line interface LINF sends it out to the multiplex line 1. This operation is similarly repeated for data packets during the data transfer phase. In the case of disconnection, the same operation as in the case of a connection request is performed except that the connection table is deleted.

FIG. 6 is a diagram showing the internal configuration of the line interface LINF (only the direction of transmission to the multiplex line is shown), 11 is a data bus interface unit, 12 is an address match check unit, 13 is a packet distribution unit, 14-1. 14-n are packet queues of a plurality of rows stored in the buffer memory BM, 15 is a transmission packet decision unit, and 16 is a line interface unit.
The data bus interface unit 11 is the data bus BU of FIG.
This is the part that interfaces with S4.
Packets are transmitted and received according to the timing of BUS4. The address match checking unit 12 is a unit for comparing whether or not the received packet is addressed to itself. If the received packet is addressed to itself, the packet is transferred to the packet distribution unit 13, but otherwise, discarded. The packet distribution unit 13 performs 14- based on the information in the header H of the packet.
This is a part for deciding which of the packet queues 1 to 14-n is to be arranged. The information of the header portion H includes connection-related information, information such as priority regarding immediacy and the like, and the packet distribution unit 13 divides the packet into a packet queue 14- according to, for example, priority information. 1 to 14-n. Reference numeral 15 denotes a part for determining which of the packet queues 14-1 to 14-n should take out a packet. Reference numeral 16 denotes a portion for interfacing with the multiplexing line 1;
The packet is transmitted in synchronization with the clock.

FIG. 7 is a diagram showing details of the packet distribution unit 13, the buffer memory BM and the transmission packet determination unit 15 shown in FIG. 6, where 6-1 is a packet distributor, 6-2 is a distribution control unit,
CLK is a timer, 7-11 to 7-n1 are timer buffer memories for sequentially storing and outputting times from the timer CLK in a first-in first-out (FIFO) format, and 7-12 to 7-n1.
7-n2 is a data buffer memory for sequentially storing and outputting packets in a first-in first-out (FIFO) format, 7-13 to 7-n3 are retention counters for counting the number of packets stored in the data buffer memory, 8 -1
Denotes a transmission unit, and 8-2 denotes a transmission packet determiner.

The packet distributor 6-1 transfers the packet from the data bus interface unit 11 of FIG.
It is distributed to any one of -12 to 7-n2 and transmitted.
The distribution control unit 6-2 identifies the priority information indicated by the header H of the packet from the data bus interface unit 11, and, based on the priority information, determines the data buffer memory to which the packet is to be distributed by the packet distributor 6 -1
Has been instructed. For example, if the priority information includes class 1 to class n, and these classes 1 to n correspond to the respective data buffer memories 7-12 to 7-n2, the packet including the priority information of class 1 is The packet transmitted from the packet distributor 6-1 to the data buffer memory 7-12, and the packet containing the priority information of class 2 is transmitted from the packet distributor 6-1 to the data buffer memory 7-22. Is transmitted from the packet distributor 6-1 to the data buffer memory 7-n2.

Each of the data buffer memories 7-12 to 7-n2 sequentially stores the packets distributed by the packet distributor 6-1. As a result, classes 1 to 1 are stored in the data buffer memories 7-12 to 7-n2.
A respective packet queue of class n is formed.

The timer buffer memory 7-11 sequentially stores the time from the timer CLK every time a packet is input to the data buffer memory 7-12. Similarly, the timer buffers 7-21 to 7-n1 are stored in the data buffer memory 7-n. 12 to store the time from the timer CLK each time a packet is input to the data buffer memory 7-n2. As a result, time columns are respectively formed in the timer buffer memories 7-11 to 7-n1, and the time columns in the timer buffer memories 7-11 to 7-n1 are stored in the data buffer memories 7-n. It corresponds to each packet queue in 12-7-n2. For example, each head time in each time sequence in each of the timer buffer memories 7-11 to 7-n1, that is, each time inputted first, is stored in each of the data buffer memories 7-12 to 7-n1. It shows the input time of each head packet in the packet queue, that is, the first input packet.

The sending unit 8-1 is provided with each data buffer memory 7-12 to 7-
The packet at the head of the packet queue is sequentially read from any one of n2, and the read packets are sequentially transmitted. The transmission packet determining unit 8-2 determines the current time from the timer CLK, the time at the beginning of each of the timer buffer memories 7-11 to 7-n1, and each of the priorities corresponding to the data buffer memories 7-12 to 7-n1. The first packet to be transmitted immediately is selected from among the first packets in each of the data buffer memories 7-12 to 7-n1 based on the degree classes 1 to n, and this first packet is sent to the sending unit 8-1. To instruct. Here, an arithmetic expression for selecting the head packet performed by the transmission packet determining unit 8-2 is shown below.

Here, Dj indicates the time during which the first packet in the data buffer memory of the priority class j stays in the data buffer memory, and indicates the first time in the timer buffer memory corresponding to the data buffer memory, that is, the first packet. Is the difference between the input time and the current time. Wj indicates a weighting factor previously given to the priority class j, and Wj−1>Wj> Wj + 1.

That is, for each head packet in each of the data buffer memories 7-12 to 7-n2, each individual packet D1W1
To DnWn are respectively obtained, a packet corresponding to the largest value among these values D1W1 to DnWn is selected as a packet to be transmitted immediately, and this packet is transmitted from the transmission unit 8-1. Such an operation is performed sequentially for each packet transmission.

However, selecting a packet to be transmitted immediately based on the above equation (1) is the most direct and appropriate method for ensuring transmission quality, but calculates the value Dj in the calculation process. , A multiplication for calculating the value DjWj, and a comparison operation for obtaining the maximum value among the individual D1W1 to DnWn.
The amount of calculation per packet performed in step 2 is 0 (2n), which is not small. For this reason, the processing speed could not be increased or the upper limit of the number of classes n was determined due to the lack of processing capability of the transmission packet determination unit 8-2. Further, the arithmetic units for performing the subtraction and the multiplication may be distributed for each data buffer memory. However, in this case, the scale of the hardware becomes very large, and the integration is not performed because the configuration is not systolic. Difficult and poor expandability.

(Problems to be Solved by the Invention) As described above, in the conventional packet communication device, the subtraction, multiplication, and comparison operations are performed in the transmission packet determination unit, so that it is difficult to increase the speed of the arithmetic processing. There is a problem in that integration is difficult because the configuration is not systolic.

Accordingly, it is an object of the present invention to provide a packet communication device suitable for high-speed operation processing and integration.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention provides an input packet in a predetermined information unit to which each of the immediacy priority information is added, corresponding to the immediacy priority information of the packet. A packet communication device for distributing the packets to a plurality of packet queues, sequentially storing the packets, selecting one of the plurality of packet queues, and sequentially transmitting packets from the selected packet queue; Counting means for counting a clock of a cycle corresponding to each packet queue for each packet while the packet is staying, and a packet queue for transmitting the packet based on the count value of the staying time counting means. And selecting means for selecting.

(Operation) According to the present invention, while a packet stays in each packet queue, a clock of a cycle corresponding to each packet queue is counted by the counting means corresponding to each packet, and based on the count value, Select the packet queue to send the packet.

Specifically, clock generating means for generating clocks of different periods corresponding to each packet queue is provided, and the clock corresponding to each packet queue generated from the clock generating means is counted by the counting means. From the input to the packet queue until it reaches its final position. Then, based on the count value of the packet counting means at the last position of each packet queue, a packet queue to send out the packet is selected.

With such a configuration, the configuration becomes very simple,
In addition, since no complicated arithmetic processing is required, it is possible to provide a packet communication device that can be integrated and reduced in size.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a packet communication apparatus according to the present invention. Here, a partial configuration which is a substitute for the packet distribution unit 13, the buffer memory BM, and the transmission packet determination unit 15 shown in FIG. Is shown. In the figure, 21 is a packet distribution unit, 22-1 to 27-1, 22-2 to 27-
2,..., 22-n to 27-n are buffer basic units, 28 is a transmission control unit, 29 is a clock generation unit, 31 is an available pointer buffer, 32 is a write packet pointer, 33 is a read packet pointer, and 34 is data Memory.

The usable pointer buffer 31 stores an address string composed of a plurality of addresses. The start address of this address string is stored in the packet distribution unit 21 and the write pointer 32.
And the address transmitted from the transmission control unit 28 is stored at the end of the address sequence, thereby updating the address sequence while securing the number of stored addresses. .

The data memory 34 receives a packet from the data bus interface unit 11 shown in FIG. 6, and writes this packet from the available pointer buffer 31 to the address specified via the write packet pointer 32. The data memory 34 reads a packet at an address designated by the transmission control unit 28 via the packet pointer 33, and transmits the packet to the line interface unit 16 in FIG.

The packet distributor 21 identifies the priority information indicated by the header H (shown in FIG. 5) included in the same packet as the packet input to the data memory 34, and based on the priority information, Basic unit 22-1,22
-2, ..., 22-n is selected. And
The packet distributor 21 inputs the same address as the address specified in the data memory 34 from the available pointer buffer 31, and sends this address to the selected first bus basic unit. For example, class 1,2,
, N, and these classes 1, 2,..., N correspond to the respective buffer basic units 22-1, 22-2,. When the packet containing the priority information of the class 2 is written to the predetermined address of the data memory 34, the address is transmitted to the buffer basic unit 22-1 corresponding to the priority class 1 and the packet containing the priority information of the class 2 is stored in the predetermined address of the data memory 34 Is written to the buffer basic unit 22-2 corresponding to the priority class 2; similarly, when a packet containing priority information of class n is written to a predetermined address of the data memory 34, Is the priority class n
Is transmitted to the buffer basic unit 22-n corresponding to
Such processing is performed every time a packet is stored in the data memory 34. At this time, in each of the buffer basic units 22-1 to 27-1 in the first column, the address moves to the last basic unit that is not occupied. In addition, each buffer basic unit 22-2 in the second column
27-2, the address moves on the basic unit to the last basic unit that is not occupied. Similarly, each buffer basic unit 22-n to 27-n in the n-th column
In, the address moves on the basic unit to the last unoccupied basic unit. For this reason,
The addresses of the packets belonging to the priority class 1 are sequentially stored in the buffer basic units 22-1 to 27-1 in the first column, and this address column corresponds to the priority class 1 packet queue. The addresses of the packets belonging to the priority class 2 are sequentially stored in the buffer basic units 22-2 to 27-2 in the second column, and this address column corresponds to the priority class 2 packet queue. I have. Similarly, the address of each packet belonging to the priority class n is sequentially stored in each of the buffer basic units 22-n to 27-n in the n-th column. ing.

The transmission control unit 28 controls the last buffer basic unit 27-
Read out the address of the packet to be transmitted immediately from any of 1, 27-2,..., 27-n and transmit this address. This address is the read packet pointer
The packet at this address is specified from the data memory 34 via the data memory 34 and transmitted from the data memory 34. Further, this address is used when read from the buffer basic unit, that is, an address indicating the portion of the transmitted packet in the data memory 34, and is located at the end of the address string in the available pointer buffer 31. It is added.

Therefore, an address string including a plurality of unused addresses is formed in the available pointer buffer 31, and each time a packet is input to the data memory 34, the head address of the address string is changed to the data memory 34 and the packet distribution unit.
To 21 each. Then, the packet is stored at the address in the data memory 34, and the address is transmitted through the packet distribution unit 21 to the buffer basic unit corresponding to the priority class indicated by the priority information of the packet. As a result, an address sequence corresponding to the packet queue of the priority class 1 is stored in each of the buffer basic units 22-1 to 27-1 in the first column, and each of the buffer basic units 22-2 to 22-1 in the second column is stored. 27-2 stores an address sequence corresponding to the priority class 2 packet queue, and similarly stores each buffer basic unit in the n-th column.
22-n to 27-n store an address string corresponding to a packet queue of priority class n. Further, the transmission control unit 28 transmits the last buffer basic unit 27-1, 27-2,
, 27-n, the address is read out,
This address is sent to the data memory 34 via the usable pointer buffer 31 and the packet pointer 33.
As a result, from the data memory 34, each of the priority classes 1 to n
Of the packet queue in the packet queue of the packet queue is transmitted.

FIG. 2 shows the structure of the name buffer basic unit, where k-1 in each buffer basic unit in the ith column.
The example of the nth buffer basic unit, the kth buffer basic unit, and the (k + 1) th buffer basic unit are illustrated.

These buffer basic units each include a counter 41, a register 42, and a ripple shift controller 43. The counter 41 receives a clock signal from the clock generator 29 (shown in FIG. 1) and counts this clock signal. The register 42 is the packet distribution unit 2
(Shown in FIG. 1) are sequentially stored. The ripple shift controller 43 controls the counter 41 and the register 42, and the transmission control unit 28
When a shift write signal is input from the control circuit (shown in FIG. 1) via the next-stage ripple shift controller 43, the counter
The count value indicated in 41 is shifted to the next-stage counter 41, and the address indicated in the register 42 is shifted to the next-stage register 42.

The transmission control unit 28 transmits a shift write signal when an address is read from the register 42 of the last buffer basic unit or when a request signal is input from the packet distribution unit 21 via each ripple shift controller 43. When transmitting the address to the register 42 of the first buffer basic unit, the packet distribution unit 21 transmits a request signal to the ripple shift controller 43 of the buffer basic unit.

As a result, the respective addresses of the address sequence corresponding to the priority class i packet queue are stored in the respective registers 42 of the respective buffer basic units in the i-th column.

On the other hand, the counter of the head buffer basic unit in the i-th column
When the address from the packet distribution unit 21 is stored in the register 42 of the buffer basic unit 41, the count value is initialized and the count is started. Each time the address is shifted to the next-stage register 42, the counted value is shifted to the next-stage counter 41, and the counting of the counted value is continued in each counter. For this reason, the counter 41 of the last buffer basic unit indicates the count value corresponding to the residence time of the address in the register 42 of the buffer basic unit.

By the way, in each buffer basic unit in the first column to each buffer basic unit in the n-th column shown in FIG. 1, a clock signal having a different frequency for each column, that is, for each priority class, is supplied from the clock generator 29. Have been added. For example, each buffer basic unit 22-1 to 27 in the first column
The counter 41 -1 clock signal of a frequency f ₁ corresponding to the priority class 1 is added, also in the counter 41 of each buffer base unit 22-2～27-2 the second row priority class 2 clock signal of the corresponding frequency f ₂ is applied, likewise each buffer basic unit of the n-th column 22-n~27
The frequency corresponding to the priority class n is stored in the counter 41 of −n.
A clock signal of fn is applied.

Here, the last buffer basic unit 27- in the first column
The residence time of listening integrated value of the address in the register 42 in 1 'and _1, the residence time integrated value D' D When the time unit T ₁ showing the cumulative interval for ₁ and 1 / f _1, the buffer base unit 27 The count value in the counter 41 at -1 is the accumulated residence time value D' ₁ . Also, the residence time integrated value of the address in the register 42 in the buffer base unit 27-2 of the last second column 'and _2, the residence time integrated value D' D ₂ time units T ₂ showing the integration interval for Is 1 / f ₂ , the counter 41 in the buffer basic unit 27-2
The count value inside is the accumulated residence time value D' ₂ . Similarly, the accumulated time of the address in the register 42 in the last buffer basic unit 27-n in the n-th column is D' _n ,
When 1 / f _n time units T _n indicating the integration interval for the residence time integrated value D _'n, the buffer base unit 27
The count value in the counter 41 at −n is the accumulated residence time value D′ _n .

Further, a time unit T used at the time of counting in each buffer basic unit in the (i-1) -th column belonging to the priority class i-1.
a _i-1, priority class i belonging to the i-th time unit T _i used in the timing in each buffer base unit column T _i-1 <
Set in advance in the relationship of T _i. In this case, the sending control unit 2
8 is the last buffer basic unit 27-1, 27-2, ..., 27
At -n, the largest accumulated residence time value among the accumulated residence time values D' _{1 to} D' ₂ in the respective counters 41 is selected. The comparison operation for this is shown in the following equation (2).

Then, the transmission control unit 28 reads an address from the register 42 in the last buffer basic unit having the counter 41 indicating the selected residence time integrated value, and reads the address usable pointer buffer 31 and the packet pointer 33. To the data memory 34 via the The data memory 34 transmits the packet of the designated address to the line interface unit 16 (shown in FIG. 6).

Therefore, priority class i-
1 has a higher priority, and the head address of the address string stored in each buffer basic unit in the (i-1) -th column is higher than the head address of the address string stored in each buffer basic unit in the i-th column. Data memory 34
To instruct. That is, the first packet of the packet queue belonging to the priority class i-1 has a higher priority than the first packet of the packet queue belonging to the priority class i, and the waiting time until the packet is transmitted from the data memory 34 is Higher priority packets are shorter.

It should be noted that the weighting coefficient Wj in the above-mentioned equation (1) of the conventional example is
The time unit T _j in the above equation (2) of this embodiment has a relationship as shown in the following equation (3).

As described above, in this embodiment, when the packets of the respective priority classes 1 to n are input, the respective residence time integrated values D ′ _{1 to} D ′ _n of these packets are counted at the cycle for each priority class, respectively. The maximum value of the accumulated residence time values D' _{1 to} D' _n is selected, and the packet of the selected accumulated residence time value is preferentially transmitted. For this reason,
By simply performing a comparison operation on each of the accumulated residence time values D ′ _{1 to} D ′ _n , a priority packet can be selected.
High-speed processing becomes possible. Furthermore, counters are cascaded to FI
Because of the simple structure of connection in the FO format, integration is easy.

〔The invention's effect〕

As described above, according to the present invention, the residence time integrated value of each packet belonging to each priority class is counted at a cycle for each priority class, and these residence time integrated values are simply calculated. A simple structure in which a priority packet can be selected and the counter is cascaded and connected in a FIFO format is advantageous in that high-speed processing and integration can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a packet communication apparatus according to the present invention, FIG. 2 is a block diagram showing a configuration of a buffer basic unit in the embodiment shown in FIG. 1, and FIG. FIG. 4 is a block diagram showing a configuration of the packet switch shown in FIG. 3, FIG. 5 is a block diagram showing a configuration of a packet, and FIG. 6 is a diagram of FIG. 7 is a block diagram showing a conventional example of the line interface shown in FIG. 7, and FIG. 7 is a block diagram showing a main part of the line interface shown in FIG. 21: Packet distribution unit, 22-1 to 27-1, 22-2 to 27-2,
22-n to 27-n Buffer basic unit, 28 Transmission control unit 29 Clock generation unit 31, Usable pointer 32 Write packet pointer 33 Read packet pointer 34 ... Data memory, 41 ... Counter, 42 ... Register, 43 ... Ripple shift controller.

Claims (2)

(57) [Claims] An input packet in a predetermined information unit to which each of the immediacy priority information is added is distributed to a plurality of packet queues provided corresponding to the immediacy priority information of the packet, and sequentially stored. A packet communication apparatus for selecting any one of the plurality of packet queues and sequentially transmitting packets from the selected packet queue, wherein each packet queue corresponds to each packet queue while the packet queues. A packet communication device, comprising: counting means for counting clocks of a cycle corresponding to each packet; and selecting means for selecting a packet queue for transmitting the packet based on the count value of the counting means. . 2. A clock generating means for generating clocks of different periods corresponding to each packet queue, wherein the counting means converts a clock corresponding to each packet queue generated from the clock generating means into a packet. From the input to the packet queue until it reaches its final position, counting is performed for each packet, and the selecting means, based on the count value of the packet at the final position of the packet queue by the counting means, The packet communication device according to claim 1, wherein a packet queue to be transmitted is selected.