JPS6028079B2 - Semiconductor static memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor static memory device such as a MOS type EPROM.

FIG. 1 shows the configuration of the output circuit section in a conventional MOS type EPROM.

1 is a charging MOS transistor, 2 is a transfer gate MOS transistor
These are enhancement (E) type transistors with a threshold voltage of approximately IV.

The power supply Vcc is usually a standard 5V, and the transistors 1,
Approximately 3, which is obtained by dividing the power supply Ncc by resistors 3 and 4, is applied to the gate of 2.
V is applied. Therefore, the high level of the common sense node 5 across the memory cell array is approximately 2V, which is the gate voltage of transistors 1 and 2, approximately 3V, minus their threshold voltage, approximately IV. The memory cell is, for example, a MOS type memory transistor with a floating gate. In this way, the sense node 5 is normally suppressed to W or less, and therefore the drain voltage of the cells in the memory cell array is usually suppressed to 2V or less. As a result, erroneous writing due to the hot electron effect of the memory cell at the time of reading and floating with the drain occur. A threshold voltage drop in the memory cell due to capacitive coupling between gates is prevented.

However, this circuit has the following disadvantages, for example, when checking the write amount of memory cells.

The write heavy check is performed by externally changing the power supply Ncc and reading the potential change of the sense contact. At this time, the voltage of the selected row decoder line, that is, the control gate voltage of the memory cell, is changed from the power supply Vcc. When the voltage is raised or lowered by changing the voltage, the gate and drain of the MOS transistor both change, so the voltage at the sense node 5 changes at the same time. In this way, sense node 5
When the voltage of , that is, the drain voltage of the memory cell moves with the power supply Vcc, the potential of the floating gate changes due to capacitive coupling, and the threshold value of the memory cell changes equivalently.
It becomes impossible to check the exact amount of writing. In addition to the above-mentioned inconvenience when checking the amount of writing, this circuit also has the disadvantage of a small design margin.

For example, if the threshold value of a memory cell increases as a result of, for example, variations in the amount of ion implantation, and its on-current decreases, the access time will eventually become slower. The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a semiconductor static memory device that allows accurate checking of the amount of data written to a memory cell.

This invention controls the gate of a charging MOS transistor that charges the sense contact of a memory cell array consisting of a MOS type memory transistor with a floating gate by the output of a constant voltage generation circuit that does not depend on the power supply voltage, and the sense contact is connected to the power supply. The main point is that it is not linked to voltage.

Examples of the present invention will be described below. Figure 2 shows a MOS type EP using a P-type substrate and consisting of an n-channel E/D circuit.
This is an example of a ROM. In the figure, 11 is a memory cell array of, for example, m rows x n columns, and memory cell transistors 11i
j (i ni 1, 2,..., m, i=1, 2,...
, n) is an E-type MOS transistor with a double silicon gate structure with a floating gate, and its threshold value is approximately 2.
It is V. 1 2j is a MOB transistor for column selection,
It is an E type with a threshold voltage of about IV.

The charging transistor 14 for charging the common sense node 13 and the transfer gate transistor 15 connecting between the sense node 13 and the sense amplifier have a threshold value of approximately OV.
This is a B-type MOS transistor. The gates of these transistors 14 and 15 are controlled by the output of a constant voltage generating circuit 16. The constant voltage generation circuit 16 outputs a constant voltage independent of the power supply Ncc, and a depletion (D) type MOS transistor (IMOS transistor) 16 with a value voltage of approximately 13V, OV B-type MOS transistor (buffer MO
S transistor) 162 and an E-type MOS transistor (second MOS transistor) 163 with a threshold voltage of approximately 2V, which has a double silicon gate structure and is made under the same conditions as the memory cell, are connected in series. A power supply Vcc is applied to the transistors 16 and 162, and the connection point between the transistors 16 and 162 is used as an output terminal.

The gates of transistors 16, 162 are both connected to the output terminal, and the gate of transistor 163 is connected to the drain. In this constant voltage generation circuit 16, when the output terminal voltage exceeds the threshold voltage of the transistor 163, the transistor 163 turns on and tries to lower the output terminal voltage, so that the output terminal voltage becomes below the threshold voltage of the transistor 163. When the voltage is about to drop, the transistors 16, 162 turn on and try to increase the output terminal voltage, so that the output terminal voltage becomes the threshold voltage of the transistor 163 plus alpha.

The positive alpha is determined by the dimensions and threshold voltages of transistors 16-163. In this case, since the transistor 16 is of the D type and exhibits constant current characteristics independent of the power supply Vcc, the output terminal voltage becomes a constant value that is not dependent on changes in the power source Ncc. Here, in the constant voltage generation circuit 16, the E type transistor 162 is replaced by the B type transistor 14,
15 is provided as a buffer in order to alleviate the influence of variations in the threshold voltages on the sense node 13.

That is, when the threshold voltages of the B-type transistors 14 and 15 change in the negative direction, the sense node 13 tries to rise, but at this time, the threshold voltage of the B-type transistor 162 also changes in the negative direction and becomes constant. It acts in the direction of lowering the output terminal voltage of the voltage generating circuit 16 and suppresses the rise in the sense node 13.
Similarly, when the value voltage changes in the positive direction, the fluctuation of the sense node 13 is compensated for in the same way. Note that the B-type transistor 17i has the same function as the charging transistor 14,
Although this prevents the drain of the memory cell array 11 from being in a floating state, it may be removed depending on the design.

With such a configuration, the threshold values of the transistors 14 and 15 are approximately OY, so the output voltage unrelated to the power supply Vcc generated by the constant voltage generation circuit 16 is directly applied to the sense node 13.

Therefore, even when checking the write amount by changing the power supply Vcc and raising and lowering the control gate voltage of the memory cell, the voltage at the sense node 13 does not fluctuate and is kept at a constant voltage, making it possible to accurately check the write amount. becomes possible. Also, the transistor 16 of the constant voltage generation circuit 16
3 is made under the same conditions as the memory cell transistor 11ii, and the threshold of the memory cell transistor 11ij is
When the value is high, the voltage at the sense node 13 becomes high as well, so the on-current of the memory cell transistor 11ij becomes less dependent on its threshold value, and the design margin in terms of process and circuit becomes large. FIG. 3 shows a modification of the constant voltage generating circuit 16 in the embodiment shown in FIG.

In addition to the transistors 161 to 163, an E-type MOS transistor 64 is added, and the transistors 16 and 16 are
Connect the connection point of 2 to the gate of the transistor 164,
The gates of transistors 162 and 163 are connected to transistor 1.
64 source, and this source is used as the output terminal. This circuit also provides a constant output voltage independent of the power supply Vcc, which is determined by the voltage of the transistor 163 and the characteristics of the transistors 16, 162. As described above, according to the present invention, by keeping the sense node constant regardless of the power supply voltage, it is possible to accurately check the write amount by externally varying the power supply voltage.

Furthermore, by using a second MOS transistor of the constant voltage generation circuit for keeping the sense contact at a constant potential, which is manufactured under the same manufacturing conditions as the memory transistor, it is possible to provide a semiconductor static memory device with a large design margin. can. Note that although n-channel has been described in the embodiment, the present invention can be similarly applied to p-channel.

In addition, in the embodiment, the charging transistor 14 and the transfer gate transistor 15 are of type B whose threshold value is not OV, but they may also be of type B. E type transistor 62
can be excluded in principle. In addition, this invention can be modified and implemented in various ways without departing from its spirit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional MOS type BPROM output circuit, and FIG. 2 is a MOS type E according to an embodiment of the present invention.
FIG. 3 is a diagram showing the configuration of the PROM, and is a diagram showing a modification of the constant voltage generating circuit section. 11...Memory cell array, 13...Sense node, 14...Charging transistor, 16.
... Constant voltage generation circuit, 16. ...O-type first MOS transistor, 162 ...E-type buffer MOS transistor, 163 ...E-type second MOS transistor. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1 A memory cell array in which MOS type memory transistors with floating gates are arranged, a charging MOS transistor that charges the sense contact of this array, and this charging MOS
1. A semiconductor static memory device comprising a constant voltage generation circuit that applies a constant voltage independent of a power supply voltage to the gate of an S transistor.