JPS6027257A - Communication control equipment - Google Patents

Abstract

PURPOSE:To improve the efficiency of line storage by applying a scanning number storage part as a generating part of scanning line numbers to make it possible to use sequential numbers in a piece of equipment which controls data communication lines different in speed. CONSTITUTION:Information indicating the classification of an address conversion is inputted from an external circuit to a register 21, and the output of this register 21 and the output of a binary counter 22 are used as addresses to read out the contents of a scanning number storage part 26. Scanning line numbers are stored for every classification of address conversion in this storage part 26, it is checked whether serial-parallel converting circuits 3010-3013 having the read-out output number have a processing request or not. The contents of the binary counter 22 are counted up by an update indication, and one bit of the output of the storage part 26 indicates initialization of the binary counter 22.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention provides control over multiple data communication lines at different speeds.
The present invention relates to a communication control device.

<Prior Art> A conventional device of this type is provided with a serial-to-parallel conversion circuit corresponding to the line, which converts bit serial data on the line into parallel data (characters) handled within the communication control device. Each time a character is received or transmitted, the serial/parallel conversion circuit outputs a one character reception indication or a next transmission character request indication (processing request). The control circuit of
If one character is received, one character is read from the serial/parallel conversion circuit and transferred to the memory, and if the next transmission character is requested, the next transmission (i data is read out from the memory and transferred to the serial/parallel conversion circuit). By repeating this operation, data can be sent and received correctly to and from the data communication line.

By the way, data i! has multiple different communication speeds. ! 11
When controlling a high-speed line, the output interval of the single character reception display or transmission character request display from the serial-to-parallel conversion circuit is shorter on a high-speed line than on a low-speed line. The processing requirements of the conversion circuit must be checked frequently.

There are two ways to check this processing request: an interrupt method that interrupts the control circuit when a processing request occurs in the serial-to-parallel converter circuit, and another method in which the control circuit issues a processing request to the serial-to-parallel converter circuit for all lines at regular intervals. There is a scanning method that checks the presence or absence of each individual item. Since the present invention relates to checking processing requests using a scanning method, a description of the interrupt method will be omitted hereafter.

+) When checking iJ processing requests using the scanning method, the line speed should be, for example, 9,600 bits per second (9,600 bits per second).
0 bps) line and 1,200 bits per second (1,200 bps)
9,600 bps)
For bpS lines, the serial-to-parallel conversion circuit is eight times faster than for 1,200bps lines.
゛You have to check for nothing. Conventionally, as a method for accommodating high-speed lines, there is a method of limiting the number of accommodated lines (scanning restriction method). For example, in a communication control device with a capacity of 1.200 bps64 line, 9,600 bps
When accommodating a pS line, it is necessary to check the 9,600 bl) S line at 8 times the speed of the 1,200 bl)
can only be accommodated in line numbers (for example, numbers 0 to 7). In this case, even if only one 9,600bps line is accommodated, the control circuit also has L200bps20
Although it had the capacity to process 0 bps line segments, it had the drawback of being able to accommodate only the remaining seven lines.

As a method for solving this drawback, there is an address replacement method in which when a certain line number comes in the scanning order, that line number is converted to a number for a high-speed line. For example, this method uses 9,6
001) When the 931 line is accommodated in line 0, when the scanning order reaches number 8j (j=1 to 7) among the line numbers 1 to 63, that number is replaced with number 0. In this system, if only one 9,600bpS line is accommodated, 7 out of 64 lines will be unusable (
8゜16.24, 32, 40, 48.56) only, if accommodating two lines of 9,600 bps, use 8J and 8
14 lines j+1 (j=1 to 7) become unusable. In this way, in the address substitution method, there is a gap in usable line numbers.

By the way, the printed circuit board (line adapter) that accommodates the parallel conversion circuit and the direct line interface generally accommodates 2.4 or 8 lines per board, and the line number inside the line adapter corresponds to the circuit of the line adapter. Due to the structure, consecutive numbers are assigned) 1! I am a connoisseur. Therefore, the fffiJ address replacement method has the disadvantage that the serial/parallel conversion circuit, etc. in the line adapter corresponding to the line number where the omission occurs is not used, resulting in poor usage efficiency. Another drawback is that the conversion circuit for address replacement corresponding to the number of high 1/10111 lines accommodated or the speed type becomes complicated, and when the number of address replacement modes is increased, the hardware hX increases significantly. Furthermore, the address substitution formula is the base theory P1! If the address substitution formula f: is made with the following formula, there is a drawback that if it becomes necessary to change the address substitution formula, the circuit must be redesigned. Some conventional communication control devices combine the above two methods to set multiple scanning patterns.
Although some of them are considered J-Noh, they do not really solve the problem.

<Summary of the Invention> The object of the present invention is to be able to use the processing power of a control circuit, to prevent line numbers from being dropped in the middle, and to use lines with consecutive numbers. To provide a communication control device that is efficient in the use of a line adapter, has high power and high speed, and can be configured with a simple hardware address 1z (exchanged to l1i) corresponding to the number of lines accommodated and the speed type. There is a particular thing.

According to this invention, information indicating the type of address conversion is manually stored in a register from an external circuit, and the storage section is read out using the output of this register and llj no J of the kuinary counter as an address. A scanning line number is stored for each address conversion type, and it is checked whether or not there is a processing request for the serial/parallel conversion circuit of the read output number. and one bit of the output of the storage section is taken as an initialization instruction for the inary counter.

<Embodiment> FIG. 1 shows an embodiment of the present invention, in which a host device 1 has a
1fa it;'I + push device 2 is connected, a scanning mode holding register 21.6 bit binary counter 22 is connected to the control circuit 20 in the communication control device 2,
The binary counter 22 can provide a reset signal from the control circuit 2o to the reset input terminal 24 of the binary counter 22 through a reset signal line 23, and the control circuit 20 can provide a power counter update signal to the binary counter 22 through a line 25. can. Scan number storage unit 26
is a readable memory in which scanning line numbers are stored for each type of address conversion, and the outputs of the register 21 and the binary counter 22 are read out as the address input 261. The running 1f number 262 is output from the storage unit 26. 111 loading/reading into the storage unit 26 (111 from the control circuit 2° required when applying 7 memories)
) included data signal lines and address signal lines are omitted. The lower 2 bits of the scan number 262 read out, and the address for 4 lines of serial/parallel conversion quotient 3'01, are supplied to the address signal line 27, excluding the lower 2 bits and the upper 1 bit of the scan number 262. The bits are supplied to a decoding circuit 28 for distinguishing the line adapter 30, and the upper one bit of the scan number 262 is supplied to the reset input terminal 24 of the binary counter 22 through a reset signal line 29. Each of the line adapters 301 to 308 in FIG. 2 shows the type of scanning mode, its code (set in the register 21), the accommodated (scanning target) line number, the accommodated line speed, the number of accommodated lines, and the scanning number storage section. The scan number generation formula set to 26 is shown below.

In this embodiment, four scanning modes are provided.

The scanning number generation formula is the output of the binary counter 22
When X2X1Xo is the address of the storage unit 26, it indicates the data stored in the storage unit 26, and is Xo &"i acid - F position pip) (LSB). The scan mode code is set in the scan mode holding register 21. If all 1,200 bps lines are accommodated, the number of accommodated lines is 32, so if 4 lines of 4,800 bf)S are accommodated, 7800 bps [1,200 bps of 4 lines] Therefore, the number that can accommodate l,200bpS lines is 32-4X4=16.

FIG. 3 shows an example of the memory contents of the 12th examination number imperial memory section 26,
The 6th bit (upper 1 bit) of the output indicates reset instruction information to the binary counter 22, and output bits 5 to 1 indicate the scanning line number. In mode 0, the output of the binary counter 22 is x5x4x8x2x as shown by the scanning number generation formula in FIG.

The lower order x4x8x2x of xo is stored as is, and a line scanning number of 32 is assigned. In mode 1 rJ: x, 4,80 for X2X1 when = o
A scan number for a line of 0 bps is assigned. In other words, the values 00, 01, 10, 11 representing each X2X are stored for frame palaces 0, 2, 4, and 6. Below, similar M 3s are stored at addresses 8.10 and 12.14, respectively. 4,800
b p s c7) The line scanning number' is O'+ 1,
Four lines 2 and 3 are assigned, and the same line number of the 4,800 bps line is read every time the address advances by 8, so the same line number is read out at 32/8 = 4 times the speed of the 1,200 bps line. . On the other hand, the address is X for a 1,200bpS line. When = 1, address X4X
The scan number is 0100 added to 3X2X1, so 4=OO for addresses 1, 3.5...
100゜5=00101.6=OO110,...
・ is the scanning number. That is 1,200bl)
Sixteen lines with running numbers 4 to 19 are assigned to the S line. The storage section 26 is used by being divided into four memory areas corresponding to four scanning modes. Item 41- is a map of the scanning number storage section, and the contents of FIG. 3 are used for each of the fourth factors. It is set in the corresponding area.

An example of operation is as follows. The control circuit 20 is the host device 1
When a scanning mode (for example, mode 1) is instructed from (one of the four scanning modes provided by the communication control device 2 is selected), 01 is stored in the scanning mode holding register 22. ” and set binary counter 2
2 is cleared through the reset signal line 23. Then, the binary counter 22 outputs all O's, so
Run 111-Syllabary (, i'1 part 26 address human power 26
1 becomes "01000000". Open side j circuit 20
When reading out the processing request display of the serial/parallel converter circuit 301, the input address "010000" from FIG.
00'', therefore (the content of the main note 'IA81°?B26 is all O's, and all 0's are output to the output 262 of note '1:'51 302 selects the serial/parallel conversion circuit of the line adapter 301 corresponding to line 0; Loaded into Raku 20.

Control II] 11 The circuit 20 checks the read processing request display, and if the one-character reception display is (5', ', ', for example, it issues a manual command to read the received fit data. Therefore, the received data can be read from the selected serial/parallel converter circuit 301o in the same way as described in 1'.The control circuit 20 sends the received data to the host device and performs the running of the current time i-♀. Finish the process.Next, control circuit 2
0 outputs a counter update signal to the line 25, updates the binary counter 22 (+1), and moves on to the next line scanning process. As a result of checking the read processing request display, if there is no processing request, the scanning processing for the line in question is terminated.

By updating the binary counter 22, the storage unit 2
6 address input 262 is “01000001”, the corresponding content from the storage unit 26” o o o i
o o''' is output.The control circuit 20 processes 1.ll
When the manual command to display the i request is issued, the 4th line is selected this time in the same path i#3 as in ff1iJ, and the contents of the corresponding serial/parallel conversion circuit are read.

As a result of sequentially updating the binary counter 22 as described above, when the hit 6 output from the scanning number storage unit 26 is 1'1'', the reset signal line 29 of the pinarino Junk 22 becomes significant, and the hit 6 becomes 1. When a binary counter history update instruction is issued from the control circuit 20 after the scanning processing path r of the line number of the output of the storage unit 26, which is ``, the binary counter 22 is cleared, so that scanning restarts from line 0. Thereafter, the above process is repeated. The same applies to cases where other scanning modes are set.

(7) Real 1 jil! t'/lJteIr, J, /I,
800 bps line and (1, January 2001)
j. I-mixing also wastes the capacity of communication control equipment1
It is possible to accommodate a maximum number of lines (1-1) with advantage. Also, read out the scanning number storage unit 26.
~ i + j function memory (RAM) J: ,! l
) The user can specify the speed mixed conditions of this +111 communication control device,
Processing capacity 11.[Jl Sendai can be set arbitrarily. In the above, C11,l,':' is assigned from the high-speed line number 0, but it is also possible to assign 'J' S: I'l before scanning C\\, and it is shown in Figure 2. Yoshi rub and run 1
! It is easy to generate a 'F' title.

<Effect> As explained above, the scanning line number is written in one place,
・;"In order to accommodate a mixture of lines of different speeds, it is possible to increase the flexibility of the scanning line number) by changing the scanning line number to 0 in a <fill 1111 device. Without passing number 219 in the number raline,
It has the advantage that consecutive numbers can be used, line accommodation efficiency can be improved, and the honeycomb is simple.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing types of scanning modes and an example of a scanning number generation formula,
Figure 3 shows scanning numbers corresponding to the scanning mode in Figure 2.
1: A diagram showing the contents of the i section 26. FIG. 4 is a diagram showing a map of the storage section 26. 1: Host device, 2: 1r14 signal control device, 20: Control circuit, 21: Scan mode face register, 22: Binary counter, 23: Reset signal line, 24: Reset manually, 25: Binary counter (1,! □New 1 word, 2
6: Scan number recording section, 26 [Near address input terminal, 2
62: Output of 26, 27: Address signal line of serial/parallel conversion circuit, 28: Decode circuit for line adapter, 29: Reset signal 11'h %30: Line adapter (301 to 3
08), 301: Serial to parallel conversion circuit (301o to 3013
), 302: decoding circuit. ! 11 permission 1I! 2 people [1 Telegraph and Telephone Corporation agent]
Takashi Kusano

Claims (1)

[Claims] (1) Multiple data] In a communication control device that detects the presence or absence of a processing request from a serial-to-parallel conversion circuit provided for each m rented line by scanning each line, the external l'', 1 i1
1v information indicating the address conversion type manually input from '8.
a binary counter that is incremented by an update instruction and shifted by an initialization instruction;
The scanning line number for each address conversion type is recorded.
The outputs of the 'liJ register and the own iJ binary counter are read out as addresses, the number of the serial/parallel converter circuit is outputted, and one bit of the output is sent to the binary counter: 01 communication control device characterized by comprising: